Set ips dividor to 1/4 of csb clock.

Previous setting cause ips clock to be out of spec. This bug was found by John
Rigby from Freescale.

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>

diff --git a/include/mpc512x.h b/include/mpc512x.h
index a06b5c6502634ebb9bf5c235aad104bfaf189d58..d1c6fb29f635159bb3b13bf54272223ef967c34b 100644 (file)
--- a/include/mpc512x.h
+++ b/include/mpc512x.h
@@ -185,7 +185,7 @@
 
 /* SCFR1 System Clock Frequency Register 1
  */
-#define SCFR1_IPS_DIV                  0x2
+#define SCFR1_IPS_DIV                  0x4
 #define SCFR1_IPS_DIV_MASK             0x03800000
 #define SCFR1_IPS_DIV_SHIFT            23