status = "okay";
};
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2_0>;
+ status = "okay";
+
+ eeprom@50{
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ power-domains = <&power K1X_PMU_DUMMY_PWR_DOMAIN>;
+ status = "okay";
+
+ mac_address0: mac_address0@0 {
+ reg = <0x0 6>;
+ };
+
+ mac_address1: mac_address1@6 {
+ reg = <0x6 6>;
+ };
+ };
+
+ es8326: es8326@19{
+ compatible = "everest,es8326";
+ reg = <0x19>;
+ #sound-dai-cells = <0>;
+ interrupt-parent = <&gpio>;
+ interrupts = <126 1>;
+ spk-ctl-gpio = <&gpio 127 0>;
+ everest,mic1-src = [44];
+ everest,mic2-src = [66];
+ status = "okay";
+ };
+};
+
&i2c8 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c8>;
>;
};
+ð0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gmac0>;
+
+ emac,reset-gpio = <&gpio 110 0>;
+ emac,reset-active-low;
+ emac,reset-delays-us = <0 10000 100000>;
+
+ /* store forward mode */
+ tx-threshold = <1518>;
+ rx-threshold = <12>;
+ tx-ring-num = <1024>;
+ rx-ring-num = <1024>;
+ dma-burst-len = <5>;
+
+ ref-clock-from-phy;
+
+ clk-tuning-enable;
+ clk-tuning-by-delayline;
+ tx-phase = <60>;
+ rx-phase = <73>;
+
+ nvmem-cells = <&mac_address0>;
+ nvmem-cell-names = "mac-address";
+
+ phy-handle = <&rgmii0>;
+
+ status = "okay";
+
+ mdio-bus {
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ rgmii0: phy@0 {
+ compatible = "ethernet-phy-id001c.c916";
+ device_type = "ethernet-phy";
+ reg = <0x1>;
+ phy-mode = "rgmii";
+ };
+ };
+};
+
+ð1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gmac1>;
+
+ emac,reset-gpio = <&gpio 115 0>;
+ emac,reset-active-low;
+ emac,reset-delays-us = <0 10000 100000>;
+
+ /* store forward mode */
+ tx-threshold = <1518>;
+ rx-threshold = <12>;
+ tx-ring-num = <1024>;
+ rx-ring-num = <1024>;
+ dma-burst-len = <5>;
+
+ ref-clock-from-phy;
+
+ clk-tuning-enable;
+ clk-tuning-by-delayline;
+ tx-phase = <90>;
+ rx-phase = <73>;
+ nvmem-cells = <&mac_address1>;
+ nvmem-cell-names = "mac-address";
+
+ phy-handle = <&rgmii1>;
+
+ status = "okay";
+
+ mdio-bus {
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ rgmii1: phy@1 {
+ compatible = "ethernet-phy-id001c.c916";
+ device_type = "ethernet-phy";
+ reg = <0x1>;
+ phy-mode = "rgmii";
+ };
+ };
+};
+
/* SD */
&sdhci0 {
pinctrl-names = "default","fast";
mmc0 = &sdhci0;
mmc1 = &sdhci1;
mmc2 = &sdhci2;
-
+ ethernet0 = ð0;
+ ethernet1 = ð1;
};
cpus {
status = "ok";
};
+ i2c2: i2c@d4012000 {
+ compatible = "spacemit,k1x-i2c";
+ spacemit,adapter-id = <2>;
+ reg = <0x0 0xd4012000 0x0 0x38>;
+ /* usually i2c client has only 1 reg field */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&plic>;
+ interrupts = <38>;
+ clocks = <&ccu CLK_TWSI2>;
+ resets = <&reset RESET_TWSI2>;
+ /*
+ dmas = <&pdma0 DMA_I2C2_RX 1
+ &pdma0 DMA_I2C2_TX 1>;
+ dma-names = "rx", "tx";
+ */
+ spacemit,dma-disable;
+ spacemit,i2c-fast-mode;
+ /* spacemit,i2c-high-mode; */
+ spacemit,i2c-master-code = /bits/ 8 <0x0e>;
+ spacemit,i2c-clk-rate = <32000000>;
+ spacemit,i2c-lcr = <0x82c469f>;
+ spacemit,i2c-wcr = <0x142a>;
+ /* apb clock: 26MHz or 52MHz */
+ spacemit,apb_clock = <52000000>;
+ power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
+ cpuidle,pm-runtime,sleep;
+ interconnects = <&dram_range0>;
+ interconnect-names = "dma-mem";
+ status = "disabled";
+ };
i2c8: i2c@d401d800 {
compatible = "spacemit,k1x-i2c";
status = "okay";
};
+ /* dram mapping for vpu/gpu/v2d/jpu for ex. */
+ dram_range1: dram_range@1 {
+ compatible = "spacemit-dram-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,
+ <0x0 0x80000000 0x1 0x00000000 0x3 0x80000000>;
+ #interconnect-cells = <0>;
+ status = "okay";
+ };
+
+
pinctrl: pinctrl@d401e000 {
compatible = "pinconf-single";
reg = <0x0 0xd401e000 0x0 0x400>;
};
};
+ eth0: ethernet@cac80000 {
+ compatible = "spacemit,k1x-emac";
+ reg = <0x00000000 0xCAC80000 0x00000000 0x00000420>;
+ k1x,apmu-base-reg = <0xD4282800>;
+ ctrl-reg = <0x3e4>;
+ dline-reg = <0x3e8>;
+ clocks = <&ccu CLK_EMAC0_BUS>,
+ <&ccu CLK_EMAC0_PTP>;
+ clock-names = "emac-clk", "ptp-clk";
+ resets = <&reset RESET_EMAC0>;
+ reset-names = "emac-reset";
+ interrupts = <131>;
+ interrupt-parent = <&plic>;
+ mac-address = [ 00 00 00 00 00 00 ];
+ ptp-support;
+ ptp-clk-rate = <10000000>;
+ power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
+ clk,pm-runtime,no-sleep;
+ cpuidle,pm-runtime,sleep;
+ interconnects = <&dram_range1>;
+ interconnect-names = "dma-mem";
+ status = "disabled";
+ };
+
+ eth1: ethernet@cac81000 {
+ compatible = "spacemit,k1x-emac";
+ reg = <0x00000000 0xCAC81000 0x00000000 0x00000420>;
+ k1x,apmu-base-reg = <0xD4282800>;
+ ctrl-reg = <0x3ec>;
+ dline-reg = <0x3f0>;
+ clocks = <&ccu CLK_EMAC1_BUS>,
+ <&ccu CLK_EMAC1_PTP>;
+ clock-names = "emac-clk", "ptp-clk";
+ resets = <&reset RESET_EMAC1>;
+ reset-names = "emac-reset";
+ interrupts = <133>;
+ interrupt-parent = <&plic>;
+ mac-address = [ 00 00 00 00 00 00 ];
+ ptp-support;
+ ptp-clk-rate = <10000000>;
+ power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
+ clk,pm-runtime,no-sleep;
+ cpuidle,pm-runtime,sleep;
+ interconnects = <&dram_range1>;
+ interconnect-names = "dma-mem";
+ status = "disabled";
+ };
+
+
pmu: power-management@0 {
compatible = "simple-bus";
#address-cells = <2>;