MIPS: Delete unused flush_cache_sigtramp()

Commit adcc81f148d7 ("MIPS: math-emu: Write-protect delay slot emulation
pages") left flush_cache_sigtramp() unused. Delete the dead code.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Davidlohr Bueso <dave@stgolabs.net>
Cc: linux-mips@vger.kernel.org

diff --git a/arch/mips/include/asm/cacheflush.h b/arch/mips/include/asm/cacheflush.h
index 4812d1f..d687b40 100644 (file)
--- a/arch/mips/include/asm/cacheflush.h
+++ b/arch/mips/include/asm/cacheflush.h
@@ -25,7 +25,6 @@
  *
  * MIPS specific flush operations:
  *
- *  - flush_cache_sigtramp() flush signal trampoline
  *  - flush_icache_all() flush the entire instruction cache
  *  - flush_data_cache_page() flushes a page from the data cache
  *  - __flush_icache_user_range(start, end) flushes range of user instructions
@@ -110,7 +109,6 @@ extern void copy_from_user_page(struct vm_area_struct *vma,
        struct page *page, unsigned long vaddr, void *dst, const void *src,
        unsigned long len);
 
-extern void (*flush_cache_sigtramp)(unsigned long addr);
 extern void (*flush_icache_all)(void);
 extern void (*local_flush_data_cache_page)(void * addr);
 extern void (*flush_data_cache_page)(unsigned long addr);

diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c
index 0e45b06..8064821 100644 (file)
--- a/arch/mips/mm/c-octeon.c
+++ b/arch/mips/mm/c-octeon.c
@@ -128,23 +128,6 @@ static void octeon_flush_icache_range(unsigned long start, unsigned long end)
 
 
 /**
- * Flush the icache for a trampoline. These are used for interrupt
- * and exception hooking.
- *
- * @addr:   Address to flush
- */
-static void octeon_flush_cache_sigtramp(unsigned long addr)
-{
-       struct vm_area_struct *vma;
-
-       down_read(&current->mm->mmap_sem);
-       vma = find_vma(current->mm, addr);
-       octeon_flush_icache_all_cores(vma);
-       up_read(&current->mm->mmap_sem);
-}
-
-
-/**
  * Flush a range out of a vma
  *
  * @vma:    VMA to flush
@@ -289,7 +272,6 @@ void octeon_cache_init(void)
        flush_cache_mm                  = octeon_flush_cache_mm;
        flush_cache_page                = octeon_flush_cache_page;
        flush_cache_range               = octeon_flush_cache_range;
-       flush_cache_sigtramp            = octeon_flush_cache_sigtramp;
        flush_icache_all                = octeon_flush_icache_all;
        flush_data_cache_page           = octeon_flush_data_cache_page;
        flush_icache_range              = octeon_flush_icache_range;

diff --git a/arch/mips/mm/c-r3k.c b/arch/mips/mm/c-r3k.c
index 01848cd..0ca401d 100644 (file)
--- a/arch/mips/mm/c-r3k.c
+++ b/arch/mips/mm/c-r3k.c
@@ -274,30 +274,6 @@ static void r3k_flush_data_cache_page(unsigned long addr)
 {
 }
 
-static void r3k_flush_cache_sigtramp(unsigned long addr)
-{
-       unsigned long flags;
-
-       pr_debug("csigtramp[%08lx]\n", addr);
-
-       flags = read_c0_status();
-
-       write_c0_status(flags&~ST0_IEC);
-
-       /* Fill the TLB to avoid an exception with caches isolated. */
-       asm(    "lw\t$0, 0x000(%0)\n\t"
-               "lw\t$0, 0x004(%0)\n\t"
-               : : "r" (addr) );
-
-       write_c0_status((ST0_ISC|ST0_SWC|flags)&~ST0_IEC);
-
-       asm(    "sb\t$0, 0x000(%0)\n\t"
-               "sb\t$0, 0x004(%0)\n\t"
-               : : "r" (addr) );
-
-       write_c0_status(flags);
-}
-
 static void r3k_flush_kernel_vmap_range(unsigned long vaddr, int size)
 {
        BUG();
@@ -331,7 +307,6 @@ void r3k_cache_init(void)
 
        __flush_kernel_vmap_range = r3k_flush_kernel_vmap_range;
 
-       flush_cache_sigtramp = r3k_flush_cache_sigtramp;
        local_flush_data_cache_page = local_r3k_flush_data_cache_page;
        flush_data_cache_page = r3k_flush_data_cache_page;
 

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index cc4e17c..5166e38 100644 (file)
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -937,119 +937,6 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
 }
 #endif /* CONFIG_DMA_NONCOHERENT */
 
-struct flush_cache_sigtramp_args {
-       struct mm_struct *mm;
-       struct page *page;
-       unsigned long addr;
-};
-
-/*
- * While we're protected against bad userland addresses we don't care
- * very much about what happens in that case.  Usually a segmentation
- * fault will dump the process later on anyway ...
- */
-static void local_r4k_flush_cache_sigtramp(void *args)
-{
-       struct flush_cache_sigtramp_args *fcs_args = args;
-       unsigned long addr = fcs_args->addr;
-       struct page *page = fcs_args->page;
-       struct mm_struct *mm = fcs_args->mm;
-       int map_coherent = 0;
-       void *vaddr;
-
-       unsigned long ic_lsize = cpu_icache_line_size();
-       unsigned long dc_lsize = cpu_dcache_line_size();
-       unsigned long sc_lsize = cpu_scache_line_size();
-
-       /*
-        * If owns no valid ASID yet, cannot possibly have gotten
-        * this page into the cache.
-        */
-       if (!has_valid_asid(mm, R4K_HIT))
-               return;
-
-       if (mm == current->active_mm) {
-               vaddr = NULL;
-       } else {
-               /*
-                * Use kmap_coherent or kmap_atomic to do flushes for
-                * another ASID than the current one.
-                */
-               map_coherent = (cpu_has_dc_aliases &&
-                               page_mapcount(page) &&
-                               !Page_dcache_dirty(page));
-               if (map_coherent)
-                       vaddr = kmap_coherent(page, addr);
-               else
-                       vaddr = kmap_atomic(page);
-               addr = (unsigned long)vaddr + (addr & ~PAGE_MASK);
-       }
-
-       R4600_HIT_CACHEOP_WAR_IMPL;
-       if (!cpu_has_ic_fills_f_dc) {
-               if (dc_lsize)
-                       vaddr ? flush_dcache_line(addr & ~(dc_lsize - 1))
-                             : protected_writeback_dcache_line(
-                                                       addr & ~(dc_lsize - 1));
-               if (!cpu_icache_snoops_remote_store && scache_size)
-                       vaddr ? flush_scache_line(addr & ~(sc_lsize - 1))
-                             : protected_writeback_scache_line(
-                                                       addr & ~(sc_lsize - 1));
-       }
-       if (ic_lsize)
-               vaddr ? flush_icache_line(addr & ~(ic_lsize - 1))
-                     : protected_flush_icache_line(addr & ~(ic_lsize - 1));
-
-       if (vaddr) {
-               if (map_coherent)
-                       kunmap_coherent();
-               else
-                       kunmap_atomic(vaddr);
-       }
-
-       if (MIPS4K_ICACHE_REFILL_WAR) {
-               __asm__ __volatile__ (
-                       ".set push\n\t"
-                       ".set noat\n\t"
-                       ".set "MIPS_ISA_LEVEL"\n\t"
-#ifdef CONFIG_32BIT
-                       "la     $at,1f\n\t"
-#endif
-#ifdef CONFIG_64BIT
-                       "dla    $at,1f\n\t"
-#endif
-                       "cache  %0,($at)\n\t"
-                       "nop; nop; nop\n"
-                       "1:\n\t"
-                       ".set pop"
-                       :
-                       : "i" (Hit_Invalidate_I));
-       }
-       if (MIPS_CACHE_SYNC_WAR)
-               __asm__ __volatile__ ("sync");
-}
-
-static void r4k_flush_cache_sigtramp(unsigned long addr)
-{
-       struct flush_cache_sigtramp_args args;
-       int npages;
-
-       down_read(&current->mm->mmap_sem);
-
-       npages = get_user_pages_fast(addr, 1, 0, &args.page);
-       if (npages < 1)
-               goto out;
-
-       args.mm = current->mm;
-       args.addr = addr;
-
-       r4k_on_each_cpu(R4K_HIT, local_r4k_flush_cache_sigtramp, &args);
-
-       put_page(args.page);
-out:
-       up_read(&current->mm->mmap_sem);
-}
-
 static void r4k_flush_icache_all(void)
 {
        if (cpu_has_vtag_icache)
@@ -1978,7 +1865,6 @@ void r4k_cache_init(void)
 
        __flush_kernel_vmap_range = r4k_flush_kernel_vmap_range;
 
-       flush_cache_sigtramp    = r4k_flush_cache_sigtramp;
        flush_icache_all        = r4k_flush_icache_all;
        local_flush_data_cache_page     = local_r4k_flush_data_cache_page;
        flush_data_cache_page   = r4k_flush_data_cache_page;
@@ -2033,7 +1919,6 @@ void r4k_cache_init(void)
                /* I$ fills from D$ just by emptying the write buffers */
                flush_cache_page = (void *)b5k_instruction_hazard;
                flush_cache_range = (void *)b5k_instruction_hazard;
-               flush_cache_sigtramp = (void *)b5k_instruction_hazard;
                local_flush_data_cache_page = (void *)b5k_instruction_hazard;
                flush_data_cache_page = (void *)b5k_instruction_hazard;
                flush_icache_range = (void *)b5k_instruction_hazard;
@@ -2052,7 +1937,6 @@ void r4k_cache_init(void)
                flush_cache_mm          = (void *)cache_noop;
                flush_cache_page        = (void *)cache_noop;
                flush_cache_range       = (void *)cache_noop;
-               flush_cache_sigtramp    = (void *)cache_noop;
                flush_icache_all        = (void *)cache_noop;
                flush_data_cache_page   = (void *)cache_noop;
                local_flush_data_cache_page     = (void *)cache_noop;

diff --git a/arch/mips/mm/c-tx39.c b/arch/mips/mm/c-tx39.c
index 5f6c099..b7c8a9d 100644 (file)
--- a/arch/mips/mm/c-tx39.c
+++ b/arch/mips/mm/c-tx39.c
@@ -290,25 +290,6 @@ static void tx39_dma_cache_inv(unsigned long addr, unsigned long size)
        }
 }
 
-static void tx39_flush_cache_sigtramp(unsigned long addr)
-{
-       unsigned long ic_lsize = current_cpu_data.icache.linesz;
-       unsigned long dc_lsize = current_cpu_data.dcache.linesz;
-       unsigned long config;
-       unsigned long flags;
-
-       protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
-
-       /* disable icache (set ICE#) */
-       local_irq_save(flags);
-       config = read_c0_conf();
-       write_c0_conf(config & ~TX39_CONF_ICE);
-       TX39_STOP_STREAMING();
-       protected_flush_icache_line(addr & ~(ic_lsize - 1));
-       write_c0_conf(config);
-       local_irq_restore(flags);
-}
-
 static __init void tx39_probe_cache(void)
 {
        unsigned long config;
@@ -368,7 +349,6 @@ void tx39_cache_init(void)
                flush_icache_range      = (void *) tx39h_flush_icache_all;
                local_flush_icache_range = (void *) tx39h_flush_icache_all;
 
-               flush_cache_sigtramp    = (void *) tx39h_flush_icache_all;
                local_flush_data_cache_page     = (void *) tx39h_flush_icache_all;
                flush_data_cache_page   = (void *) tx39h_flush_icache_all;
 
@@ -397,7 +377,6 @@ void tx39_cache_init(void)
 
                __flush_kernel_vmap_range = tx39_flush_kernel_vmap_range;
 
-               flush_cache_sigtramp = tx39_flush_cache_sigtramp;
                local_flush_data_cache_page = local_tx39_flush_data_cache_page;
                flush_data_cache_page = tx39_flush_data_cache_page;
 

diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index 55099fb..3da2169 100644 (file)
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -47,7 +47,6 @@ void (*__flush_kernel_vmap_range)(unsigned long vaddr, int size);
 EXPORT_SYMBOL_GPL(__flush_kernel_vmap_range);
 
 /* MIPS specific cache operations */
-void (*flush_cache_sigtramp)(unsigned long addr);
 void (*local_flush_data_cache_page)(void * addr);
 void (*flush_data_cache_page)(unsigned long addr);
 void (*flush_icache_all)(void);