drm/amd/pm: Enable GfxOff for Vangogh
authorJinzhou Su <Jinzhou.Su@amd.com>
Tue, 12 Jan 2021 03:33:13 +0000 (11:33 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 14 Jan 2021 04:52:22 +0000 (23:52 -0500)
Add Enable gfxoff for Vangogh during smu_post_init.
System will not enter GfxOff without allow message.

Signed-off-by: Jinzhou Su <Jinzhou.Su@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

index b279dbb..147efe1 100644 (file)
@@ -1119,6 +1119,7 @@ int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
        case CHIP_SIENNA_CICHLID:
        case CHIP_NAVY_FLOUNDER:
        case CHIP_DIMGREY_CAVEFISH:
+       case CHIP_VANGOGH:
                if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
                        return 0;
                if (enable)
index 7ac7a91..d264cab 100644 (file)
@@ -1535,12 +1535,20 @@ static int vangogh_post_smu_init(struct smu_context *smu)
 {
        struct amdgpu_device *adev = smu->adev;
        uint32_t tmp;
+       int ret = 0;
        uint8_t aon_bits = 0;
        /* Two CUs in one WGP */
        uint32_t req_active_wgps = adev->gfx.cu_info.number/2;
        uint32_t total_cu = adev->gfx.config.max_cu_per_sh *
                adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines;
 
+       /* allow message will be sent after enable message on Vangogh*/
+       ret = smu_cmn_send_smc_msg(smu, SMU_MSG_EnableGfxOff, NULL);
+       if (ret) {
+               dev_err(adev->dev, "Failed to Enable GfxOff!\n");
+               return ret;
+       }
+
        /* if all CUs are active, no need to power off any WGPs */
        if (total_cu == adev->gfx.cu_info.number)
                return 0;