drm/amd/display: clean up some inconsistent indentings

The indentation of statements in the same curly bracket should be
consistent.

Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1890
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1891
Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index eda646b..f26e080 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2151,8 +2151,8 @@ static int dcn10_align_pixel_clocks(struct dc *dc, int group_size,
                                dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
                                        dc->res_pool->dp_clock_source,
                                        grouped_pipes[i]->stream_res.tg->inst, &pclk);
-                                       grouped_pipes[i]->stream->timing.pix_clk_100hz =
-                                               pclk*get_clock_divider(grouped_pipes[i], false);
+                               grouped_pipes[i]->stream->timing.pix_clk_100hz =
+                                       pclk*get_clock_divider(grouped_pipes[i], false);
                                if (master == -1)
                                        master = i;
                        }
@@ -2199,14 +2199,14 @@ void dcn10_enable_vblanks_synchronization(
        if (master >= 0) {
                for (i = 0; i < group_size; i++) {
                        if (i != master && !grouped_pipes[i]->stream->has_non_synchronizable_pclk)
-                       grouped_pipes[i]->stream_res.tg->funcs->align_vblanks(
-                               grouped_pipes[master]->stream_res.tg,
-                               grouped_pipes[i]->stream_res.tg,
-                               grouped_pipes[master]->stream->timing.pix_clk_100hz,
-                               grouped_pipes[i]->stream->timing.pix_clk_100hz,
-                               get_clock_divider(grouped_pipes[master], false),
-                               get_clock_divider(grouped_pipes[i], false));
-                               grouped_pipes[i]->stream->vblank_synchronized = true;
+                               grouped_pipes[i]->stream_res.tg->funcs->align_vblanks(
+                                       grouped_pipes[master]->stream_res.tg,
+                                       grouped_pipes[i]->stream_res.tg,
+                                       grouped_pipes[master]->stream->timing.pix_clk_100hz,
+                                       grouped_pipes[i]->stream->timing.pix_clk_100hz,
+                                       get_clock_divider(grouped_pipes[master], false),
+                                       get_clock_divider(grouped_pipes[i], false));
+                       grouped_pipes[i]->stream->vblank_synchronized = true;
                }
                grouped_pipes[master]->stream->vblank_synchronized = true;
                DC_SYNC_INFO("Sync complete\n");