#define MTL_RXQ_DMA_MAP0 0x00000c30 /* queue 0 to 3 */
#define MTL_RXQ_DMA_MAP1 0x00000c34 /* queue 4 to 7 */
-#define MTL_RXQ_DMA_Q04MDMACH_MASK GENMASK(3, 0)
-#define MTL_RXQ_DMA_Q04MDMACH(x) ((x) << 0)
-#define MTL_RXQ_DMA_QXMDMACH_MASK(x) GENMASK(11 + (8 * ((x) - 1)), 8 * (x))
+#define MTL_RXQ_DMA_QXMDMACH_MASK(x) (0xf << 8 * (x))
#define MTL_RXQ_DMA_QXMDMACH(chan, q) ((chan) << (8 * (q)))
#define MTL_CHAN_BASE_ADDR 0x00000d00
void __iomem *ioaddr = hw->pcsr;
u32 value;
- if (queue < 4)
+ if (queue < 4) {
value = readl(ioaddr + MTL_RXQ_DMA_MAP0);
- else
- value = readl(ioaddr + MTL_RXQ_DMA_MAP1);
-
- if (queue == 0 || queue == 4) {
- value &= ~MTL_RXQ_DMA_Q04MDMACH_MASK;
- value |= MTL_RXQ_DMA_Q04MDMACH(chan);
- } else if (queue > 4) {
- value &= ~MTL_RXQ_DMA_QXMDMACH_MASK(queue - 4);
- value |= MTL_RXQ_DMA_QXMDMACH(chan, queue - 4);
- } else {
value &= ~MTL_RXQ_DMA_QXMDMACH_MASK(queue);
value |= MTL_RXQ_DMA_QXMDMACH(chan, queue);
- }
-
- if (queue < 4)
writel(value, ioaddr + MTL_RXQ_DMA_MAP0);
- else
+ } else {
+ value = readl(ioaddr + MTL_RXQ_DMA_MAP1);
+ value &= ~MTL_RXQ_DMA_QXMDMACH_MASK(queue - 4);
+ value |= MTL_RXQ_DMA_QXMDMACH(chan, queue - 4);
writel(value, ioaddr + MTL_RXQ_DMA_MAP1);
+ }
}
static void dwmac4_config_cbs(struct mac_device_info *hw,