arm64: dts: qcom: sc7280: add lpass lpi pin controller node

Add LPASS LPI pinctrl node required for Audio functionality on sc7280
based platforms.

Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1655108645-1517-4-git-send-email-quic_srivasam@quicinc.com

diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index acf407a..4461a07 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -367,6 +367,68 @@
        bias-disable;
 };
 
+&lpass_dmic01_clk {
+       drive-strength = <8>;
+       bias-disable;
+};
+
+&lpass_dmic01_clk_sleep {
+       drive-strength = <2>;
+};
+
+&lpass_dmic01_data {
+       bias-pull-down;
+};
+
+&lpass_dmic23_clk {
+       drive-strength = <8>;
+       bias-disable;
+};
+
+&lpass_dmic23_clk_sleep {
+       drive-strength = <2>;
+};
+
+&lpass_dmic23_data {
+       bias-pull-down;
+};
+
+&lpass_rx_swr_clk {
+       drive-strength = <2>;
+       slew-rate = <1>;
+       bias-disable;
+};
+
+&lpass_rx_swr_clk_sleep {
+       bias-pull-down;
+};
+
+&lpass_rx_swr_data {
+       drive-strength = <2>;
+       slew-rate = <1>;
+       bias-bus-hold;
+};
+
+&lpass_rx_swr_data_sleep {
+       bias-pull-down;
+};
+
+&lpass_tx_swr_clk {
+       drive-strength = <2>;
+       slew-rate = <1>;
+       bias-disable;
+};
+
+&lpass_tx_swr_clk_sleep {
+       bias-pull-down;
+};
+
+&lpass_tx_swr_data {
+       drive-strength = <2>;
+       slew-rate = <1>;
+       bias-bus-hold;
+};
+
 &mi2s1_data0 {
        drive-strength = <6>;
        bias-disable;

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 046aee0..735b95d 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -2224,6 +2224,98 @@
                        qcom,bcm-voters = <&apps_bcm_voter>;
                };
 
+               lpass_tlmm: pinctrl@33c0000 {
+                       compatible = "qcom,sc7280-lpass-lpi-pinctrl";
+                       reg = <0 0x033c0000 0x0 0x20000>,
+                               <0 0x03550000 0x0 0x10000>;
+                       qcom,adsp-bypass-mode;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       gpio-ranges = <&lpass_tlmm 0 0 15>;
+
+                       #clock-cells = <1>;
+
+                       lpass_dmic01_clk: dmic01-clk {
+                               pins = "gpio6";
+                               function = "dmic1_clk";
+                       };
+
+                       lpass_dmic01_clk_sleep: dmic01-clk-sleep {
+                               pins = "gpio6";
+                               function = "dmic1_clk";
+                       };
+
+                       lpass_dmic01_data: dmic01-data {
+                               pins = "gpio7";
+                               function = "dmic1_data";
+                       };
+
+                       lpass_dmic01_data_sleep: dmic01-data-sleep {
+                               pins = "gpio7";
+                               function = "dmic1_data";
+                       };
+
+                       lpass_dmic23_clk: dmic23-clk {
+                               pins = "gpio8";
+                               function = "dmic2_clk";
+                       };
+
+                       lpass_dmic23_clk_sleep: dmic23-clk-sleep {
+                               pins = "gpio8";
+                               function = "dmic2_clk";
+                       };
+
+                       lpass_dmic23_data: dmic23-data {
+                               pins = "gpio9";
+                               function = "dmic2_data";
+                       };
+
+                       lpass_dmic23_data_sleep: dmic23-data-sleep {
+                               pins = "gpio9";
+                               function = "dmic2_data";
+                       };
+
+                       lpass_rx_swr_clk: rx-swr-clk {
+                               pins = "gpio3";
+                               function = "swr_rx_clk";
+                       };
+
+                       lpass_rx_swr_clk_sleep: rx-swr-clk-sleep {
+                               pins = "gpio3";
+                               function = "swr_rx_clk";
+                       };
+
+                       lpass_rx_swr_data: rx-swr-data {
+                               pins = "gpio4", "gpio5";
+                               function = "swr_rx_data";
+                       };
+
+                       lpass_rx_swr_data_sleep: rx-swr-data-sleep {
+                               pins = "gpio4", "gpio5";
+                               function = "swr_rx_data";
+                       };
+
+                       lpass_tx_swr_clk: tx-swr-clk {
+                               pins = "gpio0";
+                               function = "swr_tx_clk";
+                       };
+
+                       lpass_tx_swr_clk_sleep: tx-swr-clk-sleep {
+                               pins = "gpio0";
+                               function = "swr_tx_clk";
+                       };
+
+                       lpass_tx_swr_data: tx-swr-data {
+                               pins = "gpio1", "gpio2", "gpio14";
+                               function = "swr_tx_data";
+                       };
+
+                       lpass_tx_swr_data_sleep: tx-swr-data-sleep {
+                               pins = "gpio1", "gpio2", "gpio14";
+                               function = "swr_tx_data";
+                       };
+               };
+
                gpu: gpu@3d00000 {
                        compatible = "qcom,adreno-635.0", "qcom,adreno";
                        reg = <0 0x03d00000 0 0x40000>,