#include <asm/errno.h>
#include <asm/byteorder.h>
#include <asm/arch/clk.h>
-#include <asm/arch/memory-map.h>
+#include <asm/arch/hardware.h>
#include "atmel_mci.h"
#ifndef CONFIG_SYS_MMC_CLK_OD
/* choose RMII or MII mode. This depends on the board */
#ifdef CONFIG_RMII
-#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
- defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) || \
- defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
+#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
+ defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) || \
+ defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \
+ defined(CONFIG_AT91SAM9XE)
macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN));
#else
macb_writel(macb, USRIO, 0);
#endif
#else
-#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
- defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) || \
- defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
+#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
+ defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) || \
+ defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \
+ defined(CONFIG_AT91SAM9XE)
macb_writel(macb, USRIO, MACB_BIT(CLKEN));
#else
macb_writel(macb, USRIO, MACB_BIT(MII));
#include <asm/io.h>
#include <asm/arch/clk.h>
-#include <asm/arch/memory-map.h>
-
-#if defined(CONFIG_USART0)
-# define USART_ID 0
-# define USART_BASE USART0_BASE
-#elif defined(CONFIG_USART1)
-# define USART_ID 1
-# define USART_BASE USART1_BASE
-#elif defined(CONFIG_USART2)
-# define USART_ID 2
-# define USART_BASE USART2_BASE
-#elif defined(CONFIG_USART3)
-# define USART_ID 3
-# define USART_BASE USART3_BASE
-#endif
+#include <asm/arch/hardware.h>
#include "atmel_usart.h"
void serial_setbrg(void)
{
- atmel_usart3_t *usart = (atmel_usart3_t*)USART_BASE;
+ atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
unsigned long divisor;
unsigned long usart_hz;
* Baud Rate = --------------
* 16 * CD
*/
- usart_hz = get_usart_clk_rate(USART_ID);
+ usart_hz = get_usart_clk_rate(CONFIG_USART_ID);
divisor = (usart_hz / 16 + gd->baudrate / 2) / gd->baudrate;
writel(USART3_BF(CD, divisor), &usart->brgr);
}
int serial_init(void)
{
- atmel_usart3_t *usart = (atmel_usart3_t*)USART_BASE;
+ atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
writel(USART3_BIT(RSTRX) | USART3_BIT(RSTTX), &usart->cr);
void serial_putc(char c)
{
- atmel_usart3_t *usart = (atmel_usart3_t*)USART_BASE;
+ atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
if (c == '\n')
serial_putc('\r');
int serial_getc(void)
{
- atmel_usart3_t *usart = (atmel_usart3_t*)USART_BASE;
+ atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
while (!(readl(&usart->csr) & USART3_BIT(RXRDY)))
WATCHDOG_RESET();
int serial_tstc(void)
{
- atmel_usart3_t *usart = (atmel_usart3_t*)USART_BASE;
+ atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
return (readl(&usart->csr) & USART3_BIT(RXRDY)) != 0;
}
#include <asm/io.h>
#include <asm/arch/clk.h>
-#include <asm/arch/memory-map.h>
+#include <asm/arch/hardware.h>
#include "atmel_spi.h"
switch (bus) {
case 0:
- regs = (void *)SPI0_BASE;
+ regs = (void *)ATMEL_BASE_SPI0;
break;
-#ifdef SPI1_BASE
+#ifdef ATMEL_BASE_SPI1
case 1:
- regs = (void *)SPI1_BASE;
+ regs = (void *)ATMEL_BASE_SPI1;
break;
#endif
-#ifdef SPI2_BASE
+#ifdef ATMEL_BASE_SPI2
case 2:
- regs = (void *)SPI2_BASE;
+ regs = (void *)ATMEL_BASE_SPI2;
break;
#endif
-#ifdef SPI3_BASE
+#ifdef ATMEL_BASE_SPI3
case 3:
- regs = (void *)SPI3_BASE;
+ regs = (void *)ATMEL_BASE_SPI3;
break;
#endif
default: