x86: Don't touch IA32_APIC_BASE MSR on Intel Quark

Intel Quark processor core provides an integrated Local APIC but
does not support the IA32_APIC_BASE MSR. As a result, the Local
APIC is always globally enabled and the Local APIC base address
is fixed at 0xfee00000. Attempting to access the IA32_APIC_BASE
MSR causes a general protection fault.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/cpu/lapic.c b/arch/x86/cpu/lapic.c
index 30d2313..dbb32c4 100644 (file)
--- a/arch/x86/cpu/lapic.c
+++ b/arch/x86/cpu/lapic.c
@@ -65,23 +65,27 @@ void lapic_write(unsigned long reg, unsigned long v)
 
 void enable_lapic(void)
 {
-       msr_t msr;
-
-       msr = msr_read(MSR_IA32_APICBASE);
-       msr.hi &= 0xffffff00;
-       msr.lo |= MSR_IA32_APICBASE_ENABLE;
-       msr.lo &= ~MSR_IA32_APICBASE_BASE;
-       msr.lo |= LAPIC_DEFAULT_BASE;
-       msr_write(MSR_IA32_APICBASE, msr);
+       if (!IS_ENABLED(CONFIG_INTEL_QUARK)) {
+               msr_t msr;
+
+               msr = msr_read(MSR_IA32_APICBASE);
+               msr.hi &= 0xffffff00;
+               msr.lo |= MSR_IA32_APICBASE_ENABLE;
+               msr.lo &= ~MSR_IA32_APICBASE_BASE;
+               msr.lo |= LAPIC_DEFAULT_BASE;
+               msr_write(MSR_IA32_APICBASE, msr);
+       }
 }
 
 void disable_lapic(void)
 {
-       msr_t msr;
+       if (!IS_ENABLED(CONFIG_INTEL_QUARK)) {
+               msr_t msr;
 
-       msr = msr_read(MSR_IA32_APICBASE);
-       msr.lo &= ~MSR_IA32_APICBASE_ENABLE;
-       msr_write(MSR_IA32_APICBASE, msr);
+               msr = msr_read(MSR_IA32_APICBASE);
+               msr.lo &= ~MSR_IA32_APICBASE_ENABLE;
+               msr_write(MSR_IA32_APICBASE, msr);
+       }
 }
 
 unsigned long lapicid(void)