arm64: dts: ti: k3-j7200-main: Add PCIe device tree node

Add PCIe device tree node (both RC and EP) for the single PCIe
instance present in j7200.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20210105151421.23237-5-kishon@ti.com

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index fbe4cd1..4e39f03 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -594,6 +594,54 @@
                };
        };
 
+       pcie1_rc: pcie@2910000 {
+               compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
+               reg = <0x00 0x02910000 0x00 0x1000>,
+                     <0x00 0x02917000 0x00 0x400>,
+                     <0x00 0x0d800000 0x00 0x00800000>,
+                     <0x00 0x18000000 0x00 0x00001000>;
+               reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+               interrupt-names = "link_state";
+               interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
+               device_type = "pci";
+               ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
+               max-link-speed = <3>;
+               num-lanes = <4>;
+               power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 240 6>;
+               clock-names = "fck";
+               #address-cells = <3>;
+               #size-cells = <2>;
+               bus-range = <0x0 0xf>;
+               cdns,no-bar-match-nbits = <64>;
+               vendor-id = /bits/ 16 <0x104c>;
+               device-id = /bits/ 16 <0xb00f>;
+               msi-map = <0x0 &gic_its 0x0 0x10000>;
+               dma-coherent;
+               ranges = <0x01000000 0x0 0x18001000  0x00 0x18001000  0x0 0x0010000>,
+                        <0x02000000 0x0 0x18011000  0x00 0x18011000  0x0 0x7fef000>;
+               dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+       };
+
+       pcie1_ep: pcie-ep@2910000 {
+               compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep";
+               reg = <0x00 0x02910000 0x00 0x1000>,
+                     <0x00 0x02917000 0x00 0x400>,
+                     <0x00 0x0d800000 0x00 0x00800000>,
+                     <0x00 0x18000000 0x00 0x08000000>;
+               reg-names = "intd_cfg", "user_cfg", "reg", "mem";
+               interrupt-names = "link_state";
+               interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
+               ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
+               max-link-speed = <3>;
+               num-lanes = <4>;
+               power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 240 6>;
+               clock-names = "fck";
+               max-functions = /bits/ 8 <6>;
+               dma-coherent;
+       };
+
        usbss0: cdns-usb@4104000 {
                compatible = "ti,j721e-usb";
                reg = <0x00 0x4104000 0x00 0x100>;