#include "ir/function.hpp"
#include "sys/cvar.hpp"
#include <cstring>
+#include <iostream>
+#include <iomanip>
namespace gbe
{
genKernel->insnNum = p->store.size();
genKernel->insns = GBE_NEW_ARRAY_NO_ARG(GenInstruction, genKernel->insnNum);
std::memcpy(genKernel->insns, &p->store[0], genKernel->insnNum * sizeof(GenInstruction));
- if (OCL_OUTPUT_ASM)
- for (uint32_t insnID = 0; insnID < genKernel->insnNum; ++insnID)
+ if (OCL_OUTPUT_ASM) {
+ std::cout << genKernel->getName() << "'s disassemble begin:" << std::endl;
+ ir::LabelIndex curLabel = (ir::LabelIndex)0;
+ std::cout << " L0:" << std::endl;
+ for (uint32_t insnID = 0; insnID < genKernel->insnNum; ++insnID) {
+ if (labelPos.find((ir::LabelIndex)(curLabel + 1))->second == insnID) {
+ std::cout << " L" << curLabel + 1 << ":" << std::endl;
+ curLabel = (ir::LabelIndex)(curLabel + 1);
+ }
+ std::cout << " (" << std::setw(8) << insnID * 2 << ") ";
gen_disasm(stdout, &p->store[insnID]);
+ }
+ std::cout << genKernel->getName() << "'s disassemble end." << std::endl;
+ }
return true;
}
if (!ctx.isScalarReg(vReg))
registerSize *= ctx.getSimdWidth();
}
- cout << "%" << setw(-8) << vReg << "\tg" << setw(-3) << reg << "." << setw(-2) << subreg << "B"
- << "\t" << setw(3) << registerSize
- << "\t[" << setw(8) << this->intervals[(uint)vReg].minID
+ cout << "%" << setiosflags(ios::left) << setw(8) << vReg << "g"
+ << setiosflags(ios::left) << setw(3) << reg << "."
+ << setiosflags(ios::left) << setw(2) << subreg
+ << " " << setw(3) << registerSize << "B"
+ << " [" << setw(8) << this->intervals[(uint)vReg].minID
<< " -> " << setw(8) << this->intervals[(uint)vReg].maxID
<< "]" << endl;
}