clk: add mipi enable and bandgap gate

PD#146437: axg: add mipi enable and bandgap gate and
	update clkmsr for cts_encl_clk

Change-Id: If14ede7ab0a0b649879153cb1089bec04c7412b2
Signed-off-by: Yun Cai <yun.cai@amlogic.com>

diff --git a/drivers/amlogic/clk/axg/axg.c b/drivers/amlogic/clk/axg/axg.c
index 6c80432..33de547 100644 (file)
--- a/drivers/amlogic/clk/axg/axg.c
+++ b/drivers/amlogic/clk/axg/axg.c
@@ -356,20 +356,7 @@ static struct clk_mux axg_pcie_mux = {
                .flags = (CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED),
        },
 };
-#if 0
-static struct clk_gate axg_pcie_input_gate = {
-       .reg = (void *)HHI_PCIE_PLL_CNTL6,
-       .bit_idx = 1,
-       .lock = &clk_lock,
-       .hw.init = &(struct clk_init_data) {
-               .name = "axg_pcie_input_gate",
-               .ops = &clk_gate_ops,
-               .parent_names = (const char *[]){ "pcie_input" },
-               .num_parents = 1,
-               .flags = (CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED),
-       },
-};
-#endif
+
 static struct clk_mux axg_pcie_ref = {
        .reg = (void *)HHI_PCIE_PLL_CNTL6,
        .mask = 0x1,
@@ -411,6 +398,33 @@ static struct clk_gate axg_pcie_cml_en1 = {
                .flags = (CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED),
        },
 };
+
+static struct clk_gate axg_mipi_enable_gate = {
+       .reg = (void *)HHI_MIPI_CNTL0,
+       .bit_idx = 29,
+       .lock = &clk_lock,
+       .hw.init = &(struct clk_init_data) {
+               .name = "axg_mipi_enable_gate",
+               .ops = &clk_gate_ops,
+               .parent_names = (const char *[]){ "NULL" },
+               .num_parents = 0,
+               .flags = (CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED),
+       },
+};
+
+static struct clk_gate axg_mipi_bandgap_gate = {
+       .reg = (void *)HHI_MIPI_CNTL0,
+       .bit_idx = 26,
+       .lock = &clk_lock,
+       .hw.init = &(struct clk_init_data) {
+               .name = "axg_mipi_bandgap_gate",
+               .ops = &clk_gate_ops,
+               .parent_names = (const char *[]){ "NULL" },
+               .num_parents = 0,
+               .flags = (CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED),
+       },
+};
+
 /*
  * FIXME cpu clocks and the legacy composite clocks (e.g. clk81) are both PLL
  * post-dividers and should be modelled with their respective PLLs via the
@@ -727,6 +741,8 @@ static struct clk_hw *axg_clk_hws[] = {
        [CLKID_PCIE_REF]                        = &axg_pcie_ref.hw,
        [CLKID_PCIE_CML_EN0]    = &axg_pcie_cml_en0.hw,
        [CLKID_PCIE_CML_EN1]    = &axg_pcie_cml_en1.hw,
+       [CLKID_MIPI_ENABLE_GATE]        = &axg_mipi_enable_gate.hw,
+       [CLKID_MIPI_BANDGAP_GATE]       = &axg_mipi_bandgap_gate.hw,
 };
 /* Convenience tables to populate base addresses in .probe */
 
@@ -791,6 +807,8 @@ static struct clk_gate *axg_clk_gates[] = {
        &axg_ao_ahb_bus,
        &axg_ao_iface,
        &axg_ao_i2c,
+       &axg_mipi_enable_gate,
+       &axg_mipi_bandgap_gate,
 };
 
 static void __init axg_clkc_init(struct device_node *np)

diff --git a/drivers/amlogic/clk/axg/axg.h b/drivers/amlogic/clk/axg/axg.h
index 3887676..d36ffd8 100644 (file)
--- a/drivers/amlogic/clk/axg/axg.h
+++ b/drivers/amlogic/clk/axg/axg.h
@@ -26,6 +26,7 @@
  * to get the right value
  */
 
+#define HHI_MIPI_CNTL0                 0x0 /* 0x0 offset in data sheet */
 #define HHI_GP0_PLL_CNTL               0x40 /* 0x10 offset in data sheet */
 
 #define HHI_HIFI_PLL_CNTL              0x80 /* 0x20 offset in data sheet */

diff --git a/drivers/amlogic/clk/axg/axg_clk-pll.c b/drivers/amlogic/clk/axg/axg_clk-pll.c
index 28c45ef..162308c 100644 (file)
--- a/drivers/amlogic/clk/axg/axg_clk-pll.c
+++ b/drivers/amlogic/clk/axg/axg_clk-pll.c
@@ -31,6 +31,7 @@
  */
 
 #include <linux/clk-provider.h>
+#include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/err.h>
 #include <linux/io.h>
@@ -39,7 +40,7 @@
 #include <linux/slab.h>
 #include <linux/string.h>
 #include <linux/amlogic/cpu_version.h>
-#include <linux/clk.h>
+#include <dt-bindings/clock/amlogic,axg-clkc.h>
 
 #ifdef CONFIG_ARM64
 #include "../clkc.h"
@@ -206,9 +207,6 @@ static int meson_axg_pll_set_rate(struct clk_hw *hw, unsigned long rate,
                void *cntlbase = pll->base + p->reg_off;
 
                if (!strcmp(clk_hw_get_name(hw), "pcie_pll")) {
-                       reg = readl(pll->base);
-                       reg |= (AXG_MIPI_CNTL0_ENABLE | AXG_MIPI_CNTL0_BANDGAP);
-                       writel(reg, pll->base);
                        writel(AXG_PCIE_PLL_CNTL, cntlbase + (u64)(0*4));
                        writel(AXG_PCIE_PLL_CNTL1, cntlbase + (u64)(1*4));
                        writel(AXG_PCIE_PLL_CNTL2, cntlbase + (u64)(2*4));
@@ -313,6 +311,8 @@ static int meson_axg_pll_enable(struct clk_hw *hw)
                void *cntlbase = pll->base + p->reg_off;
 
                if (!strcmp(clk_hw_get_name(hw), "pcie_pll")) {
+                       clk_prepare_enable(clks[CLKID_MIPI_ENABLE_GATE]);
+                       clk_prepare_enable(clks[CLKID_MIPI_BANDGAP_GATE]);
                        if (readl(cntlbase + (u64)(6*4)) == AXG_PCIE_PLL_CNTL6)
                                first_set = 0;
                } else if (!strcmp(clk_hw_get_name(hw), "hifi_pll")) {
@@ -357,6 +357,11 @@ static void meson_axg_pll_disable(struct clk_hw *hw)
                writel(readl(pll->base + p->reg_off) & (~MESON_PLL_ENABLE),
                        pll->base + p->reg_off);
 
+               if (!strcmp(clk_hw_get_name(hw), "pcie_pll")) {
+                       clk_disable_unprepare(clks[CLKID_MIPI_ENABLE_GATE]);
+                       clk_disable_unprepare(clks[CLKID_MIPI_BANDGAP_GATE]);
+               };
+
                if (pll->lock)
                        spin_unlock_irqrestore(pll->lock, flags);
        }

diff --git a/drivers/amlogic/clk/clk_measure.c b/drivers/amlogic/clk/clk_measure.c
index 87ab692..b213397 100644 (file)
--- a/drivers/amlogic/clk/clk_measure.c
+++ b/drivers/amlogic/clk/clk_measure.c
@@ -537,7 +537,7 @@ int axg_clk_measure(struct seq_file *s, void *what, unsigned int index)
                [12] = "0                        ",
                [11] = "0                        ",
                [10] = "0                        ",
-               [9] = "0                         ",
+               [9] = "cts_encl_clk          ",
                [8] = "0                         ",
                [7] = "clk81               ",
                [6] = "0                         ",

diff --git a/include/dt-bindings/clock/amlogic,axg-clkc.h b/include/dt-bindings/clock/amlogic,axg-clkc.h
index 85d2924..24ff084 100644 (file)
--- a/include/dt-bindings/clock/amlogic,axg-clkc.h
+++ b/include/dt-bindings/clock/amlogic,axg-clkc.h
@@ -52,9 +52,11 @@
 #define CLKID_PCIE_INPUT_GATE 27
 #define CLKID_PCIE_CML_EN0 28
 #define CLKID_PCIE_CML_EN1 29
+#define CLKID_MIPI_ENABLE_GATE 30
+#define CLKID_MIPI_BANDGAP_GATE 31
 
 /*HHI_GCLK_MPEG0: 0x50*/
-#define GATE_BASE0    25
+#define GATE_BASE0    32
 #define CLKID_DDR    (GATE_BASE0 + 0)
 #define CLKID_AUDIO_LOCKER     (GATE_BASE0 + 1)
 #define CLKID_MIPI_DSI_HOST              (GATE_BASE0 + 2)