hw-obj-$(CONFIG_EEPRO100_PCI) += eepro100.o
hw-obj-$(CONFIG_PCNET_PCI) += pcnet-pci.o
hw-obj-$(CONFIG_PCNET_COMMON) += pcnet.o
+hw-obj-$(CONFIG_E1000_PCI) += e1000.o
hw-obj-$(CONFIG_SMC91C111) += smc91c111.o
hw-obj-$(CONFIG_LAN9118) += lan9118.o
# PCI network cards
obj-$(CONFIG_RTL8139_PCI) += rtl8139.o
-obj-$(CONFIG_E1000_PCI) += e1000.o
# Inter-VM PCI shared memory
obj-$(CONFIG_KVM) += ivshmem.o
E1000State *s = opaque;
unsigned int index = (addr & 0x1ffff) >> 2;
-#ifdef TARGET_WORDS_BIGENDIAN
- val = bswap32(val);
-#endif
if (index < NWRITEOPS && macreg_writeops[index]) {
macreg_writeops[index](s, index, val);
} else if (index < NREADOPS && macreg_readops[index]) {
if (index < NREADOPS && macreg_readops[index])
{
- uint32_t val = macreg_readops[index](s, index);
-#ifdef TARGET_WORDS_BIGENDIAN
- val = bswap32(val);
-#endif
- return val;
+ return macreg_readops[index](s, index);
}
DBGOUT(UNKNOWN, "MMIO unknown read addr=0x%08x\n", index<<2);
return 0;
pci_conf[PCI_INTERRUPT_PIN] = 1; // interrupt pin 0
d->mmio_index = cpu_register_io_memory(e1000_mmio_read,
- e1000_mmio_write, d, DEVICE_NATIVE_ENDIAN);
+ e1000_mmio_write, d, DEVICE_LITTLE_ENDIAN);
pci_register_bar(&d->dev, 0, PNPMMIO_SIZE,
PCI_BASE_ADDRESS_SPACE_MEMORY, e1000_mmio_map);