Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 2ba3540..754a240 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,18 @@
+2022-05-16  Sebastian Pop  <spop@amazon.com>
+
+       PR target/105162
+       * config/aarch64/aarch64-protos.h (atomic_ool_names): Increase dimension
+       of str array.
+       * config/aarch64/aarch64.cc (aarch64_atomic_ool_func): Call
+       memmodel_from_int and handle MEMMODEL_SYNC_*.
+       (DEF0): Add __aarch64_*_sync functions.
+
+2022-05-16  Eric Botcazou  <ebotcazou@adacore.com>
+
+       * dwarf2out.cc (loc_list_from_tree_1) <TRUTH_NOT_EXPR>: Do a logical
+       instead of a bitwise negation.
+       <COND_EXPR>: Swap the operands if the condition is TRUTH_NOT_EXPR.
+
 2022-05-13  Eric Botcazou  <ebotcazou@adacore.com>
 
        * tree-sra.cc (sra_modify_assign): Check that scalar storage order

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 634dc22..260f749 100644 (file)
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20220516
+20220517

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 70758d8..ef42b12 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,19 @@
+2022-05-16  Sebastian Pop  <spop@amazon.com>
+
+       PR target/105162
+       * gcc.target/aarch64/sync-comp-swap-ool.c: New.
+       * gcc.target/aarch64/sync-op-acquire-ool.c: New.
+       * gcc.target/aarch64/sync-op-full-ool.c: New.
+       * gcc.target/aarch64/target_attr_20.c: Update check.
+       * gcc.target/aarch64/target_attr_21.c: Same.
+
+2022-05-16  Richard Biener  <rguenther@suse.de>
+
+       Backported from master:
+       2022-05-16  Richard Biener  <rguenther@suse.de>
+
+       * gcc.dg/torture/pr105598.c: New testcase.
+
 2022-05-15  Jason Merrill  <jason@redhat.com>
 
        PR c++/105589

diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog
index 2a6f45b..540228a 100644 (file)
--- a/libgcc/ChangeLog
+++ b/libgcc/ChangeLog
@@ -1,3 +1,9 @@
+2022-05-16  Sebastian Pop  <spop@amazon.com>
+
+       PR target/105162
+       * config/aarch64/lse.S: Define BARRIER and handle memory MODEL 5.
+       * config/aarch64/t-lse: Add a 5th memory model for _sync functions.
+
 2022-05-13  Martin Liska  <mliska@suse.cz>
 
        Backported from master:

diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index df0ce7e..875c9f8 100644 (file)
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,39 @@
+2022-05-16  Jonathan Wakely  <jwakely@redhat.com>
+
+       Backported from master:
+       2022-05-16  Jonathan Wakely  <jwakely@redhat.com>
+
+       * doc/xml/manual/prerequisites.xml: Fix attributes for external
+       hyperlink.
+       * doc/html/manual/setup.html: Regenerate.
+
+2022-05-16  Jonathan Wakely  <jwakely@redhat.com>
+
+       Backported from master:
+       2022-05-16  Jonathan Wakely  <jwakely@redhat.com>
+
+       * doc/xml/manual/status_cxx2023.xml: Update with gcc-12 support.
+       * doc/html/*: Regenerate.
+
+2022-05-16  Jonathan Wakely  <jwakely@redhat.com>
+
+       Backported from master:
+       2022-05-16  Jonathan Wakely  <jwakely@redhat.com>
+
+       * doc/xml/manual/intro.xml: Include new chapter.
+       * doc/xml/manual/status_cxx2020.xml: Tweak release numbers.
+       * doc/xml/manual/status_cxx2023.xml: New file.
+       * doc/html/*: Regenerate.
+
+2022-05-16  Jonathan Wakely  <jwakely@redhat.com>
+
+       Backported from master:
+       2022-05-16  Jonathan Wakely  <jwakely@redhat.com>
+
+       * doc/html/manual/status.html: Regenerate.
+       * doc/xml/manual/status_cxx2020.xml: Fix supported version for
+       C++20 bit operations.
+
 2022-05-13  Alexandre Oliva  <oliva@adacore.com>
 
        Backported from master: