dt-bindings: clock: add SM8250 QCOM Graphics clock bindings

Add device tree bindings for graphics clock controller for
Qualcomm Technology Inc's SM8250 SoCs.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20200709135251.643-9-jonathan@marek.ca
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
index 3e064ed..df943c4 100644 (file)
--- a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
@@ -11,12 +11,13 @@ maintainers:
 
 description: |
   Qualcomm graphics clock control module which supports the clocks, resets and
-  power domains on SDM845/SC7180/SM8150.
+  power domains on SDM845/SC7180/SM8150/SM8250.
 
   See also:
     dt-bindings/clock/qcom,gpucc-sdm845.h
     dt-bindings/clock/qcom,gpucc-sc7180.h
     dt-bindings/clock/qcom,gpucc-sm8150.h
+    dt-bindings/clock/qcom,gpucc-sm8250.h
 
 properties:
   compatible:
@@ -24,6 +25,7 @@ properties:
       - qcom,sdm845-gpucc
       - qcom,sc7180-gpucc
       - qcom,sm8150-gpucc
+      - qcom,sm8250-gpucc
 
   clocks:
     items:

diff --git a/include/dt-bindings/clock/qcom,gpucc-sm8250.h b/include/dt-bindings/clock/qcom,gpucc-sm8250.h
new file mode 100644 (file)
index 0000000..dc8e387
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gpucc-sm8250.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8250_H
+#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8250_H
+
+/* GPU_CC clock registers */
+#define GPU_CC_AHB_CLK                         0
+#define GPU_CC_CRC_AHB_CLK                     1
+#define GPU_CC_CX_APB_CLK                      2
+#define GPU_CC_CX_GMU_CLK                      3
+#define GPU_CC_CX_SNOC_DVM_CLK                 4
+#define GPU_CC_CXO_AON_CLK                     5
+#define GPU_CC_CXO_CLK                         6
+#define GPU_CC_GMU_CLK_SRC                     7
+#define GPU_CC_GX_GMU_CLK                      8
+#define GPU_CC_PLL1                            9
+#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK         10
+
+/* GPU_CC Resets */
+#define GPUCC_GPU_CC_ACD_BCR                   0
+#define GPUCC_GPU_CC_CX_BCR                    1
+#define GPUCC_GPU_CC_GFX3D_AON_BCR             2
+#define GPUCC_GPU_CC_GMU_BCR                   3
+#define GPUCC_GPU_CC_GX_BCR                    4
+#define GPUCC_GPU_CC_XO_BCR                    5
+
+/* GPU_CC GDSCRs */
+#define GPU_CX_GDSC                            0
+#define GPU_GX_GDSC                            1
+
+#endif