i965: Remove Gen10-specific state setup and workarounds

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6899>

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index 76471f5..5cf03c7 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -103,9 +103,6 @@ brw_blorp_init(struct brw_context *brw)
    case 9:
       brw->blorp.exec = gen9_blorp_exec;
       break;
-   case 10:
-      brw->blorp.exec = gen10_blorp_exec;
-      break;
    case 11:
       brw->blorp.exec = gen11_blorp_exec;
       break;
@@ -164,8 +161,7 @@ blorp_surf_for_miptree(struct brw_context *brw,
        * surface.  Without one, it does nothing.
        */
       surf->clear_color =
-         intel_miptree_get_clear_color(devinfo, mt, mt->surf.format,
-                                       !is_render_target, (struct brw_bo **)
+         intel_miptree_get_clear_color(mt, (struct brw_bo **)
                                        &surf->clear_color_addr.buffer,
                                        &surf->clear_color_addr.offset);
 

diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index 20cb24c..6a64bbe 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
@@ -400,9 +400,6 @@ brw_init_pipe_control(struct brw_context *brw,
    case 11:
       brw->vtbl.emit_raw_pipe_control = gen11_emit_raw_pipe_control;
       break;
-   case 10:
-      brw->vtbl.emit_raw_pipe_control = gen10_emit_raw_pipe_control;
-      break;
    case 9:
       brw->vtbl.emit_raw_pipe_control = gen9_emit_raw_pipe_control;
       break;
@@ -425,6 +422,8 @@ brw_init_pipe_control(struct brw_context *brw,
          devinfo->is_g4x ? gen45_emit_raw_pipe_control
                          : gen4_emit_raw_pipe_control;
       break;
+   default:
+      unreachable("Unhandled Gen.");
    }
 
    if (devinfo->gen < 6)

diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 24e7e54..77438d6 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -312,7 +312,7 @@ void brw_init_state( struct brw_context *brw )
    if (devinfo->gen >= 11)
       gen11_init_atoms(brw);
    else if (devinfo->gen >= 10)
-      gen10_init_atoms(brw);
+      unreachable("Gen10 support dropped.");
    else if (devinfo->gen >= 9)
       gen9_init_atoms(brw);
    else if (devinfo->gen >= 8)

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index f5659f2..a5fbd18 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -166,10 +166,7 @@ brw_emit_surface_state(struct brw_context *brw,
       /* We only really need a clear color if we also have an auxiliary
        * surface.  Without one, it does nothing.
        */
-      clear_color =
-         intel_miptree_get_clear_color(devinfo, mt, view.format,
-                                       view.usage & ISL_SURF_USAGE_TEXTURE_BIT,
-                                       &clear_bo, &clear_offset);
+      clear_color = intel_miptree_get_clear_color(mt, &clear_bo, &clear_offset);
    }
 
    void *state = brw_state_batch(brw,

diff --git a/src/mesa/drivers/dri/i965/gen8_multisample_state.c b/src/mesa/drivers/dri/i965/gen8_multisample_state.c
index 5381d32..3afa586 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen8_multisample_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_multisample_state.c
@@ -28,57 +28,11 @@
 #include "brw_multisample_state.h"
 
 /**
- * From Gen10 Workarounds page in h/w specs:
- * WaSampleOffsetIZ:
- * Prior to the 3DSTATE_SAMPLE_PATTERN driver must ensure there are no
- * markers in the pipeline by programming a PIPE_CONTROL with stall.
- */
-static void
-gen10_emit_wa_cs_stall_flush(struct brw_context *brw)
-{
-   UNUSED const struct gen_device_info *devinfo = &brw->screen->devinfo;
-   assert(devinfo->gen == 10);
-   brw_emit_pipe_control_flush(brw,
-                               PIPE_CONTROL_CS_STALL |
-                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
-}
-
-/**
- * From Gen10 Workarounds page in h/w specs:
- * WaSampleOffsetIZ:
- * When 3DSTATE_SAMPLE_PATTERN is programmed, driver must then issue an
- * MI_LOAD_REGISTER_IMM command to an offset between 0x7000 and 0x7FFF(SVL)
- * after the command to ensure the state has been delivered prior to any
- * command causing a marker in the pipeline.
- */
-static void
-gen10_emit_wa_lri_to_cache_mode_zero(struct brw_context *brw)
-{
-   UNUSED const struct gen_device_info *devinfo = &brw->screen->devinfo;
-   assert(devinfo->gen == 10);
-
-   /* Write to CACHE_MODE_0 (0x7000) */
-   brw_load_register_imm32(brw, GEN7_CACHE_MODE_0, 0);
-
-   /* Before changing the value of CACHE_MODE_0 register, GFX pipeline must
-    * be idle; i.e., full flush is required.
-    */
-   brw_emit_pipe_control_flush(brw,
-                               PIPE_CONTROL_CACHE_FLUSH_BITS |
-                               PIPE_CONTROL_CACHE_INVALIDATE_BITS);
-}
-
-/**
  * 3DSTATE_SAMPLE_PATTERN
  */
 void
 gen8_emit_3dstate_sample_pattern(struct brw_context *brw)
 {
-   const struct gen_device_info *devinfo = &brw->screen->devinfo;
-
-   if (devinfo->gen == 10)
-      gen10_emit_wa_cs_stall_flush(brw);
-
    BEGIN_BATCH(9);
    OUT_BATCH(_3DSTATE_SAMPLE_PATTERN << 16 | (9 - 2));
 
@@ -98,7 +52,4 @@ gen8_emit_3dstate_sample_pattern(struct brw_context *brw)
    /* 1x and 2x MSAA */
    OUT_BATCH(brw_multisample_positions_1x_2x);
    ADVANCE_BATCH();
-
-   if (devinfo->gen == 10)
-      gen10_emit_wa_lri_to_cache_mode_zero(brw);
 }

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index f5f8eb6..0a65c9f 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -3280,34 +3280,15 @@ intel_miptree_set_clear_color(struct brw_context *brw,
 }
 
 union isl_color_value
-intel_miptree_get_clear_color(const struct gen_device_info *devinfo,
-                              const struct intel_mipmap_tree *mt,
-                              enum isl_format view_format, bool sampling,
+intel_miptree_get_clear_color(const struct intel_mipmap_tree *mt,
                               struct brw_bo **clear_color_bo,
                               uint64_t *clear_color_offset)
 {
    assert(mt->aux_buf);
 
-   if (devinfo->gen == 10 && isl_format_is_srgb(view_format) && sampling) {
-      /* The gen10 sampler doesn't gamma-correct the clear color. In this case,
-       * we switch to using the inline clear color and do the sRGB color
-       * conversion process defined in the OpenGL spec. The red, green, and
-       * blue channels take part in gamma correction, while the alpha channel
-       * is unchanged.
-       */
-      union isl_color_value srgb_decoded_value = mt->fast_clear_color;
-      for (unsigned i = 0; i < 3; i++) {
-         srgb_decoded_value.f32[i] =
-            util_format_srgb_to_linear_float(mt->fast_clear_color.f32[i]);
-      }
-      *clear_color_bo = 0;
-      *clear_color_offset = 0;
-      return srgb_decoded_value;
-   } else {
-      *clear_color_bo = mt->aux_buf->clear_color_bo;
-      *clear_color_offset = mt->aux_buf->clear_color_offset;
-      return mt->fast_clear_color;
-   }
+   *clear_color_bo = mt->aux_buf->clear_color_bo;
+   *clear_color_offset = mt->aux_buf->clear_color_offset;
+   return mt->fast_clear_color;
 }
 
 static void

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 3e53a00..b8f53bd 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -702,9 +702,7 @@ intel_miptree_set_clear_color(struct brw_context *brw,
 
 /* Get a clear color suitable for filling out an ISL surface state. */
 union isl_color_value
-intel_miptree_get_clear_color(const struct gen_device_info *devinfo,
-                              const struct intel_mipmap_tree *mt,
-                              enum isl_format view_format, bool sampling,
+intel_miptree_get_clear_color(const struct intel_mipmap_tree *mt,
                               struct brw_bo **clear_color_bo,
                               uint64_t *clear_color_offset);