perf/arm-cmn: Update watchpoint format

From CMN-650 onwards, some of the fields in the watchpoint config
registers moved subtly enough to easily overlook. Watchpoint events are
still only partially supported on newer IPs - which in itself deserves
noting - but were not intended to become any *less* functional than on
CMN-600.

Fixes: 60d1504070c2 ("perf/arm-cmn: Support new IP features")
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Link: https://lore.kernel.org/r/e1ce4c2f1e4f73ab1c60c3a85e4037cd62dd6352.1645727871.git.robin.murphy@arm.com
Signed-off-by: Will Deacon <will@kernel.org>

diff --git a/drivers/perf/arm-cmn.c b/drivers/perf/arm-cmn.c
index e924d45..9c1d82b 100644 (file)
--- a/drivers/perf/arm-cmn.c
+++ b/drivers/perf/arm-cmn.c
@@ -71,9 +71,11 @@
 #define CMN_DTM_WPn(n)                 (0x1A0 + (n) * 0x18)
 #define CMN_DTM_WPn_CONFIG(n)          (CMN_DTM_WPn(n) + 0x00)
 #define CMN_DTM_WPn_CONFIG_WP_DEV_SEL2 GENMASK_ULL(18,17)
-#define CMN_DTM_WPn_CONFIG_WP_COMBINE  BIT(6)
-#define CMN_DTM_WPn_CONFIG_WP_EXCLUSIVE        BIT(5)
-#define CMN_DTM_WPn_CONFIG_WP_GRP      BIT(4)
+#define CMN_DTM_WPn_CONFIG_WP_COMBINE  BIT(9)
+#define CMN_DTM_WPn_CONFIG_WP_EXCLUSIVE        BIT(8)
+#define CMN600_WPn_CONFIG_WP_COMBINE   BIT(6)
+#define CMN600_WPn_CONFIG_WP_EXCLUSIVE BIT(5)
+#define CMN_DTM_WPn_CONFIG_WP_GRP      GENMASK_ULL(5, 4)
 #define CMN_DTM_WPn_CONFIG_WP_CHN_SEL  GENMASK_ULL(3, 1)
 #define CMN_DTM_WPn_CONFIG_WP_DEV_SEL  BIT(0)
 #define CMN_DTM_WPn_VAL(n)             (CMN_DTM_WPn(n) + 0x08)
@@ -155,6 +157,7 @@
 #define CMN_CONFIG_WP_COMBINE          GENMASK_ULL(27, 24)
 #define CMN_CONFIG_WP_DEV_SEL          GENMASK_ULL(50, 48)
 #define CMN_CONFIG_WP_CHN_SEL          GENMASK_ULL(55, 51)
+/* Note that we don't yet support the tertiary match group on newer IPs */
 #define CMN_CONFIG_WP_GRP              BIT_ULL(56)
 #define CMN_CONFIG_WP_EXCLUSIVE                BIT_ULL(57)
 #define CMN_CONFIG1_WP_VAL             GENMASK_ULL(63, 0)
@@ -908,15 +911,18 @@ static u32 arm_cmn_wp_config(struct perf_event *event)
        u32 grp = CMN_EVENT_WP_GRP(event);
        u32 exc = CMN_EVENT_WP_EXCLUSIVE(event);
        u32 combine = CMN_EVENT_WP_COMBINE(event);
+       bool is_cmn600 = to_cmn(event->pmu)->model == CMN600;
 
        config = FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_DEV_SEL, dev) |
                 FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_CHN_SEL, chn) |
                 FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_GRP, grp) |
-                FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_EXCLUSIVE, exc) |
                 FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_DEV_SEL2, dev >> 1);
+       if (exc)
+               config |= is_cmn600 ? CMN600_WPn_CONFIG_WP_EXCLUSIVE :
+                                     CMN_DTM_WPn_CONFIG_WP_EXCLUSIVE;
        if (combine && !grp)
-               config |= CMN_DTM_WPn_CONFIG_WP_COMBINE;
-
+               config |= is_cmn600 ? CMN600_WPn_CONFIG_WP_COMBINE :
+                                     CMN_DTM_WPn_CONFIG_WP_COMBINE;
        return config;
 }