v4l2: fixed sc2235->dvp->isp->ddr error
authorchanghuang.liang <changhuang.liang@starfivetech.com>
Mon, 30 May 2022 05:54:43 +0000 (13:54 +0800)
committerchanghuang.liang <changhuang.liang@starfivetech.com>
Mon, 30 May 2022 05:54:43 +0000 (13:54 +0800)
drivers/media/platform/starfive/v4l2_driver/stf_csi_hw_ops.c
drivers/media/platform/starfive/v4l2_driver/stf_vin.c
drivers/media/platform/starfive/v4l2_driver/stf_vin_hw_ops.c

index 5776181..2b9ea12 100755 (executable)
@@ -44,7 +44,7 @@ static int stf_csi_power_on(struct stf_csi_dev *csi_dev, u8 on)
        pmic_set_domain(POWER_SW_0_REG, POWER_SW_0_VDD18_MIPIRX, on);
        pmic_set_domain(POWER_SW_0_REG, POWER_SW_0_VDD09_MIPIRX, on);
 
-       aon_syscon = ioremap(0x17010000, 0x1000);
+       aon_syscon = ioremap(0x17010000, 0x4);
        reg_write(aon_syscon, 0x00, 0x80000000);
 
        return 0;
@@ -188,9 +188,8 @@ static int csi2rx_start(struct stf_csi_dev *csi_dev, void *reg_base)
        u32 reg;
 
        if (!csiphy) {
-               st_err(ST_CSI, "csiphy%d sensor not exist use csiphy%d init.\n",
-                               csi_dev->csiphy_id, !csi_dev->csiphy_id);
-               csiphy = stfcamss->csiphy_dev[!csi_dev->csiphy_id].csiphy;
+               st_err(ST_CSI, "csiphy%d config not exist\n", csi_dev->csiphy_id);
+               return -EINVAL;
        }
 
        csi2rx_reset(reg_base);
index 30aa19c..7ef2916 100755 (executable)
@@ -175,7 +175,7 @@ exit_line:
        mutex_lock(&vin_dev->power_lock);
        if (on) {
                if (vin_dev->power_count == 0) {
-                       vin_dev->hw_ops->vin_top_clk_init(vin_dev);
+                       //vin_dev->hw_ops->vin_top_clk_init(vin_dev);
                        vin_dev->hw_ops->vin_clk_enable(vin_dev);
                        vin_dev->hw_ops->vin_config_set(vin_dev);
                }
@@ -188,7 +188,7 @@ exit_line:
                }
                if (vin_dev->power_count == 1) {
                        vin_dev->hw_ops->vin_clk_disable(vin_dev);
-                       vin_dev->hw_ops->vin_top_clk_deinit(vin_dev);
+                       //vin_dev->hw_ops->vin_top_clk_deinit(vin_dev);
                }
                vin_dev->power_count--;
        }
index b1cae9c..09dfc40 100755 (executable)
@@ -101,16 +101,13 @@ static int stf_vin_clk_enable(struct stf_vin2_dev *vin_dev)
 {
        struct stfcamss *stfcamss = vin_dev->stfcamss;
 
-       reset_control_deassert(stfcamss->sys_rst[STFRST_PCLK].rstc);
-       reset_control_deassert(stfcamss->sys_rst[STFRST_SYS_CLK].rstc);
-       reset_control_deassert(stfcamss->sys_rst[STFRST_AXIRD].rstc);
-       reset_control_deassert(stfcamss->sys_rst[STFRST_AXIWR].rstc);
-
        clk_prepare_enable(stfcamss->sys_clk[STFCLK_PCLK].clk);
-
        clk_set_rate(stfcamss->sys_clk[STFCLK_APB_FUNC].clk, 51200000);
        clk_set_rate(stfcamss->sys_clk[STFCLK_SYS_CLK].clk, 307200000);
 
+       reset_control_deassert(stfcamss->sys_rst[STFRST_PCLK].rstc);
+       reset_control_deassert(stfcamss->sys_rst[STFRST_SYS_CLK].rstc);
+
        return 0;
 }
 
@@ -121,8 +118,6 @@ static int stf_vin_clk_disable(struct stf_vin2_dev *vin_dev)
 
        reset_control_assert(stfcamss->sys_rst[STFRST_PCLK].rstc);
        reset_control_assert(stfcamss->sys_rst[STFRST_SYS_CLK].rstc);
-       reset_control_assert(stfcamss->sys_rst[STFRST_AXIRD].rstc);
-       reset_control_assert(stfcamss->sys_rst[STFRST_AXIWR].rstc);
 
        clk_disable_unprepare(stfcamss->sys_clk[STFCLK_PCLK].clk);
 
@@ -136,13 +131,17 @@ static int stf_vin_config_set(struct stf_vin2_dev *vin_dev)
 
 static int stf_vin_wr_stream_set(struct stf_vin2_dev *vin_dev, int on)
 {
+       struct stfcamss *stfcamss = vin_dev->stfcamss;
        struct stf_vin_dev *vin = vin_dev->stfcamss->vin;
 
        print_reg(ST_VIN, vin->sysctrl_base, SYSCONSAIF_SYSCFG_20);
-       if (on)
+       if (on) {
+               reset_control_deassert(stfcamss->sys_rst[STFRST_AXIWR].rstc);
                reg_set(vin->sysctrl_base, SYSCONSAIF_SYSCFG_20, U0_VIN_CNFG_AXIWR0_EN);
-       else
+       } else {
                reg_clear(vin->sysctrl_base, SYSCONSAIF_SYSCFG_20, U0_VIN_CNFG_AXIWR0_EN);
+               reset_control_assert(stfcamss->sys_rst[STFRST_AXIWR].rstc);
+       }
 
        print_reg(ST_VIN, vin->sysctrl_base, SYSCONSAIF_SYSCFG_20);