MRI->constrainRegClass(DstReg, DstRC);
}
+ // SubReg defs are illegal in machine SSA phase,
+ // we should not generate SubReg defs.
+ //
+ // For example, for the instructions:
+ //
+ // %1:g8rc_and_g8rc_nox0 = EXTSW %0:g8rc
+ // %3:gprc_and_gprc_nor0 = COPY %0.sub_32:g8rc
+ //
+ // We should generate:
+ //
+ // %1:g8rc_and_g8rc_nox0 = EXTSW %0:g8rc
+ // %6:gprc_and_gprc_nor0 = COPY %1.sub_32:g8rc_and_g8rc_nox0
+ // %3:gprc_and_gprc_nor0 = COPY %6:gprc_and_gprc_nor0
+ //
+ if (UseSrcSubIdx)
+ RC = MRI->getRegClass(UseMI->getOperand(0).getReg());
+
Register NewVR = MRI->createVirtualRegister(RC);
- MachineInstr *Copy = BuildMI(*UseMBB, UseMI, UseMI->getDebugLoc(),
- TII->get(TargetOpcode::COPY), NewVR)
+ BuildMI(*UseMBB, UseMI, UseMI->getDebugLoc(),
+ TII->get(TargetOpcode::COPY), NewVR)
.addReg(DstReg, 0, SubIdx);
- // SubIdx applies to both SrcReg and DstReg when UseSrcSubIdx is set.
- if (UseSrcSubIdx) {
- Copy->getOperand(0).setSubReg(SubIdx);
- Copy->getOperand(0).setIsUndef();
- }
+ if (UseSrcSubIdx)
+ UseMO->setSubReg(0);
+
UseMO->setReg(NewVR);
++NumReuse;
Changed = true;
--- /dev/null
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=powerpc64le -simplify-mir -verify-machineinstrs \
+# RUN: -run-pass=peephole-opt %s -o - | FileCheck %s
+
+# This tests to make sure that we do not generate subreg def
+# as it is illegal to generate subreg defs in machine SSA phase.
+
+---
+name: test_peephole_subreg_def
+alignment: 16
+tracksRegLiveness: true
+frameInfo:
+ maxAlignment: 1
+machineFunctionInfo: {}
+body: |
+ bb.0.entry:
+ liveins: $x3
+
+ ; CHECK-LABEL: name: test_peephole_subreg_def
+ ; CHECK: liveins: $x3
+ ; CHECK: [[COPY:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY $x3
+ ; CHECK: [[ADDI8_:%[0-9]+]]:g8rc = ADDI8 [[COPY]], 1
+ ; CHECK: [[EXTSW:%[0-9]+]]:g8rc_and_g8rc_nox0 = EXTSW [[ADDI8_]]
+ ; CHECK: [[LI8_:%[0-9]+]]:g8rc = LI8 0
+ ; CHECK: STB8 [[LI8_]], 0, [[EXTSW]]
+ ; CHECK: [[COPY1:%[0-9]+]]:gprc_and_gprc_nor0 = COPY [[EXTSW]].sub_32
+ ; CHECK: [[COPY2:%[0-9]+]]:gprc_and_gprc_nor0 = COPY [[COPY1]]
+ ; CHECK: [[ADDI:%[0-9]+]]:gprc = ADDI killed [[COPY2]], 1
+ ; CHECK: [[EXTSW_32_64_:%[0-9]+]]:g8rc_and_g8rc_nox0 = EXTSW_32_64 killed [[ADDI]]
+ ; CHECK: STB8 [[LI8_]], 0, killed [[EXTSW_32_64_]]
+ %0:g8rc_and_g8rc_nox0 = COPY $x3
+ %1:g8rc = ADDI8 %0, 1
+ %2:g8rc_and_g8rc_nox0 = EXTSW %1
+ %3:g8rc = LI8 0
+ STB8 %3, 0, killed %2
+ %4:gprc_and_gprc_nor0 = COPY %1.sub_32
+ %5:gprc = ADDI killed %4, 1
+ %6:g8rc_and_g8rc_nox0 = EXTSW_32_64 killed %5
+ STB8 %3, 0, killed %6
+
+...