uint32_t in = simple_strtoul(buf, NULL, 16);
s_clock_name = of_get_property(pdev->dev.of_node, "clock-src", NULL);
+ if (!s_clock_name)
+ return 0;
cpu_type = of_get_property(pdev->dev.of_node, "cpu-type", NULL);
-
+ if (!cpu_type)
+ return 0;
if (!in) {
clk_resume_usb(pdev, s_clock_name,
(unsigned long)(otg_dev->core_if->usb_peri_reg),
hcfg.d32);
/* Load restore values for [31:14] bits */
- pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
- pcgcctl.d32 = gr->pcgcctl_local | 0x00020000;
+ pcgcctl.d32 = ((gr->pcgcctl_local & 0xffffc000) | 0x00020000);
if (rmode)
pcgcctl.b.restoremode = 1;
dwc_udelay(10);
/* Load restore values for [31:14] bits and set EssRegRestored bit */
- pcgcctl.d32 = gr->pcgcctl_local | 0xffffc000;
- pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
+ pcgcctl.d32 = ((gr->pcgcctl_local | 0xffffc000) & 0xffffc000);
pcgcctl.b.ess_reg_restored = 1;
if (rmode)
pcgcctl.b.restoremode = 1;
DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
/* Load restore values for [31:14] bits */
- pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
- pcgcctl.d32 = gr->pcgcctl_local | 0x00020000;
+ pcgcctl.d32 = ((gr->pcgcctl_local & 0xffffc000) | 0x00020000);
if (!rmode)
pcgcctl.d32 |= 0x208;
dwc_udelay(10);
/* Load restore values for [31:14] bits */
- pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
- pcgcctl.d32 = gr->pcgcctl_local | 0x00020000;
+ pcgcctl.d32 = ((gr->pcgcctl_local & 0xffffc000) | 0x00020000);
pcgcctl.b.ess_reg_restored = 1;
if (!rmode)
pcgcctl.d32 |= 0x208;
if (ptr)
xfer_info = (hc_xfer_info_t *) ptr;
+ if (!xfer_info)
+ return;
if (!xfer_info->hc) {
DWC_ERROR("xfer_info->hc = %p\n", xfer_info->hc);
return;
if (ptr)
xfer_info = (ep_xfer_info_t *) ptr;
+ if (!xfer_info)
+ return;
if (!xfer_info->ep) {
DWC_ERROR("xfer_info->ep = %p\n", xfer_info->ep);
return;
depctl.b.eptype = ep->type;
depctl.b.txfnum = ep->tx_fifo_num;
- if (ep->type == DWC_OTG_EP_TYPE_ISOC)
- depctl.b.setd0pid = 1;
- else
- depctl.b.setd0pid = 1;
+ depctl.b.setd0pid = 1;
depctl.b.usbactep = 1;
{
glpmcfg_data_t lpmcfg;
- if (DWC_OTG_PARAM_TEST(val, 0, 15)) {
+ if (val > 15) {
DWC_WARN("Wrong valaue for hird_thres\n");
DWC_WARN("hird_thres must be 0-f\n");
return ;
return 1;
}
- if ((otg_cap_param != DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE ||
+ if ((otg_cap_param != DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE &&
otg_cap_param != DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE) &&
gpwrdn.b.bsessvld == 0) {
/* Save gpwrdn register for further usage if stschng interrupt */
*/
static uint32_t dwc_otg_handle_pwrdn_stschng_intr(dwc_otg_device_t *otg_dev)
{
- int retval;
+ int retval = 0;
gpwrdn_data_t gpwrdn = {.d32 = 0 };
gpwrdn_data_t gpwrdn_temp = {.d32 = 0 };
dwc_otg_core_if_t *core_if = otg_dev->core_if;
/* The core will be in ON STATE */
core_if->lx_state = DWC_OTG_L0;
core_if->xhib = 0;
-
- DWC_SPINUNLOCK(core_if->lock);
+ if (core_if->lock)
+ DWC_SPINUNLOCK(core_if->lock);
if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup)
core_if->pcd_cb->resume_wakeup(core_if->pcd_cb_p);
-
- DWC_SPINLOCK(core_if->lock);
+ if (core_if->lock)
+ DWC_SPINLOCK(core_if->lock);
}
gintsts.b.restoredone = 1;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&pdev->dev, "missing memory resource\n");
+ DWC_FREE(dwc_otg_device);
return -ENODEV;
}
ctrl_reg_addr = devm_ioremap_nocache(&pdev->dev, res->start, resource_size(res));
if (!ctrl_reg_addr) {
dev_err(&pdev->dev, "ioremap failed\n");
+ DWC_FREE(dwc_otg_device);
return -ENOMEM;
}
if (clk_enable_usb(pdev, s_clock_name,
(unsigned long)phy_reg_addr, cpu_type, controller_type)) {
dev_err(&pdev->dev, "Set dwc_otg PHY clock failed!\n");
+ DWC_FREE(dwc_otg_device);
return -ENODEV;
}
const char *cpu_type = NULL;
s_clock_name = of_get_property(pdev->dev.of_node, "clock-src", NULL);
+ if (!s_clock_name)
+ return 0;
cpu_type = of_get_property(pdev->dev.of_node, "cpu-type", NULL);
-
+ if (!cpu_type)
+ return 0;
clk_suspend_usb(pdev, s_clock_name,
(unsigned long)(g_dwc_otg_device[pdev->id]->
core_if->usb_peri_reg), cpu_type);
const char *cpu_type = NULL;
s_clock_name = of_get_property(pdev->dev.of_node, "clock-src", NULL);
+ if (!s_clock_name)
+ return 0;
cpu_type = of_get_property(pdev->dev.of_node, "cpu-type", NULL);
-
+ if (!cpu_type)
+ return 0;
clk_resume_usb(pdev, s_clock_name,
(unsigned long)(g_dwc_otg_device[pdev->id]->
core_if->usb_peri_reg), cpu_type);
dwc_otg_hcd_urb_t *urb;
int pipe_type;
+ if (!qtd)
+ return;
urb = qtd->urb;
+ if (!urb)
+ return;
pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
dwc_otg_hcd_qtd_remove(hcd, qtd, qh);
dwc_otg_hcd_qtd_free(qtd);
if (!qh->desc_list) {
retval = -DWC_E_NO_MEMORY;
DWC_ERROR("%s: DMA descriptor list allocation failed\n", __func__);
-
+ return retval;
}
dwc_memset(qh->desc_list, 0x00,
if (!hcd->frame_list) {
retval = -DWC_E_NO_MEMORY;
DWC_ERROR("%s: Frame List allocation failed\n", __func__);
+ return retval;
}
dwc_memset(hcd->frame_list, 0x00, 4 * MAX_FRLIST_EN_NUM);
hcd->fops->complete(hcd, urb->priv, urb,
urb->status);
dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
-
- if (failed)
- goto stop_scan;
+ goto stop_scan;
} else if (qh->ep_type == UE_CONTROL) {
if (qtd->control_phase == DWC_OTG_CONTROL_SETUP) {
if (urb->length > 0)
*/
if (halt_status == DWC_OTG_HC_XFER_STALL)
qh->data_toggle = DWC_OTG_HC_PID_DATA0;
- else
- dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
+ else {
+ if (qtd)
+ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
+ }
}
if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
int retval = 0;
int irq = 0;
-
+ int tt = 0;
DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT\n");
/*
*/
#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 30)
hcd = usb_create_hcd(&dwc_otg_hc_driver, &pdev->dev, pdev->dev.bus_id);
+ tt = 0;
#else
hcd = usb_create_hcd(&dwc_otg_hc_driver, &pdev->dev, dev_name(&pdev->dev));
- hcd->has_tt = 1;
+ tt = 1;
#endif
if (!hcd) {
retval = -ENOMEM;
goto error1;
}
+ hcd->has_tt = tt;
+
hcd->regs = otg_dev->os_dep.base;
set_bit(HCD_FLAG_DWC_OTG, &hcd->flags);
case PIPE_ISOCHRONOUS:
pipetype = "ISOCHRONOUS";
break;
- default:
- pipetype = "UNKNOWN";
- break;
};
pipetype;
}));
case PIPE_INTERRUPT:
ep_type = USB_ENDPOINT_XFER_INT;
break;
- default:
- DWC_WARN("Wrong ep type\n");
}
dwc_otg_urb = dwc_otg_hcd_urb_alloc(dwc_otg_hcd,
static uint32_t calc_bus_time(int speed, int is_in, int is_isoc, int bytecount)
{
- unsigned long retval;
+ long retval;
switch (speed) {
case USB_SPEED_HIGH:
default:
DWC_WARN("Unknown device speed\n");
retval = -1;
+ return retval;
}
return DWC_NS_TO_US(retval);
return pcd;
#ifdef DWC_UTE_CFI
fail:
-#endif
+
if (pcd->setup_pkt)
DWC_FREE(pcd->setup_pkt);
if (pcd->status_buf)
if (pcd)
DWC_FREE(pcd);
return NULL;
+#endif
}
num = UE_GET_ADDR(desc->bEndpointAddress);
dir = UE_GET_DIR(desc->bEndpointAddress);
- if (!desc->wMaxPacketSize) {
+ if (UGETW(desc->wMaxPacketSize) == 0) {
DWC_WARN("bad maxpacketsize\n");
retval = -DWC_E_INVALID;
goto out;
DWC_DEBUGPL(DBG_ANY, "ep0: odd state %d\n",
pcd->ep0state);
DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+ DWC_FREE(req);
return -DWC_E_SHUTDOWN;
}
usb_req->actual = 0;
ep = ep_from_handle(pcd, usb_ep);
- if (ep == NULL)
+ if (ep == NULL) {
is_isoc_ep = 0;
- else
- is_isoc_ep = (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) ? 1 : 0;
+ return -EINVAL;
+ }
+ is_isoc_ep = (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) ? 1 : 0;
if (GET_CORE_IF(pcd)->dma_enable) {
struct device *dev = &gadget_wrapper->pcd->otg_dev->os_dep.pldev->dev;
int portnum = 0;
const void *prop;
int i = 0;
- u32 retval;
+ int retval;
u32 pll_setting[8];
prop = of_get_property(dev->of_node, "portnum", NULL);
{
if (is_power_on)
/*set vbus on by gpio*/
- gpiod_direction_output(usb_gd, is_power_on);
+ gpiod_direction_output(usb_gd, 1);
else
/*set vbus off by gpio first*/
- gpiod_direction_output(usb_gd, is_power_on);
+ gpiod_direction_output(usb_gd, 0);
}
static void amlogic_new_set_vbus_power
{
if (is_power_on)
/*set vbus on by gpio*/
- gpiod_direction_output(usb_gd, is_power_on);
+ gpiod_direction_output(usb_gd, 1);
else
/*set vbus off by gpio first*/
- gpiod_direction_output(usb_gd, is_power_on);
+ gpiod_direction_output(usb_gd, 0);
}
static void amlogic_new_set_vbus_power