#define DEF_RVV_LMUL4_OPS(TYPE, REQUIRE)
#endif
-DEF_RVV_I_OPS (vint8mf8_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_I_OPS (vint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_I_OPS (vint8mf4_t, 0)
DEF_RVV_I_OPS (vint8mf2_t, 0)
DEF_RVV_I_OPS (vint8m1_t, 0)
DEF_RVV_I_OPS (vint8m2_t, 0)
DEF_RVV_I_OPS (vint8m4_t, 0)
DEF_RVV_I_OPS (vint8m8_t, 0)
-DEF_RVV_I_OPS (vint16mf4_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_I_OPS (vint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_I_OPS (vint16mf2_t, 0)
DEF_RVV_I_OPS (vint16m1_t, 0)
DEF_RVV_I_OPS (vint16m2_t, 0)
DEF_RVV_I_OPS (vint16m4_t, 0)
DEF_RVV_I_OPS (vint16m8_t, 0)
-DEF_RVV_I_OPS (vint32mf2_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_I_OPS (vint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_I_OPS (vint32m1_t, 0)
DEF_RVV_I_OPS (vint32m2_t, 0)
DEF_RVV_I_OPS (vint32m4_t, 0)
DEF_RVV_I_OPS (vint32m8_t, 0)
-DEF_RVV_I_OPS (vint64m1_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_I_OPS (vint64m2_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_I_OPS (vint64m4_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_I_OPS (vint64m8_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_I_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_I_OPS (vint64m2_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_I_OPS (vint64m4_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_I_OPS (vint64m8_t, RVV_REQUIRE_ELEN_64)
-DEF_RVV_U_OPS (vuint8mf8_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_U_OPS (vuint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_U_OPS (vuint8mf4_t, 0)
DEF_RVV_U_OPS (vuint8mf2_t, 0)
DEF_RVV_U_OPS (vuint8m1_t, 0)
DEF_RVV_U_OPS (vuint8m2_t, 0)
DEF_RVV_U_OPS (vuint8m4_t, 0)
DEF_RVV_U_OPS (vuint8m8_t, 0)
-DEF_RVV_U_OPS (vuint16mf4_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_U_OPS (vuint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_U_OPS (vuint16mf2_t, 0)
DEF_RVV_U_OPS (vuint16m1_t, 0)
DEF_RVV_U_OPS (vuint16m2_t, 0)
DEF_RVV_U_OPS (vuint16m4_t, 0)
DEF_RVV_U_OPS (vuint16m8_t, 0)
-DEF_RVV_U_OPS (vuint32mf2_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_U_OPS (vuint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_U_OPS (vuint32m1_t, 0)
DEF_RVV_U_OPS (vuint32m2_t, 0)
DEF_RVV_U_OPS (vuint32m4_t, 0)
DEF_RVV_U_OPS (vuint32m8_t, 0)
-DEF_RVV_U_OPS (vuint64m1_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_U_OPS (vuint64m2_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_U_OPS (vuint64m4_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_U_OPS (vuint64m8_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_U_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_U_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_U_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_U_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_64)
-DEF_RVV_F_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_ZVE64)
+DEF_RVV_F_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_F_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32)
DEF_RVV_F_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_32)
DEF_RVV_F_OPS (vfloat32m4_t, RVV_REQUIRE_ELEN_FP_32)
DEF_RVV_F_OPS (vfloat64m4_t, RVV_REQUIRE_ELEN_FP_64)
DEF_RVV_F_OPS (vfloat64m8_t, RVV_REQUIRE_ELEN_FP_64)
-DEF_RVV_B_OPS (vbool64_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_B_OPS (vbool64_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_B_OPS (vbool32_t, 0)
DEF_RVV_B_OPS (vbool16_t, 0)
DEF_RVV_B_OPS (vbool8_t, 0)
DEF_RVV_B_OPS (vbool2_t, 0)
DEF_RVV_B_OPS (vbool1_t, 0)
-DEF_RVV_WEXTI_OPS (vint16mf4_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_WEXTI_OPS (vint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_WEXTI_OPS (vint16mf2_t, 0)
DEF_RVV_WEXTI_OPS (vint16m1_t, 0)
DEF_RVV_WEXTI_OPS (vint16m2_t, 0)
DEF_RVV_WEXTI_OPS (vint16m4_t, 0)
DEF_RVV_WEXTI_OPS (vint16m8_t, 0)
-DEF_RVV_WEXTI_OPS (vint32mf2_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_WEXTI_OPS (vint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_WEXTI_OPS (vint32m1_t, 0)
DEF_RVV_WEXTI_OPS (vint32m2_t, 0)
DEF_RVV_WEXTI_OPS (vint32m4_t, 0)
DEF_RVV_WEXTI_OPS (vint32m8_t, 0)
-DEF_RVV_WEXTI_OPS (vint64m1_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_WEXTI_OPS (vint64m2_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_WEXTI_OPS (vint64m4_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_WEXTI_OPS (vint64m8_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_WEXTI_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_WEXTI_OPS (vint64m2_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_WEXTI_OPS (vint64m4_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_WEXTI_OPS (vint64m8_t, RVV_REQUIRE_ELEN_64)
-DEF_RVV_QEXTI_OPS (vint32mf2_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_QEXTI_OPS (vint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_QEXTI_OPS (vint32m1_t, 0)
DEF_RVV_QEXTI_OPS (vint32m2_t, 0)
DEF_RVV_QEXTI_OPS (vint32m4_t, 0)
DEF_RVV_QEXTI_OPS (vint32m8_t, 0)
-DEF_RVV_QEXTI_OPS (vint64m1_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_QEXTI_OPS (vint64m2_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_QEXTI_OPS (vint64m4_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_QEXTI_OPS (vint64m8_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_QEXTI_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_QEXTI_OPS (vint64m2_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_QEXTI_OPS (vint64m4_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_QEXTI_OPS (vint64m8_t, RVV_REQUIRE_ELEN_64)
-DEF_RVV_OEXTI_OPS (vint64m1_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_OEXTI_OPS (vint64m2_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_OEXTI_OPS (vint64m4_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_OEXTI_OPS (vint64m8_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_OEXTI_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_OEXTI_OPS (vint64m2_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_OEXTI_OPS (vint64m4_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_OEXTI_OPS (vint64m8_t, RVV_REQUIRE_ELEN_64)
-DEF_RVV_WEXTU_OPS (vuint16mf4_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_WEXTU_OPS (vuint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_WEXTU_OPS (vuint16mf2_t, 0)
DEF_RVV_WEXTU_OPS (vuint16m1_t, 0)
DEF_RVV_WEXTU_OPS (vuint16m2_t, 0)
DEF_RVV_WEXTU_OPS (vuint16m4_t, 0)
DEF_RVV_WEXTU_OPS (vuint16m8_t, 0)
-DEF_RVV_WEXTU_OPS (vuint32mf2_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_WEXTU_OPS (vuint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_WEXTU_OPS (vuint32m1_t, 0)
DEF_RVV_WEXTU_OPS (vuint32m2_t, 0)
DEF_RVV_WEXTU_OPS (vuint32m4_t, 0)
DEF_RVV_WEXTU_OPS (vuint32m8_t, 0)
-DEF_RVV_WEXTU_OPS (vuint64m1_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_WEXTU_OPS (vuint64m2_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_WEXTU_OPS (vuint64m4_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_WEXTU_OPS (vuint64m8_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_WEXTU_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_WEXTU_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_WEXTU_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_WEXTU_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_64)
-DEF_RVV_QEXTU_OPS (vuint32mf2_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_QEXTU_OPS (vuint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_QEXTU_OPS (vuint32m1_t, 0)
DEF_RVV_QEXTU_OPS (vuint32m2_t, 0)
DEF_RVV_QEXTU_OPS (vuint32m4_t, 0)
DEF_RVV_QEXTU_OPS (vuint32m8_t, 0)
-DEF_RVV_QEXTU_OPS (vuint64m1_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_QEXTU_OPS (vuint64m2_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_QEXTU_OPS (vuint64m4_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_QEXTU_OPS (vuint64m8_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_QEXTU_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_QEXTU_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_QEXTU_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_QEXTU_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_64)
-DEF_RVV_OEXTU_OPS (vuint64m1_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_OEXTU_OPS (vuint64m2_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_OEXTU_OPS (vuint64m4_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_OEXTU_OPS (vuint64m8_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_OEXTU_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_OEXTU_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_OEXTU_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_OEXTU_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_64)
-DEF_RVV_FULL_V_I_OPS (vint8mf8_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_FULL_V_I_OPS (vint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_FULL_V_I_OPS (vint8mf4_t, 0)
DEF_RVV_FULL_V_I_OPS (vint8mf2_t, 0)
DEF_RVV_FULL_V_I_OPS (vint8m1_t, 0)
DEF_RVV_FULL_V_I_OPS (vint8m2_t, 0)
DEF_RVV_FULL_V_I_OPS (vint8m4_t, 0)
DEF_RVV_FULL_V_I_OPS (vint8m8_t, 0)
-DEF_RVV_FULL_V_I_OPS (vint16mf4_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_FULL_V_I_OPS (vint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_FULL_V_I_OPS (vint16mf2_t, 0)
DEF_RVV_FULL_V_I_OPS (vint16m1_t, 0)
DEF_RVV_FULL_V_I_OPS (vint16m2_t, 0)
DEF_RVV_FULL_V_I_OPS (vint16m4_t, 0)
DEF_RVV_FULL_V_I_OPS (vint16m8_t, 0)
-DEF_RVV_FULL_V_I_OPS (vint32mf2_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_FULL_V_I_OPS (vint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_FULL_V_I_OPS (vint32m1_t, 0)
DEF_RVV_FULL_V_I_OPS (vint32m2_t, 0)
DEF_RVV_FULL_V_I_OPS (vint32m4_t, 0)
DEF_RVV_FULL_V_I_OPS (vint64m4_t, RVV_REQUIRE_FULL_V)
DEF_RVV_FULL_V_I_OPS (vint64m8_t, RVV_REQUIRE_FULL_V)
-DEF_RVV_FULL_V_U_OPS (vuint8mf8_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_FULL_V_U_OPS (vuint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_FULL_V_U_OPS (vuint8mf4_t, 0)
DEF_RVV_FULL_V_U_OPS (vuint8mf2_t, 0)
DEF_RVV_FULL_V_U_OPS (vuint8m1_t, 0)
DEF_RVV_FULL_V_U_OPS (vuint8m2_t, 0)
DEF_RVV_FULL_V_U_OPS (vuint8m4_t, 0)
DEF_RVV_FULL_V_U_OPS (vuint8m8_t, 0)
-DEF_RVV_FULL_V_U_OPS (vuint16mf4_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_FULL_V_U_OPS (vuint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_FULL_V_U_OPS (vuint16mf2_t, 0)
DEF_RVV_FULL_V_U_OPS (vuint16m1_t, 0)
DEF_RVV_FULL_V_U_OPS (vuint16m2_t, 0)
DEF_RVV_FULL_V_U_OPS (vuint16m4_t, 0)
DEF_RVV_FULL_V_U_OPS (vuint16m8_t, 0)
-DEF_RVV_FULL_V_U_OPS (vuint32mf2_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_FULL_V_U_OPS (vuint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_FULL_V_U_OPS (vuint32m1_t, 0)
DEF_RVV_FULL_V_U_OPS (vuint32m2_t, 0)
DEF_RVV_FULL_V_U_OPS (vuint32m4_t, 0)
DEF_RVV_WEXTF_OPS (vfloat64m4_t, RVV_REQUIRE_ELEN_FP_64)
DEF_RVV_WEXTF_OPS (vfloat64m8_t, RVV_REQUIRE_ELEN_FP_64)
-DEF_RVV_CONVERT_I_OPS (vint32mf2_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_CONVERT_I_OPS (vint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_CONVERT_I_OPS (vint32m1_t, 0)
DEF_RVV_CONVERT_I_OPS (vint32m2_t, 0)
DEF_RVV_CONVERT_I_OPS (vint32m4_t, 0)
DEF_RVV_CONVERT_I_OPS (vint32m8_t, 0)
-DEF_RVV_CONVERT_I_OPS (vint64m1_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_CONVERT_I_OPS (vint64m2_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_CONVERT_I_OPS (vint64m4_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_CONVERT_I_OPS (vint64m8_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_CONVERT_I_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_CONVERT_I_OPS (vint64m2_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_CONVERT_I_OPS (vint64m4_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_CONVERT_I_OPS (vint64m8_t, RVV_REQUIRE_ELEN_64)
-DEF_RVV_CONVERT_U_OPS (vuint32mf2_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_CONVERT_U_OPS (vuint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_CONVERT_U_OPS (vuint32m1_t, 0)
DEF_RVV_CONVERT_U_OPS (vuint32m2_t, 0)
DEF_RVV_CONVERT_U_OPS (vuint32m4_t, 0)
DEF_RVV_CONVERT_U_OPS (vuint32m8_t, 0)
-DEF_RVV_CONVERT_U_OPS (vuint64m1_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_CONVERT_U_OPS (vuint64m2_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_CONVERT_U_OPS (vuint64m4_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_CONVERT_U_OPS (vuint64m8_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_CONVERT_U_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_CONVERT_U_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_CONVERT_U_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_CONVERT_U_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_64)
-DEF_RVV_WCONVERT_I_OPS (vint64m1_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_ZVE64)
-DEF_RVV_WCONVERT_I_OPS (vint64m2_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_ZVE64)
-DEF_RVV_WCONVERT_I_OPS (vint64m4_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_ZVE64)
-DEF_RVV_WCONVERT_I_OPS (vint64m8_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_ZVE64)
+DEF_RVV_WCONVERT_I_OPS (vint64m1_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_ELEN_64)
+DEF_RVV_WCONVERT_I_OPS (vint64m2_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_ELEN_64)
+DEF_RVV_WCONVERT_I_OPS (vint64m4_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_ELEN_64)
+DEF_RVV_WCONVERT_I_OPS (vint64m8_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_ELEN_64)
-DEF_RVV_WCONVERT_U_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_ZVE64)
-DEF_RVV_WCONVERT_U_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_ZVE64)
-DEF_RVV_WCONVERT_U_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_ZVE64)
-DEF_RVV_WCONVERT_U_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_ZVE64)
+DEF_RVV_WCONVERT_U_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_ELEN_64)
+DEF_RVV_WCONVERT_U_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_ELEN_64)
+DEF_RVV_WCONVERT_U_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_ELEN_64)
+DEF_RVV_WCONVERT_U_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_ELEN_64)
DEF_RVV_WCONVERT_F_OPS (vfloat64m1_t, RVV_REQUIRE_ELEN_FP_64)
DEF_RVV_WCONVERT_F_OPS (vfloat64m2_t, RVV_REQUIRE_ELEN_FP_64)
DEF_RVV_WCONVERT_F_OPS (vfloat64m4_t, RVV_REQUIRE_ELEN_FP_64)
DEF_RVV_WCONVERT_F_OPS (vfloat64m8_t, RVV_REQUIRE_ELEN_FP_64)
-DEF_RVV_WI_OPS (vint8mf8_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_WI_OPS (vint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_WI_OPS (vint8mf4_t, 0)
DEF_RVV_WI_OPS (vint8mf2_t, 0)
DEF_RVV_WI_OPS (vint8m1_t, 0)
DEF_RVV_WI_OPS (vint8m2_t, 0)
DEF_RVV_WI_OPS (vint8m4_t, 0)
DEF_RVV_WI_OPS (vint8m8_t, 0)
-DEF_RVV_WI_OPS (vint16mf4_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_WI_OPS (vint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_WI_OPS (vint16mf2_t, 0)
DEF_RVV_WI_OPS (vint16m1_t, 0)
DEF_RVV_WI_OPS (vint16m2_t, 0)
DEF_RVV_WI_OPS (vint16m4_t, 0)
DEF_RVV_WI_OPS (vint16m8_t, 0)
-DEF_RVV_WI_OPS (vint32mf2_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_WI_OPS (vint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_WI_OPS (vint32m1_t, 0)
DEF_RVV_WI_OPS (vint32m2_t, 0)
DEF_RVV_WI_OPS (vint32m4_t, 0)
DEF_RVV_WI_OPS (vint32m8_t, 0)
-DEF_RVV_WU_OPS (vuint8mf8_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_WU_OPS (vuint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_WU_OPS (vuint8mf4_t, 0)
DEF_RVV_WU_OPS (vuint8mf2_t, 0)
DEF_RVV_WU_OPS (vuint8m1_t, 0)
DEF_RVV_WU_OPS (vuint8m2_t, 0)
DEF_RVV_WU_OPS (vuint8m4_t, 0)
DEF_RVV_WU_OPS (vuint8m8_t, 0)
-DEF_RVV_WU_OPS (vuint16mf4_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_WU_OPS (vuint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_WU_OPS (vuint16mf2_t, 0)
DEF_RVV_WU_OPS (vuint16m1_t, 0)
DEF_RVV_WU_OPS (vuint16m2_t, 0)
DEF_RVV_WU_OPS (vuint16m4_t, 0)
DEF_RVV_WU_OPS (vuint16m8_t, 0)
-DEF_RVV_WU_OPS (vuint32mf2_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_WU_OPS (vuint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_WU_OPS (vuint32m1_t, 0)
DEF_RVV_WU_OPS (vuint32m2_t, 0)
DEF_RVV_WU_OPS (vuint32m4_t, 0)
DEF_RVV_WU_OPS (vuint32m8_t, 0)
-DEF_RVV_WF_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_ZVE64)
+DEF_RVV_WF_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_WF_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32)
DEF_RVV_WF_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_32)
DEF_RVV_WF_OPS (vfloat32m4_t, RVV_REQUIRE_ELEN_FP_32)
DEF_RVV_WF_OPS (vfloat32m8_t, RVV_REQUIRE_ELEN_FP_32)
-DEF_RVV_EI16_OPS (vint8mf8_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_EI16_OPS (vint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_EI16_OPS (vint8mf4_t, 0)
DEF_RVV_EI16_OPS (vint8mf2_t, 0)
DEF_RVV_EI16_OPS (vint8m1_t, 0)
DEF_RVV_EI16_OPS (vint8m2_t, 0)
DEF_RVV_EI16_OPS (vint8m4_t, 0)
-DEF_RVV_EI16_OPS (vint16mf4_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_EI16_OPS (vint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_EI16_OPS (vint16mf2_t, 0)
DEF_RVV_EI16_OPS (vint16m1_t, 0)
DEF_RVV_EI16_OPS (vint16m2_t, 0)
DEF_RVV_EI16_OPS (vint16m4_t, 0)
DEF_RVV_EI16_OPS (vint16m8_t, 0)
-DEF_RVV_EI16_OPS (vint32mf2_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_EI16_OPS (vint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_EI16_OPS (vint32m1_t, 0)
DEF_RVV_EI16_OPS (vint32m2_t, 0)
DEF_RVV_EI16_OPS (vint32m4_t, 0)
DEF_RVV_EI16_OPS (vint32m8_t, 0)
-DEF_RVV_EI16_OPS (vint64m1_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_EI16_OPS (vint64m2_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_EI16_OPS (vint64m4_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_EI16_OPS (vint64m8_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_EI16_OPS (vuint8mf8_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_EI16_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_EI16_OPS (vint64m2_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_EI16_OPS (vint64m4_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_EI16_OPS (vint64m8_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_EI16_OPS (vuint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_EI16_OPS (vuint8mf4_t, 0)
DEF_RVV_EI16_OPS (vuint8mf2_t, 0)
DEF_RVV_EI16_OPS (vuint8m1_t, 0)
DEF_RVV_EI16_OPS (vuint8m2_t, 0)
DEF_RVV_EI16_OPS (vuint8m4_t, 0)
-DEF_RVV_EI16_OPS (vuint16mf4_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_EI16_OPS (vuint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_EI16_OPS (vuint16mf2_t, 0)
DEF_RVV_EI16_OPS (vuint16m1_t, 0)
DEF_RVV_EI16_OPS (vuint16m2_t, 0)
DEF_RVV_EI16_OPS (vuint16m4_t, 0)
DEF_RVV_EI16_OPS (vuint16m8_t, 0)
-DEF_RVV_EI16_OPS (vuint32mf2_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_EI16_OPS (vuint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_EI16_OPS (vuint32m1_t, 0)
DEF_RVV_EI16_OPS (vuint32m2_t, 0)
DEF_RVV_EI16_OPS (vuint32m4_t, 0)
DEF_RVV_EI16_OPS (vuint32m8_t, 0)
-DEF_RVV_EI16_OPS (vuint64m1_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_EI16_OPS (vuint64m2_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_EI16_OPS (vuint64m4_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_EI16_OPS (vuint64m8_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_EI16_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_ZVE64)
+DEF_RVV_EI16_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_EI16_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_EI16_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_EI16_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_EI16_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_EI16_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32)
DEF_RVV_EI16_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_32)
DEF_RVV_EI16_OPS (vfloat32m4_t, RVV_REQUIRE_ELEN_FP_32)
DEF_RVV_EI16_OPS (vfloat64m4_t, RVV_REQUIRE_ELEN_FP_64)
DEF_RVV_EI16_OPS (vfloat64m8_t, RVV_REQUIRE_ELEN_FP_64)
-DEF_RVV_EEW8_INTERPRET_OPS (vint16mf4_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_EEW8_INTERPRET_OPS (vint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_EEW8_INTERPRET_OPS (vint16mf2_t, 0)
DEF_RVV_EEW8_INTERPRET_OPS (vint16m1_t, 0)
DEF_RVV_EEW8_INTERPRET_OPS (vint16m2_t, 0)
DEF_RVV_EEW8_INTERPRET_OPS (vint16m4_t, 0)
DEF_RVV_EEW8_INTERPRET_OPS (vint16m8_t, 0)
-DEF_RVV_EEW8_INTERPRET_OPS (vint32mf2_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_EEW8_INTERPRET_OPS (vint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_EEW8_INTERPRET_OPS (vint32m1_t, 0)
DEF_RVV_EEW8_INTERPRET_OPS (vint32m2_t, 0)
DEF_RVV_EEW8_INTERPRET_OPS (vint32m4_t, 0)
DEF_RVV_EEW8_INTERPRET_OPS (vint32m8_t, 0)
-DEF_RVV_EEW8_INTERPRET_OPS (vint64m1_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_EEW8_INTERPRET_OPS (vint64m2_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_EEW8_INTERPRET_OPS (vint64m4_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_EEW8_INTERPRET_OPS (vint64m8_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_EEW8_INTERPRET_OPS (vuint16mf4_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_EEW8_INTERPRET_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_EEW8_INTERPRET_OPS (vint64m2_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_EEW8_INTERPRET_OPS (vint64m4_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_EEW8_INTERPRET_OPS (vint64m8_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_EEW8_INTERPRET_OPS (vuint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_EEW8_INTERPRET_OPS (vuint16mf2_t, 0)
DEF_RVV_EEW8_INTERPRET_OPS (vuint16m1_t, 0)
DEF_RVV_EEW8_INTERPRET_OPS (vuint16m2_t, 0)
DEF_RVV_EEW8_INTERPRET_OPS (vuint16m4_t, 0)
DEF_RVV_EEW8_INTERPRET_OPS (vuint16m8_t, 0)
-DEF_RVV_EEW8_INTERPRET_OPS (vuint32mf2_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_EEW8_INTERPRET_OPS (vuint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_EEW8_INTERPRET_OPS (vuint32m1_t, 0)
DEF_RVV_EEW8_INTERPRET_OPS (vuint32m2_t, 0)
DEF_RVV_EEW8_INTERPRET_OPS (vuint32m4_t, 0)
DEF_RVV_EEW8_INTERPRET_OPS (vuint32m8_t, 0)
-DEF_RVV_EEW8_INTERPRET_OPS (vuint64m1_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_EEW8_INTERPRET_OPS (vuint64m2_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_EEW8_INTERPRET_OPS (vuint64m4_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_EEW8_INTERPRET_OPS (vuint64m8_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_EEW8_INTERPRET_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_EEW8_INTERPRET_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_EEW8_INTERPRET_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_EEW8_INTERPRET_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_64)
DEF_RVV_EEW16_INTERPRET_OPS (vint8mf4_t, 0)
DEF_RVV_EEW16_INTERPRET_OPS (vint8mf2_t, 0)
DEF_RVV_EEW16_INTERPRET_OPS (vint8m2_t, 0)
DEF_RVV_EEW16_INTERPRET_OPS (vint8m4_t, 0)
DEF_RVV_EEW16_INTERPRET_OPS (vint8m8_t, 0)
-DEF_RVV_EEW16_INTERPRET_OPS (vint32mf2_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_EEW16_INTERPRET_OPS (vint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_EEW16_INTERPRET_OPS (vint32m1_t, 0)
DEF_RVV_EEW16_INTERPRET_OPS (vint32m2_t, 0)
DEF_RVV_EEW16_INTERPRET_OPS (vint32m4_t, 0)
DEF_RVV_EEW16_INTERPRET_OPS (vint32m8_t, 0)
-DEF_RVV_EEW16_INTERPRET_OPS (vint64m1_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_EEW16_INTERPRET_OPS (vint64m2_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_EEW16_INTERPRET_OPS (vint64m4_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_EEW16_INTERPRET_OPS (vint64m8_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_EEW16_INTERPRET_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_EEW16_INTERPRET_OPS (vint64m2_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_EEW16_INTERPRET_OPS (vint64m4_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_EEW16_INTERPRET_OPS (vint64m8_t, RVV_REQUIRE_ELEN_64)
DEF_RVV_EEW16_INTERPRET_OPS (vuint8mf4_t, 0)
DEF_RVV_EEW16_INTERPRET_OPS (vuint8mf2_t, 0)
DEF_RVV_EEW16_INTERPRET_OPS (vuint8m1_t, 0)
DEF_RVV_EEW16_INTERPRET_OPS (vuint8m2_t, 0)
DEF_RVV_EEW16_INTERPRET_OPS (vuint8m4_t, 0)
DEF_RVV_EEW16_INTERPRET_OPS (vuint8m8_t, 0)
-DEF_RVV_EEW16_INTERPRET_OPS (vuint32mf2_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_EEW16_INTERPRET_OPS (vuint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_EEW16_INTERPRET_OPS (vuint32m1_t, 0)
DEF_RVV_EEW16_INTERPRET_OPS (vuint32m2_t, 0)
DEF_RVV_EEW16_INTERPRET_OPS (vuint32m4_t, 0)
DEF_RVV_EEW16_INTERPRET_OPS (vuint32m8_t, 0)
-DEF_RVV_EEW16_INTERPRET_OPS (vuint64m1_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_EEW16_INTERPRET_OPS (vuint64m2_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_EEW16_INTERPRET_OPS (vuint64m4_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_EEW16_INTERPRET_OPS (vuint64m8_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_EEW16_INTERPRET_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_EEW16_INTERPRET_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_EEW16_INTERPRET_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_EEW16_INTERPRET_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_64)
DEF_RVV_EEW32_INTERPRET_OPS (vint8mf2_t, 0)
DEF_RVV_EEW32_INTERPRET_OPS (vint8m1_t, 0)
DEF_RVV_EEW32_INTERPRET_OPS (vint16m2_t, 0)
DEF_RVV_EEW32_INTERPRET_OPS (vint16m4_t, 0)
DEF_RVV_EEW32_INTERPRET_OPS (vint16m8_t, 0)
-DEF_RVV_EEW32_INTERPRET_OPS (vint64m1_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_EEW32_INTERPRET_OPS (vint64m2_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_EEW32_INTERPRET_OPS (vint64m4_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_EEW32_INTERPRET_OPS (vint64m8_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_EEW32_INTERPRET_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_EEW32_INTERPRET_OPS (vint64m2_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_EEW32_INTERPRET_OPS (vint64m4_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_EEW32_INTERPRET_OPS (vint64m8_t, RVV_REQUIRE_ELEN_64)
DEF_RVV_EEW32_INTERPRET_OPS (vuint8mf2_t, 0)
DEF_RVV_EEW32_INTERPRET_OPS (vuint8m1_t, 0)
DEF_RVV_EEW32_INTERPRET_OPS (vuint8m2_t, 0)
DEF_RVV_EEW32_INTERPRET_OPS (vuint16m2_t, 0)
DEF_RVV_EEW32_INTERPRET_OPS (vuint16m4_t, 0)
DEF_RVV_EEW32_INTERPRET_OPS (vuint16m8_t, 0)
-DEF_RVV_EEW32_INTERPRET_OPS (vuint64m1_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_EEW32_INTERPRET_OPS (vuint64m2_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_EEW32_INTERPRET_OPS (vuint64m4_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_EEW32_INTERPRET_OPS (vuint64m8_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_EEW32_INTERPRET_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_EEW32_INTERPRET_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_EEW32_INTERPRET_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_EEW32_INTERPRET_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_64)
DEF_RVV_EEW64_INTERPRET_OPS (vint8m1_t, 0)
DEF_RVV_EEW64_INTERPRET_OPS (vint8m2_t, 0)
DEF_RVV_EEW64_INTERPRET_OPS (vuint32m4_t, 0)
DEF_RVV_EEW64_INTERPRET_OPS (vuint32m8_t, 0)
-DEF_RVV_X2_VLMUL_EXT_OPS (vint8mf8_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_X2_VLMUL_EXT_OPS (vint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X2_VLMUL_EXT_OPS (vint8mf4_t, 0)
DEF_RVV_X2_VLMUL_EXT_OPS (vint8mf2_t, 0)
DEF_RVV_X2_VLMUL_EXT_OPS (vint8m1_t, 0)
DEF_RVV_X2_VLMUL_EXT_OPS (vint8m2_t, 0)
DEF_RVV_X2_VLMUL_EXT_OPS (vint8m4_t, 0)
-DEF_RVV_X2_VLMUL_EXT_OPS (vint16mf4_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_X2_VLMUL_EXT_OPS (vint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X2_VLMUL_EXT_OPS (vint16mf2_t, 0)
DEF_RVV_X2_VLMUL_EXT_OPS (vint16m1_t, 0)
DEF_RVV_X2_VLMUL_EXT_OPS (vint16m2_t, 0)
DEF_RVV_X2_VLMUL_EXT_OPS (vint16m4_t, 0)
-DEF_RVV_X2_VLMUL_EXT_OPS (vint32mf2_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_X2_VLMUL_EXT_OPS (vint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X2_VLMUL_EXT_OPS (vint32m1_t, 0)
DEF_RVV_X2_VLMUL_EXT_OPS (vint32m2_t, 0)
DEF_RVV_X2_VLMUL_EXT_OPS (vint32m4_t, 0)
-DEF_RVV_X2_VLMUL_EXT_OPS (vint64m1_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_X2_VLMUL_EXT_OPS (vint64m2_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_X2_VLMUL_EXT_OPS (vint64m4_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_X2_VLMUL_EXT_OPS (vuint8mf8_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_X2_VLMUL_EXT_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_X2_VLMUL_EXT_OPS (vint64m2_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_X2_VLMUL_EXT_OPS (vint64m4_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_X2_VLMUL_EXT_OPS (vuint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X2_VLMUL_EXT_OPS (vuint8mf4_t, 0)
DEF_RVV_X2_VLMUL_EXT_OPS (vuint8mf2_t, 0)
DEF_RVV_X2_VLMUL_EXT_OPS (vuint8m1_t, 0)
DEF_RVV_X2_VLMUL_EXT_OPS (vuint8m2_t, 0)
DEF_RVV_X2_VLMUL_EXT_OPS (vuint8m4_t, 0)
-DEF_RVV_X2_VLMUL_EXT_OPS (vuint16mf4_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_X2_VLMUL_EXT_OPS (vuint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X2_VLMUL_EXT_OPS (vuint16mf2_t, 0)
DEF_RVV_X2_VLMUL_EXT_OPS (vuint16m1_t, 0)
DEF_RVV_X2_VLMUL_EXT_OPS (vuint16m2_t, 0)
DEF_RVV_X2_VLMUL_EXT_OPS (vuint16m4_t, 0)
-DEF_RVV_X2_VLMUL_EXT_OPS (vuint32mf2_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_X2_VLMUL_EXT_OPS (vuint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X2_VLMUL_EXT_OPS (vuint32m1_t, 0)
DEF_RVV_X2_VLMUL_EXT_OPS (vuint32m2_t, 0)
DEF_RVV_X2_VLMUL_EXT_OPS (vuint32m4_t, 0)
-DEF_RVV_X2_VLMUL_EXT_OPS (vuint64m1_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_X2_VLMUL_EXT_OPS (vuint64m2_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_X2_VLMUL_EXT_OPS (vuint64m4_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_X2_VLMUL_EXT_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_ZVE64)
+DEF_RVV_X2_VLMUL_EXT_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_X2_VLMUL_EXT_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_X2_VLMUL_EXT_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_X2_VLMUL_EXT_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X2_VLMUL_EXT_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32)
DEF_RVV_X2_VLMUL_EXT_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_32)
DEF_RVV_X2_VLMUL_EXT_OPS (vfloat32m4_t, RVV_REQUIRE_ELEN_FP_32)
DEF_RVV_X2_VLMUL_EXT_OPS (vfloat64m2_t, RVV_REQUIRE_ELEN_FP_64)
DEF_RVV_X2_VLMUL_EXT_OPS (vfloat64m4_t, RVV_REQUIRE_ELEN_FP_64)
-DEF_RVV_X4_VLMUL_EXT_OPS (vint8mf8_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_X4_VLMUL_EXT_OPS (vint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X4_VLMUL_EXT_OPS (vint8mf4_t, 0)
DEF_RVV_X4_VLMUL_EXT_OPS (vint8mf2_t, 0)
DEF_RVV_X4_VLMUL_EXT_OPS (vint8m1_t, 0)
DEF_RVV_X4_VLMUL_EXT_OPS (vint8m2_t, 0)
-DEF_RVV_X4_VLMUL_EXT_OPS (vint16mf4_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_X4_VLMUL_EXT_OPS (vint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X4_VLMUL_EXT_OPS (vint16mf2_t, 0)
DEF_RVV_X4_VLMUL_EXT_OPS (vint16m1_t, 0)
DEF_RVV_X4_VLMUL_EXT_OPS (vint16m2_t, 0)
-DEF_RVV_X4_VLMUL_EXT_OPS (vint32mf2_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_X4_VLMUL_EXT_OPS (vint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X4_VLMUL_EXT_OPS (vint32m1_t, 0)
DEF_RVV_X4_VLMUL_EXT_OPS (vint32m2_t, 0)
-DEF_RVV_X4_VLMUL_EXT_OPS (vint64m1_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_X4_VLMUL_EXT_OPS (vint64m2_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_X4_VLMUL_EXT_OPS (vuint8mf8_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_X4_VLMUL_EXT_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_X4_VLMUL_EXT_OPS (vint64m2_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_X4_VLMUL_EXT_OPS (vuint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X4_VLMUL_EXT_OPS (vuint8mf4_t, 0)
DEF_RVV_X4_VLMUL_EXT_OPS (vuint8mf2_t, 0)
DEF_RVV_X4_VLMUL_EXT_OPS (vuint8m1_t, 0)
DEF_RVV_X4_VLMUL_EXT_OPS (vuint8m2_t, 0)
-DEF_RVV_X4_VLMUL_EXT_OPS (vuint16mf4_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_X4_VLMUL_EXT_OPS (vuint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X4_VLMUL_EXT_OPS (vuint16mf2_t, 0)
DEF_RVV_X4_VLMUL_EXT_OPS (vuint16m1_t, 0)
DEF_RVV_X4_VLMUL_EXT_OPS (vuint16m2_t, 0)
-DEF_RVV_X4_VLMUL_EXT_OPS (vuint32mf2_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_X4_VLMUL_EXT_OPS (vuint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X4_VLMUL_EXT_OPS (vuint32m1_t, 0)
DEF_RVV_X4_VLMUL_EXT_OPS (vuint32m2_t, 0)
-DEF_RVV_X4_VLMUL_EXT_OPS (vuint64m1_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_X4_VLMUL_EXT_OPS (vuint64m2_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_X4_VLMUL_EXT_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_ZVE64)
+DEF_RVV_X4_VLMUL_EXT_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_X4_VLMUL_EXT_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_X4_VLMUL_EXT_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X4_VLMUL_EXT_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32)
DEF_RVV_X4_VLMUL_EXT_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_32)
DEF_RVV_X4_VLMUL_EXT_OPS (vfloat64m1_t, RVV_REQUIRE_ELEN_FP_64)
DEF_RVV_X4_VLMUL_EXT_OPS (vfloat64m2_t, RVV_REQUIRE_ELEN_FP_64)
-DEF_RVV_X8_VLMUL_EXT_OPS (vint8mf8_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_X8_VLMUL_EXT_OPS (vint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X8_VLMUL_EXT_OPS (vint8mf4_t, 0)
DEF_RVV_X8_VLMUL_EXT_OPS (vint8mf2_t, 0)
DEF_RVV_X8_VLMUL_EXT_OPS (vint8m1_t, 0)
-DEF_RVV_X8_VLMUL_EXT_OPS (vint16mf4_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_X8_VLMUL_EXT_OPS (vint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X8_VLMUL_EXT_OPS (vint16mf2_t, 0)
DEF_RVV_X8_VLMUL_EXT_OPS (vint16m1_t, 0)
-DEF_RVV_X8_VLMUL_EXT_OPS (vint32mf2_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_X8_VLMUL_EXT_OPS (vint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X8_VLMUL_EXT_OPS (vint32m1_t, 0)
-DEF_RVV_X8_VLMUL_EXT_OPS (vint64m1_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_X8_VLMUL_EXT_OPS (vuint8mf8_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_X8_VLMUL_EXT_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_X8_VLMUL_EXT_OPS (vuint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X8_VLMUL_EXT_OPS (vuint8mf4_t, 0)
DEF_RVV_X8_VLMUL_EXT_OPS (vuint8mf2_t, 0)
DEF_RVV_X8_VLMUL_EXT_OPS (vuint8m1_t, 0)
-DEF_RVV_X8_VLMUL_EXT_OPS (vuint16mf4_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_X8_VLMUL_EXT_OPS (vuint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X8_VLMUL_EXT_OPS (vuint16mf2_t, 0)
DEF_RVV_X8_VLMUL_EXT_OPS (vuint16m1_t, 0)
-DEF_RVV_X8_VLMUL_EXT_OPS (vuint32mf2_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_X8_VLMUL_EXT_OPS (vuint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X8_VLMUL_EXT_OPS (vuint32m1_t, 0)
-DEF_RVV_X8_VLMUL_EXT_OPS (vuint64m1_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_X8_VLMUL_EXT_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_ZVE64)
+DEF_RVV_X8_VLMUL_EXT_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_X8_VLMUL_EXT_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X8_VLMUL_EXT_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32)
DEF_RVV_X8_VLMUL_EXT_OPS (vfloat64m1_t, RVV_REQUIRE_ELEN_FP_64)
-DEF_RVV_X16_VLMUL_EXT_OPS (vint8mf8_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_X16_VLMUL_EXT_OPS (vint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X16_VLMUL_EXT_OPS (vint8mf4_t, 0)
DEF_RVV_X16_VLMUL_EXT_OPS (vint8mf2_t, 0)
-DEF_RVV_X16_VLMUL_EXT_OPS (vint16mf4_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_X16_VLMUL_EXT_OPS (vint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X16_VLMUL_EXT_OPS (vint16mf2_t, 0)
-DEF_RVV_X16_VLMUL_EXT_OPS (vint32mf2_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_X16_VLMUL_EXT_OPS (vuint8mf8_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_X16_VLMUL_EXT_OPS (vint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
+DEF_RVV_X16_VLMUL_EXT_OPS (vuint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X16_VLMUL_EXT_OPS (vuint8mf4_t, 0)
DEF_RVV_X16_VLMUL_EXT_OPS (vuint8mf2_t, 0)
-DEF_RVV_X16_VLMUL_EXT_OPS (vuint16mf4_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_X16_VLMUL_EXT_OPS (vuint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X16_VLMUL_EXT_OPS (vuint16mf2_t, 0)
-DEF_RVV_X16_VLMUL_EXT_OPS (vuint32mf2_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_X16_VLMUL_EXT_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_ZVE64)
+DEF_RVV_X16_VLMUL_EXT_OPS (vuint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
+DEF_RVV_X16_VLMUL_EXT_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_MIN_VLEN_64)
-DEF_RVV_X32_VLMUL_EXT_OPS (vint8mf8_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_X32_VLMUL_EXT_OPS (vint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X32_VLMUL_EXT_OPS (vint8mf4_t, 0)
-DEF_RVV_X32_VLMUL_EXT_OPS (vint16mf4_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_X32_VLMUL_EXT_OPS (vuint8mf8_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_X32_VLMUL_EXT_OPS (vint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
+DEF_RVV_X32_VLMUL_EXT_OPS (vuint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X32_VLMUL_EXT_OPS (vuint8mf4_t, 0)
-DEF_RVV_X32_VLMUL_EXT_OPS (vuint16mf4_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_X32_VLMUL_EXT_OPS (vuint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
-DEF_RVV_X64_VLMUL_EXT_OPS (vint8mf8_t, RVV_REQUIRE_ZVE64)
-DEF_RVV_X64_VLMUL_EXT_OPS (vuint8mf8_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_X64_VLMUL_EXT_OPS (vint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
+DEF_RVV_X64_VLMUL_EXT_OPS (vuint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_LMUL1_OPS (vint8m1_t, 0)
DEF_RVV_LMUL1_OPS (vint16m1_t, 0)
DEF_RVV_LMUL1_OPS (vint32m1_t, 0)
-DEF_RVV_LMUL1_OPS (vint64m1_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_LMUL1_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64)
DEF_RVV_LMUL1_OPS (vuint8m1_t, 0)
DEF_RVV_LMUL1_OPS (vuint16m1_t, 0)
DEF_RVV_LMUL1_OPS (vuint32m1_t, 0)
-DEF_RVV_LMUL1_OPS (vuint64m1_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_LMUL1_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
DEF_RVV_LMUL1_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32)
DEF_RVV_LMUL1_OPS (vfloat64m1_t, RVV_REQUIRE_ELEN_FP_64)
DEF_RVV_LMUL2_OPS (vint8m2_t, 0)
DEF_RVV_LMUL2_OPS (vint16m2_t, 0)
DEF_RVV_LMUL2_OPS (vint32m2_t, 0)
-DEF_RVV_LMUL2_OPS (vint64m2_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_LMUL2_OPS (vint64m2_t, RVV_REQUIRE_ELEN_64)
DEF_RVV_LMUL2_OPS (vuint8m2_t, 0)
DEF_RVV_LMUL2_OPS (vuint16m2_t, 0)
DEF_RVV_LMUL2_OPS (vuint32m2_t, 0)
-DEF_RVV_LMUL2_OPS (vuint64m2_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_LMUL2_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64)
DEF_RVV_LMUL2_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_32)
DEF_RVV_LMUL2_OPS (vfloat64m2_t, RVV_REQUIRE_ELEN_FP_64)
DEF_RVV_LMUL4_OPS (vint8m4_t, 0)
DEF_RVV_LMUL4_OPS (vint16m4_t, 0)
DEF_RVV_LMUL4_OPS (vint32m4_t, 0)
-DEF_RVV_LMUL4_OPS (vint64m4_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_LMUL4_OPS (vint64m4_t, RVV_REQUIRE_ELEN_64)
DEF_RVV_LMUL4_OPS (vuint8m4_t, 0)
DEF_RVV_LMUL4_OPS (vuint16m4_t, 0)
DEF_RVV_LMUL4_OPS (vuint32m4_t, 0)
-DEF_RVV_LMUL4_OPS (vuint64m4_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_LMUL4_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64)
DEF_RVV_LMUL4_OPS (vfloat32m4_t, RVV_REQUIRE_ELEN_FP_32)
DEF_RVV_LMUL4_OPS (vfloat64m4_t, RVV_REQUIRE_ELEN_FP_64)