drm/i915: Ignore minimum lines for level 0 in skl_compute_plane_wm, v2.

According to bspec, result_lines > 31 is only a maximum for latency
level 1 through 7.

For level 0 the number of lines is ignored, so always write 0 there
to prevent overflowing the 5 bits value.

This is required to make NV12 work.

Changes since v1:
- Rebase on top of GEN11 wm changes. It seems to use res_lines for
  level 0 limit calculations, but still doesn't appear to program it.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> #v1
Link: https://patchwork.freedesktop.org/patch/msgid/20180205105841.31634-1-maarten.lankhorst@linux.intel.com

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index eb68abf..41f26ab 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4596,7 +4596,8 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
                min_disp_buf_needed = res_blocks;
        }
 
-       if (res_blocks >= ddb_allocation || res_lines > 31 ||
+       if ((level > 0 && res_lines > 31) ||
+           res_blocks >= ddb_allocation ||
            min_disp_buf_needed >= ddb_allocation) {
                *enabled = false;
 
@@ -4617,8 +4618,9 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
                }
        }
 
+       /* The number of lines are ignored for the level 0 watermark. */
+       *out_lines = level ? res_lines : 0;
        *out_blocks = res_blocks;
-       *out_lines = res_lines;
        *enabled = true;
 
        return 0;