goto fail_base;
}
+ device->vk.supported_sync_types = device->ws->get_sync_types(device->ws);
+
#ifndef _WIN32
if (drm_device && instance->vk.enabled_extensions.KHR_display) {
master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
struct radeon_info;
struct ac_surf_info;
struct radeon_surf;
+struct vk_sync_type;
enum radeon_bo_domain { /* bitfield */
RADEON_DOMAIN_GTT = 2,
int (*import_syncobj_from_sync_file)(struct radeon_winsys *ws, uint32_t syncobj, int fd);
int (*get_fd)(struct radeon_winsys *ws);
+
+ const struct vk_sync_type *const *(*get_sync_types)(struct radeon_winsys *ws);
};
static inline void
#include "radv_amdgpu_surface.h"
#include "radv_amdgpu_winsys_public.h"
#include "radv_debug.h"
+#include "vk_drm_syncobj.h"
#include "xf86drm.h"
static bool
return amdgpu_device_get_fd(ws->dev);
}
+static const struct vk_sync_type *const *
+radv_amdgpu_winsys_get_sync_types(struct radeon_winsys *rws)
+{
+ struct radv_amdgpu_winsys *ws = (struct radv_amdgpu_winsys *)rws;
+ return ws->sync_types;
+}
+
struct radeon_winsys *
radv_amdgpu_winsys_create(int fd, uint64_t debug_flags, uint64_t perftest_flags, bool reserve_vmid)
{
if (r)
goto vmid_fail;
}
+ int num_sync_types = 0;
+
+ ws->syncobj_sync_type = vk_drm_syncobj_get_type(amdgpu_device_get_fd(ws->dev));
+ if (ws->syncobj_sync_type.features) {
+ ws->sync_types[num_sync_types++] = &ws->syncobj_sync_type;
+ if (!(ws->syncobj_sync_type.features & VK_SYNC_FEATURE_TIMELINE)) {
+ ws->emulated_timeline_sync_type = vk_sync_timeline_get_type(&ws->syncobj_sync_type);
+ ws->sync_types[num_sync_types++] = &ws->emulated_timeline_sync_type.sync;
+ }
+ }
+
+ ws->sync_types[num_sync_types++] = NULL;
+ assert(num_sync_types <= ARRAY_SIZE(ws->sync_types));
ws->perftest = perftest_flags;
ws->zero_all_vram_allocs = debug_flags & RADV_DEBUG_ZERO_VRAM;
ws->base.get_chip_name = radv_amdgpu_winsys_get_chip_name;
ws->base.destroy = radv_amdgpu_winsys_destroy;
ws->base.get_fd = radv_amdgpu_winsys_get_fd;
+ ws->base.get_sync_types = radv_amdgpu_winsys_get_sync_types;
radv_amdgpu_bo_init_functions(ws);
radv_amdgpu_cs_init_functions(ws);
radv_amdgpu_surface_init_functions(ws);
#include "ac_gpu_info.h"
#include "radv_radeon_winsys.h"
+#include "vk_sync.h"
+#include "vk_sync_timeline.h"
+
struct radv_amdgpu_winsys {
struct radeon_winsys base;
amdgpu_device_handle dev;
struct u_rwlock log_bo_list_lock;
struct list_head log_bo_list;
+ const struct vk_sync_type *sync_types[3];
+ struct vk_sync_type syncobj_sync_type;
+ struct vk_sync_timeline_type emulated_timeline_sync_type;
+
uint32_t refcount;
};
#include "util/u_string.h"
#include "radv_null_bo.h"
#include "radv_null_cs.h"
+#include "vk_sync_dummy.h"
/* Hardcode some GPU info that are needed for the driver or for some tools. */
static const struct {
return -1;
}
+static const struct vk_sync_type *const *
+radv_null_winsys_get_sync_types(struct radeon_winsys *rws)
+{
+ return radv_null_winsys(rws)->sync_types;
+}
+
struct radeon_winsys *
radv_null_winsys_create()
{
ws->base.destroy = radv_null_winsys_destroy;
ws->base.query_info = radv_null_winsys_query_info;
ws->base.get_fd = radv_null_winsys_get_fd;
+ ws->base.get_sync_types = radv_null_winsys_get_sync_types;
radv_null_bo_init_functions(ws);
radv_null_cs_init_functions(ws);
+ ws->sync_types[0] = &vk_sync_dummy_type;
+ ws->sync_types[1] = NULL;
return &ws->base;
}
#include "ac_gpu_info.h"
#include "radv_radeon_winsys.h"
+struct vk_sync_type;
+
struct radv_null_winsys {
struct radeon_winsys base;
+ const struct vk_sync_type *sync_types[2];
};
static inline struct radv_null_winsys *