drm/mediatek: add background color input select function for ovl/ovl_2l

This patch add background color input select function for ovl/ovl_2l

ovl include 4 DRAM layer and 1 background color layer
ovl_2l include 4 DRAM layer and 1 background color layer
DRAM layer frame buffer data from render hardware, GPU for example.
backgournd color layer is embed in ovl/ovl_2l, we can only set
it color, but not support DRAM frame buffer.

for ovl0->ovl0_2l direct link usecase,
we need set ovl0_2l background color intput select from ovl0
if render send DRAM buffer layer number <=4, all these layer read
by ovl.
layer0 is at the bottom of all layers.
layer3 is at the top of all layers.
if render send DRAM buffer layer numbfer >=4 && <=6
ovl0 read layer0~3
ovl0_2l read layer4~5
layer5 is at the top ot all these layers.

the decision of how to setting ovl0/ovl0_2l read these layer data
is controlled in mtk crtc, which will be another patch

Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 11b2049..7a87196 100644 (file)
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -19,6 +19,8 @@
 #define DISP_REG_OVL_EN                                0x000c
 #define DISP_REG_OVL_RST                       0x0014
 #define DISP_REG_OVL_ROI_SIZE                  0x0020
+#define DISP_REG_OVL_DATAPATH_CON              0x0024
+#define OVL_BGCLR_SEL_IN                               BIT(2)
 #define DISP_REG_OVL_ROI_BGCLR                 0x0028
 #define DISP_REG_OVL_SRC_CON                   0x002c
 #define DISP_REG_OVL_CON(n)                    (0x0030 + 0x20 * (n))
@@ -237,6 +239,24 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
                mtk_ovl_layer_on(comp, idx);
 }
 
+static void mtk_ovl_bgclr_in_on(struct mtk_ddp_comp *comp)
+{
+       unsigned int reg;
+
+       reg = readl(comp->regs + DISP_REG_OVL_DATAPATH_CON);
+       reg = reg | OVL_BGCLR_SEL_IN;
+       writel(reg, comp->regs + DISP_REG_OVL_DATAPATH_CON);
+}
+
+static void mtk_ovl_bgclr_in_off(struct mtk_ddp_comp *comp)
+{
+       unsigned int reg;
+
+       reg = readl(comp->regs + DISP_REG_OVL_DATAPATH_CON);
+       reg = reg & ~OVL_BGCLR_SEL_IN;
+       writel(reg, comp->regs + DISP_REG_OVL_DATAPATH_CON);
+}
+
 static const struct mtk_ddp_comp_funcs mtk_disp_ovl_funcs = {
        .config = mtk_ovl_config,
        .start = mtk_ovl_start,
@@ -247,6 +267,8 @@ static const struct mtk_ddp_comp_funcs mtk_disp_ovl_funcs = {
        .layer_on = mtk_ovl_layer_on,
        .layer_off = mtk_ovl_layer_off,
        .layer_config = mtk_ovl_layer_config,
+       .bgclr_in_on = mtk_ovl_bgclr_in_on,
+       .bgclr_in_off = mtk_ovl_bgclr_in_off,
 };
 
 static int mtk_disp_ovl_bind(struct device *dev, struct device *master,