clk: qcom: gcc: Remove CPUSS clocks control for SC7280

The CPUSS clocks are kept always ON and at a fixed frequency of 100MHZ
from the bootloader and no longer required to be controlled from HLOS.

Fixes: a3cc092196ef ("clk: qcom: Add Global Clock controller (GCC) driver for SC7280")
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1633579571-25475-1-git-send-email-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/qcom/gcc-sc7280.c b/drivers/clk/qcom/gcc-sc7280.c
index 6cefcdc..667f584 100644 (file)
--- a/drivers/clk/qcom/gcc-sc7280.c
+++ b/drivers/clk/qcom/gcc-sc7280.c
@@ -479,24 +479,6 @@ static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src = {
                },
        },
 };
-static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
-       F(19200000, P_BI_TCXO, 1, 0, 0),
-       { }
-};
-
-static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
-       .cmd_rcgr = 0x4800c,
-       .mnd_width = 0,
-       .hid_width = 5,
-       .parent_map = gcc_parent_map_0,
-       .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
-       .clkr.hw.init = &(struct clk_init_data){
-               .name = "gcc_cpuss_ahb_clk_src",
-               .parent_data = gcc_parent_data_0_ao,
-               .num_parents = ARRAY_SIZE(gcc_parent_data_0_ao),
-               .ops = &clk_rcg2_ops,
-       },
-};
 
 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
        F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
@@ -1239,21 +1221,6 @@ static struct clk_rcg2 gcc_sec_ctrl_clk_src = {
        },
 };
 
-static struct clk_regmap_div gcc_cpuss_ahb_postdiv_clk_src = {
-       .reg = 0x48024,
-       .shift = 0,
-       .width = 4,
-       .clkr.hw.init = &(struct clk_init_data) {
-               .name = "gcc_cpuss_ahb_postdiv_clk_src",
-               .parent_hws = (const struct clk_hw*[]){
-                       &gcc_cpuss_ahb_clk_src.clkr.hw,
-               },
-               .num_parents = 1,
-               .flags = CLK_SET_RATE_PARENT,
-               .ops = &clk_regmap_div_ro_ops,
-       },
-};
-
 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
        .reg = 0xf050,
        .shift = 0,
@@ -1500,27 +1467,6 @@ static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
        },
 };
 
-/* For CPUSS functionality the AHB clock needs to be left enabled */
-static struct clk_branch gcc_cpuss_ahb_clk = {
-       .halt_reg = 0x48000,
-       .halt_check = BRANCH_HALT_VOTED,
-       .hwcg_reg = 0x48000,
-       .hwcg_bit = 1,
-       .clkr = {
-               .enable_reg = 0x52000,
-               .enable_mask = BIT(21),
-               .hw.init = &(struct clk_init_data){
-                       .name = "gcc_cpuss_ahb_clk",
-                       .parent_hws = (const struct clk_hw*[]){
-                               &gcc_cpuss_ahb_postdiv_clk_src.clkr.hw,
-                       },
-                       .num_parents = 1,
-                       .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
-                       .ops = &clk_branch2_ops,
-               },
-       },
-};
-
 static struct clk_branch gcc_ddrss_gpu_axi_clk = {
        .halt_reg = 0x71154,
        .halt_check = BRANCH_HALT_SKIP,
@@ -2608,27 +2554,6 @@ static struct clk_branch gcc_sdcc4_apps_clk = {
        },
 };
 
-/* For CPUSS functionality the AHB clock needs to be left enabled */
-static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
-       .halt_reg = 0x48178,
-       .halt_check = BRANCH_HALT_VOTED,
-       .hwcg_reg = 0x48178,
-       .hwcg_bit = 1,
-       .clkr = {
-               .enable_reg = 0x52000,
-               .enable_mask = BIT(0),
-               .hw.init = &(struct clk_init_data){
-                       .name = "gcc_sys_noc_cpuss_ahb_clk",
-                       .parent_hws = (const struct clk_hw*[]){
-                               &gcc_cpuss_ahb_postdiv_clk_src.clkr.hw,
-                       },
-                       .num_parents = 1,
-                       .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
-                       .ops = &clk_branch2_ops,
-               },
-       },
-};
-
 static struct clk_branch gcc_throttle_pcie_ahb_clk = {
        .halt_reg = 0x9001c,
        .halt_check = BRANCH_HALT,
@@ -3294,9 +3219,6 @@ static struct clk_regmap *gcc_sc7280_clocks[] = {
        [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
        [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
        [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
-       [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
-       [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
-       [GCC_CPUSS_AHB_POSTDIV_CLK_SRC] = &gcc_cpuss_ahb_postdiv_clk_src.clkr,
        [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
        [GCC_DDRSS_PCIE_SF_CLK] = &gcc_ddrss_pcie_sf_clk.clkr,
        [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
@@ -3403,7 +3325,6 @@ static struct clk_regmap *gcc_sc7280_clocks[] = {
        [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
        [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
        [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
-       [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
        [GCC_THROTTLE_PCIE_AHB_CLK] = &gcc_throttle_pcie_ahb_clk.clkr,
        [GCC_TITAN_NRT_THROTTLE_CORE_CLK] =
                &gcc_titan_nrt_throttle_core_clk.clkr,