struct imx_mu_dcfg {
int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data);
int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
+ int (*rxdb)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
void (*init)(struct imx_mu_priv *priv);
enum imx_mu_type type;
u32 xTR; /* Transmit Register0 */
return 0;
}
+static int imx_mu_generic_rxdb(struct imx_mu_priv *priv,
+ struct imx_mu_con_priv *cp)
+{
+ imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx),
+ priv->dcfg->xSR[IMX_MU_GSR]);
+ mbox_chan_received_data(cp->chan, NULL);
+
+ return 0;
+}
+
static int imx_mu_specific_tx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data)
{
u32 *arg = data;
priv->dcfg->rx(priv, cp);
} else if ((val == IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx)) &&
(cp->type == IMX_MU_TYPE_RXDB)) {
- imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx),
- priv->dcfg->xSR[IMX_MU_GSR]);
- mbox_chan_received_data(chan, NULL);
+ priv->dcfg->rxdb(priv, cp);
} else {
dev_warn_ratelimited(priv->dev, "Not handled interrupt\n");
return IRQ_NONE;
static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = {
.tx = imx_mu_generic_tx,
.rx = imx_mu_generic_rx,
+ .rxdb = imx_mu_generic_rxdb,
.init = imx_mu_init_generic,
.xTR = 0x0,
.xRR = 0x10,
static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
.tx = imx_mu_generic_tx,
.rx = imx_mu_generic_rx,
+ .rxdb = imx_mu_generic_rxdb,
.init = imx_mu_init_generic,
.xTR = 0x20,
.xRR = 0x40,
static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp = {
.tx = imx_mu_generic_tx,
.rx = imx_mu_generic_rx,
+ .rxdb = imx_mu_generic_rxdb,
.init = imx_mu_init_generic,
+ .rxdb = imx_mu_generic_rxdb,
.type = IMX_MU_V2,
.xTR = 0x200,
.xRR = 0x280,
.tx = imx_mu_specific_tx,
.rx = imx_mu_specific_rx,
.init = imx_mu_init_specific,
+ .rxdb = imx_mu_generic_rxdb,
.xTR = 0x0,
.xRR = 0x10,
.xSR = {0x20, 0x20, 0x20, 0x20},