ASoC: SOF: Intel: hda: Define rom_status_reg in sof_intel_dsp_desc
authorRanjani Sridharan <ranjani.sridharan@linux.intel.com>
Thu, 14 Apr 2022 18:48:15 +0000 (13:48 -0500)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Thu, 25 Aug 2022 09:40:28 +0000 (11:40 +0200)
[ Upstream commit 71778f7940f0b496aa1ca1134f3b70b425a59bab ]

Add the rom_status_reg field to struct sof_intel_dsp_desc and define
it for HDA platforms. This will be used to check the ROM status during
FW boot.

Signed-off-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com>
Link: https://lore.kernel.org/r/20220414184817.362215-14-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
sound/soc/sof/intel/apl.c
sound/soc/sof/intel/cnl.c
sound/soc/sof/intel/hda-loader.c
sound/soc/sof/intel/hda.c
sound/soc/sof/intel/icl.c
sound/soc/sof/intel/shim.h
sound/soc/sof/intel/tgl.c

index c7ed2b3..0a42034 100644 (file)
@@ -139,6 +139,7 @@ const struct sof_intel_dsp_desc apl_chip_info = {
        .ipc_ack = HDA_DSP_REG_HIPCIE,
        .ipc_ack_mask = HDA_DSP_REG_HIPCIE_DONE,
        .ipc_ctl = HDA_DSP_REG_HIPCCTL,
+       .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
        .rom_init_timeout       = 150,
        .ssp_count = APL_SSP_COUNT,
        .ssp_base_offset = APL_SSP_BASE_OFFSET,
index e115e12..a63b235 100644 (file)
@@ -344,6 +344,7 @@ const struct sof_intel_dsp_desc cnl_chip_info = {
        .ipc_ack = CNL_DSP_REG_HIPCIDA,
        .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
        .ipc_ctl = CNL_DSP_REG_HIPCCTL,
+       .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
        .rom_init_timeout       = 300,
        .ssp_count = CNL_SSP_COUNT,
        .ssp_base_offset = CNL_SSP_BASE_OFFSET,
@@ -363,6 +364,7 @@ const struct sof_intel_dsp_desc jsl_chip_info = {
        .ipc_ack = CNL_DSP_REG_HIPCIDA,
        .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
        .ipc_ctl = CNL_DSP_REG_HIPCCTL,
+       .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
        .rom_init_timeout       = 300,
        .ssp_count = ICL_SSP_COUNT,
        .ssp_base_offset = CNL_SSP_BASE_OFFSET,
index ee09393..439cb33 100644 (file)
@@ -163,7 +163,7 @@ static int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag)
 
        /* step 7: wait for ROM init */
        ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
-                                       HDA_DSP_SRAM_REG_ROM_STATUS, status,
+                                       chip->rom_status_reg, status,
                                        ((status & HDA_DSP_ROM_STS_MASK)
                                                == HDA_DSP_ROM_INIT),
                                        HDA_DSP_REG_POLL_INTERVAL_US,
@@ -174,8 +174,8 @@ static int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag)
 
        if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
                dev_err(sdev->dev,
-                       "error: %s: timeout HDA_DSP_SRAM_REG_ROM_STATUS read\n",
-                       __func__);
+                       "%s: timeout with rom_status_reg (%#x) read\n",
+                       __func__, chip->rom_status_reg);
 
 err:
        flags = SOF_DBG_DUMP_REGS | SOF_DBG_DUMP_PCI | SOF_DBG_DUMP_MBOX;
@@ -251,6 +251,8 @@ static int cl_cleanup(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab,
 
 static int cl_copy_fw(struct snd_sof_dev *sdev, struct hdac_ext_stream *stream)
 {
+       struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
+       const struct sof_intel_dsp_desc *chip = hda->desc;
        unsigned int reg;
        int ret, status;
 
@@ -261,7 +263,7 @@ static int cl_copy_fw(struct snd_sof_dev *sdev, struct hdac_ext_stream *stream)
        }
 
        status = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
-                                       HDA_DSP_SRAM_REG_ROM_STATUS, reg,
+                                       chip->rom_status_reg, reg,
                                        ((reg & HDA_DSP_ROM_STS_MASK)
                                                == HDA_DSP_ROM_FW_ENTERED),
                                        HDA_DSP_REG_POLL_INTERVAL_US,
@@ -274,8 +276,8 @@ static int cl_copy_fw(struct snd_sof_dev *sdev, struct hdac_ext_stream *stream)
 
        if (status < 0) {
                dev_err(sdev->dev,
-                       "error: %s: timeout HDA_DSP_SRAM_REG_ROM_STATUS read\n",
-                       __func__);
+                       "%s: timeout with rom_status_reg (%#x) read\n",
+                       __func__, chip->rom_status_reg);
        }
 
        ret = cl_trigger(sdev, stream, SNDRV_PCM_TRIGGER_STOP);
index ddf7090..e733c40 100644 (file)
@@ -353,11 +353,13 @@ static const struct hda_dsp_msg_code hda_dsp_rom_msg[] = {
 
 static void hda_dsp_get_status(struct snd_sof_dev *sdev)
 {
+       const struct sof_intel_dsp_desc *chip;
        u32 status;
        int i;
 
+       chip = get_chip_info(sdev->pdata);
        status = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
-                                 HDA_DSP_SRAM_REG_ROM_STATUS);
+                                 chip->rom_status_reg);
 
        for (i = 0; i < ARRAY_SIZE(hda_dsp_rom_msg); i++) {
                if (status == hda_dsp_rom_msg[i].code) {
@@ -402,13 +404,15 @@ static void hda_dsp_get_registers(struct snd_sof_dev *sdev,
 /* dump the first 8 dwords representing the extended ROM status */
 static void hda_dsp_dump_ext_rom_status(struct snd_sof_dev *sdev, u32 flags)
 {
+       const struct sof_intel_dsp_desc *chip;
        char msg[128];
        int len = 0;
        u32 value;
        int i;
 
+       chip = get_chip_info(sdev->pdata);
        for (i = 0; i < HDA_EXT_ROM_STATUS_SIZE; i++) {
-               value = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_SRAM_REG_ROM_STATUS + i * 0x4);
+               value = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->rom_status_reg + i * 0x4);
                len += snprintf(msg + len, sizeof(msg) - len, " 0x%x", value);
        }
 
index ee095b8..4065c4d 100644 (file)
@@ -139,6 +139,7 @@ const struct sof_intel_dsp_desc icl_chip_info = {
        .ipc_ack = CNL_DSP_REG_HIPCIDA,
        .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
        .ipc_ctl = CNL_DSP_REG_HIPCCTL,
+       .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
        .rom_init_timeout       = 300,
        .ssp_count = ICL_SSP_COUNT,
        .ssp_base_offset = CNL_SSP_BASE_OFFSET,
index e9f7d4d..9670775 100644 (file)
@@ -161,6 +161,7 @@ struct sof_intel_dsp_desc {
        int ipc_ack;
        int ipc_ack_mask;
        int ipc_ctl;
+       int rom_status_reg;
        int rom_init_timeout;
        int ssp_count;                  /* ssp count of the platform */
        int ssp_base_offset;            /* base address of the SSPs */
index 199d41a..aba52d8 100644 (file)
@@ -134,6 +134,7 @@ const struct sof_intel_dsp_desc tgl_chip_info = {
        .ipc_ack = CNL_DSP_REG_HIPCIDA,
        .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
        .ipc_ctl = CNL_DSP_REG_HIPCCTL,
+       .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
        .rom_init_timeout       = 300,
        .ssp_count = ICL_SSP_COUNT,
        .ssp_base_offset = CNL_SSP_BASE_OFFSET,
@@ -153,6 +154,7 @@ const struct sof_intel_dsp_desc tglh_chip_info = {
        .ipc_ack = CNL_DSP_REG_HIPCIDA,
        .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
        .ipc_ctl = CNL_DSP_REG_HIPCCTL,
+       .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
        .rom_init_timeout       = 300,
        .ssp_count = ICL_SSP_COUNT,
        .ssp_base_offset = CNL_SSP_BASE_OFFSET,
@@ -172,6 +174,7 @@ const struct sof_intel_dsp_desc ehl_chip_info = {
        .ipc_ack = CNL_DSP_REG_HIPCIDA,
        .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
        .ipc_ctl = CNL_DSP_REG_HIPCCTL,
+       .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
        .rom_init_timeout       = 300,
        .ssp_count = ICL_SSP_COUNT,
        .ssp_base_offset = CNL_SSP_BASE_OFFSET,
@@ -191,6 +194,7 @@ const struct sof_intel_dsp_desc adls_chip_info = {
        .ipc_ack = CNL_DSP_REG_HIPCIDA,
        .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
        .ipc_ctl = CNL_DSP_REG_HIPCCTL,
+       .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
        .rom_init_timeout       = 300,
        .ssp_count = ICL_SSP_COUNT,
        .ssp_base_offset = CNL_SSP_BASE_OFFSET,