[X86] matchBinaryShuffle - relax PACKSS for v2i64 -> v4i32 shuffle truncation pattern...

Similar to combineVectorSignBitsTruncation, we don't require all-signbits source inputs, just enough signbits to reach into the lowest i16 to safely use PACKSSDW.

diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 0ba9041..2c65984 100644 (file)
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -39937,10 +39937,11 @@ static bool matchBinaryShuffle(MVT MaskVT, ArrayRef<int> Mask,
   }
   // TODO: Can we handle this inside matchShuffleWithPACK?
   if (MaskVT == MVT::v4i32 && Subtarget.hasSSE2() &&
-      isTargetShuffleEquivalent(MaskVT, Mask, {0, 2, 4, 6}, DAG)) {
-    if (V1.getScalarValueSizeInBits() == 64 &&
-        V2.getScalarValueSizeInBits() == 64 &&
-        DAG.ComputeNumSignBits(V1) == 64 && DAG.ComputeNumSignBits(V2) == 64) {
+      isTargetShuffleEquivalent(MaskVT, Mask, {0, 2, 4, 6}, DAG) &&
+      V1.getScalarValueSizeInBits() == 64 &&
+      V2.getScalarValueSizeInBits() == 64) {
+    // Use PACKSSWD if the signbits extend to the lowest 16-bits.
+    if (DAG.ComputeNumSignBits(V1) > 48 && DAG.ComputeNumSignBits(V2) > 48) {
       SrcVT = MVT::v4i32;
       DstVT = MVT::v8i16;
       Shuffle = X86ISD::PACKSS;

diff --git a/llvm/test/CodeGen/X86/concat-cast.ll b/llvm/test/CodeGen/X86/concat-cast.ll
index 8900752..ae61fa1 100644 (file)
--- a/llvm/test/CodeGen/X86/concat-cast.ll
+++ b/llvm/test/CodeGen/X86/concat-cast.ll
@@ -459,7 +459,7 @@ define <4 x float> @PR45794(<2 x i64> %x, <2 x i64> %y) {
 ; AVX512F-NEXT:    # kill: def $xmm0 killed $xmm0 def $zmm0
 ; AVX512F-NEXT:    vpsraq $48, %zmm0, %zmm0
 ; AVX512F-NEXT:    vpsraq $48, %zmm1, %zmm1
-; AVX512F-NEXT:    vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
+; AVX512F-NEXT:    vpackssdw %xmm1, %xmm0, %xmm0
 ; AVX512F-NEXT:    vcvtdq2ps %xmm0, %xmm0
 ; AVX512F-NEXT:    vzeroupper
 ; AVX512F-NEXT:    retq