[(set_attr "isa" "*,nox64")
(set_attr "type" "alu")
(set_attr "mode" "QI")])
+
+;; Split DST = (HI<<32)|LO early to minimize register usage.
+(define_code_iterator any_or_plus [plus ior xor])
+(define_split
+ [(set (match_operand:DI 0 "register_operand")
+ (any_or_plus:DI
+ (ashift:DI (match_operand:DI 1 "register_operand")
+ (const_int 32))
+ (zero_extend:DI (match_operand:SI 2 "register_operand"))))]
+ "!TARGET_64BIT"
+ [(set (match_dup 3) (match_dup 4))
+ (set (match_dup 5) (match_dup 2))]
+{
+ operands[3] = gen_highpart (SImode, operands[0]);
+ operands[4] = gen_lowpart (SImode, operands[1]);
+ operands[5] = gen_lowpart (SImode, operands[0]);
+})
+
+(define_split
+ [(set (match_operand:DI 0 "register_operand")
+ (any_or_plus:DI
+ (zero_extend:DI (match_operand:SI 1 "register_operand"))
+ (ashift:DI (match_operand:DI 2 "register_operand")
+ (const_int 32))))]
+ "!TARGET_64BIT"
+ [(set (match_dup 3) (match_dup 4))
+ (set (match_dup 5) (match_dup 1))]
+{
+ operands[3] = gen_highpart (SImode, operands[0]);
+ operands[4] = gen_lowpart (SImode, operands[2]);
+ operands[5] = gen_lowpart (SImode, operands[0]);
+})
\f
;; Negation instructions
(vec_select:SI
(match_operand:V4SI 1 "register_operand" "v,x,v")
(parallel [(const_int 0)]))))]
- "TARGET_SSE4_1"
+ "TARGET_64BIT && TARGET_SSE4_1"
"#"
- [(set_attr "isa" "x64,*,avx512f")
+ [(set_attr "isa" "*,*,avx512f")
(set (attr "preferred_for_speed")
(cond [(eq_attr "alternative" "0")
(symbol_ref "TARGET_INTER_UNIT_MOVES_FROM_VEC")
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-m32 -O2 -msse4" } */
+typedef int __v4si __attribute__ ((__vector_size__ (16)));
+
+long long test1(__v4si v) {
+ unsigned int loVal = (unsigned int)v[0];
+ unsigned int hiVal = (unsigned int)v[1];
+ return (long long)(loVal) | ((long long)(hiVal) << 32);
+}
+
+long long test2(__v4si v) {
+ unsigned int loVal = (unsigned int)v[2];
+ unsigned int hiVal = (unsigned int)v[3];
+ return (long long)(loVal) | ((long long)(hiVal) << 32);
+}
+
+long long test3(__v4si v) {
+ unsigned int loVal = (unsigned int)v[0];
+ unsigned int hiVal = (unsigned int)v[1];
+ return (long long)(loVal) ^ ((long long)(hiVal) << 32);
+}
+
+long long test4(__v4si v) {
+ unsigned int loVal = (unsigned int)v[2];
+ unsigned int hiVal = (unsigned int)v[3];
+ return (long long)(loVal) ^ ((long long)(hiVal) << 32);
+}
+
+long long test5(__v4si v) {
+ unsigned int loVal = (unsigned int)v[0];
+ unsigned int hiVal = (unsigned int)v[1];
+ return (long long)(loVal) + ((long long)(hiVal) << 32);
+}
+
+long long test6(__v4si v) {
+ unsigned int loVal = (unsigned int)v[2];
+ unsigned int hiVal = (unsigned int)v[3];
+ return (long long)(loVal) + ((long long)(hiVal) << 32);
+}
+
+/* { dg-final { scan-assembler-not "\tor" } } */
+/* { dg-final { scan-assembler-not "\txor" } } */
+/* { dg-final { scan-assembler-not "\tadd" } } */