Node->getOpcode() == ISD::MUL || Node->getOpcode() == ISD::SHL ||
Node->getOpcode() == ISD::SRL ||
Node->getOpcode() == ISD::SIGN_EXTEND_INREG ||
+ Node->getOpcode() == RISCVISD::GREV ||
+ Node->getOpcode() == RISCVISD::GORC ||
isa<ConstantSDNode>(Node)) &&
"Unexpected opcode");
case RISCV::SUBW:
case RISCV::MULW:
case RISCV::SLLIW:
+ case RISCV::GREVIW:
+ case RISCV::GORCIW:
// Result is already sign extended just remove the sext.w.
// NOTE: We only handle the nodes that are selected with hasAllWUsers.
ReplaceUses(N, N0.getNode());
// Select GREVIW/GORCIW when the immediate doesn't have bit 5 set and the result
// is sign extended.
-// FIXME: Use binop_allwusers and doPeepholeSExtW instead?
-def : Pat<(i64 (sext_inreg (binop_oneuse<riscv_grev> GPR:$rs1, uimm5:$imm), i32)),
- (GREVIW GPR:$rs1, uimm5:$imm)>;
-def : Pat<(i64 (sext_inreg (binop_oneuse<riscv_gorc> GPR:$rs1, uimm5:$imm), i32)),
- (GORCIW GPR:$rs1, uimm5:$imm)>;
+// FIXME: Two special patterns keeped when Imm is 7.
+def : Pat<(i64 (sext_inreg (binop_oneuse<riscv_grev> GPR:$rs1, 7), i32)),
+ (GREVIW GPR:$rs1, 7)>;
+def : Pat<(i64 (sext_inreg (binop_oneuse<riscv_gorc> GPR:$rs1, 7), i32)),
+ (GORCIW GPR:$rs1, 7)>;
+def : PatGprImm<binop_allwusers<riscv_grev>, GREVIW, uimm5>;
+def : PatGprImm<binop_allwusers<riscv_gorc>, GORCIW, uimm5>;
def : PatGprGpr<riscv_shflw, SHFLW>;
def : PatGprGpr<riscv_unshflw, UNSHFLW>;
;
; RV64ZBP-LABEL: bswap_i32_nosext:
; RV64ZBP: # %bb.0:
-; RV64ZBP-NEXT: rev8.w a0, a0
+; RV64ZBP-NEXT: greviw a0, a0, 24
; RV64ZBP-NEXT: sw a0, 0(a1)
; RV64ZBP-NEXT: ret
%1 = tail call i32 @llvm.bswap.i32(i32 %a)
;
; RV64ZBP-LABEL: bitreverse_i32_nosext:
; RV64ZBP: # %bb.0:
-; RV64ZBP-NEXT: rev.w a0, a0
+; RV64ZBP-NEXT: greviw a0, a0, 31
; RV64ZBP-NEXT: sw a0, 0(a1)
; RV64ZBP-NEXT: ret
%1 = tail call i32 @llvm.bitreverse.i32(i32 %a)