/// Recursive helper for combineVectorSizedSetCCEquality() to emit the memcmp
/// expansion.
template <typename F>
-static SDValue emitOrXorXorTree(SDValue X, SDLoc &DL, SelectionDAG &DAG,
+static SDValue emitOrXorXorTree(SDValue X, const SDLoc &DL, SelectionDAG &DAG,
EVT VecVT, EVT CmpVT, bool HasPT, F SToV) {
SDValue Op0 = X.getOperand(0);
SDValue Op1 = X.getOperand(1);
/// Try to map a 128-bit or larger integer comparison to vector instructions
/// before type legalization splits it up into chunks.
-static SDValue combineVectorSizedSetCCEquality(SDNode *SetCC, SelectionDAG &DAG,
+static SDValue combineVectorSizedSetCCEquality(EVT VT, SDValue X, SDValue Y,
+ ISD::CondCode CC,
+ const SDLoc &DL,
+ SelectionDAG &DAG,
const X86Subtarget &Subtarget) {
- ISD::CondCode CC = cast<CondCodeSDNode>(SetCC->getOperand(2))->get();
assert((CC == ISD::SETNE || CC == ISD::SETEQ) && "Bad comparison predicate");
// We're looking for an oversized integer equality comparison.
- SDValue X = SetCC->getOperand(0);
- SDValue Y = SetCC->getOperand(1);
EVT OpVT = X.getValueType();
unsigned OpSize = OpVT.getSizeInBits();
if (!OpVT.isScalarInteger() || OpSize < 128)
!IsOrXorXorTreeCCZero)
return SDValue();
- EVT VT = SetCC->getValueType(0);
- SDLoc DL(SetCC);
-
// Use XOR (plus OR) and PTEST after SSE4.1 for 128/256-bit operands.
// Use PCMPNEQ (plus OR) and KORTEST for 512-bit operands.
// Otherwise use PCMPEQ (plus AND) and mask testing.
SDLoc DL(N);
if (CC == ISD::SETNE || CC == ISD::SETEQ) {
- if (SDValue V = combineVectorSizedSetCCEquality(N, DAG, Subtarget))
+ if (SDValue V = combineVectorSizedSetCCEquality(VT, LHS, RHS, CC, DL, DAG,
+ Subtarget))
return V;
if (VT == MVT::i1 && isNullConstant(RHS)) {