r600: Alpha to coverage dithering on Evergreen+
authorVitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Sun, 9 Apr 2023 20:05:12 +0000 (23:05 +0300)
committerMarge Bot <emma+marge@anholt.net>
Thu, 13 Apr 2023 02:07:52 +0000 (02:07 +0000)
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22384>

docs/relnotes/new_features.txt
src/gallium/drivers/r600/evergreen_state.c
src/gallium/drivers/r600/r600_pipe.c

index 801a215..2a705e8 100644 (file)
@@ -9,3 +9,4 @@ primitiveUnderestimation on RADV/GFX9+
 VK_KHR_fragment_shading_rate on RADV/GFX11
 VK_EXT_mesh_shader on RADV/GFX11
 RGP support on RADV/GFX11
+GL_NV_alpha_to_coverage_dither_control on r600/evergreen+
index b8a2ae7..7a6b98a 100644 (file)
@@ -324,6 +324,7 @@ static void *evergreen_create_blend_state_mode(struct pipe_context *ctx,
                                               const struct pipe_blend_state *state, int mode)
 {
        uint32_t color_control = 0, target_mask = 0;
+       uint32_t alpha_to_mask = 0;
        struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
 
        if (!blend) {
@@ -359,14 +360,27 @@ static void *evergreen_create_blend_state_mode(struct pipe_context *ctx,
        else
                color_control |= S_028808_MODE(V_028808_CB_DISABLE);
 
-
        r600_store_context_reg(&blend->buffer, R_028808_CB_COLOR_CONTROL, color_control);
-       r600_store_context_reg(&blend->buffer, R_028B70_DB_ALPHA_TO_MASK,
-                              S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
-                              S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
-                              S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
-                              S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
-                              S_028B70_ALPHA_TO_MASK_OFFSET3(2));
+
+       if (state->alpha_to_coverage) {
+               if (state->alpha_to_coverage_dither) {
+                       alpha_to_mask = S_028B70_ALPHA_TO_MASK_ENABLE(1) |
+                                       S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
+                                       S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
+                                       S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
+                                       S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
+                                       S_028B70_OFFSET_ROUND(1);
+               } else {
+                       alpha_to_mask = S_028B70_ALPHA_TO_MASK_ENABLE(1) |
+                                       S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
+                                       S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
+                                       S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
+                                       S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
+                                       S_028B70_OFFSET_ROUND(0);
+               }
+       }
+       r600_store_context_reg(&blend->buffer, R_028B70_DB_ALPHA_TO_MASK, alpha_to_mask);
+
        r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
 
        /* Copy over the dwords set so far into buffer_no_blend.
index 4042324..a7ba6f7 100644 (file)
@@ -383,6 +383,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
        case PIPE_CAP_SHADER_ARRAY_COMPONENTS:
        case PIPE_CAP_QUERY_BUFFER_OBJECT:
        case PIPE_CAP_IMAGE_STORE_FORMATTED:
+       case PIPE_CAP_ALPHA_TO_COVERAGE_DITHER_CONTROL:
                return family >= CHIP_CEDAR ? 1 : 0;
        case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
                return family >= CHIP_CEDAR ? 4 : 0;