clk: qcom: gcc-msm8998: Add clkref clocks

Add clkref clocks for usb3, hdmi, ufs, pcie, and usb2. They are all
sourced off CXO_IN, so parent them off "xo" until a proper link to the
rpmcc can be described in DT.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c
index c1819ef..5f989ee 100644 (file)
--- a/drivers/clk/qcom/gcc-msm8998.c
+++ b/drivers/clk/qcom/gcc-msm8998.c
@@ -2526,6 +2526,76 @@ static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
        },
 };
 
+static struct clk_branch gcc_hdmi_clkref_clk = {
+       .halt_reg = 0x88000,
+       .clkr = {
+               .enable_reg = 0x88000,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_hdmi_clkref_clk",
+                       .parent_names = (const char *[]){ "xo" },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_ufs_clkref_clk = {
+       .halt_reg = 0x88004,
+       .clkr = {
+               .enable_reg = 0x88004,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_ufs_clkref_clk",
+                       .parent_names = (const char *[]){ "xo" },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_usb3_clkref_clk = {
+       .halt_reg = 0x88008,
+       .clkr = {
+               .enable_reg = 0x88008,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_usb3_clkref_clk",
+                       .parent_names = (const char *[]){ "xo" },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_pcie_clkref_clk = {
+       .halt_reg = 0x8800c,
+       .clkr = {
+               .enable_reg = 0x8800c,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_pcie_clkref_clk",
+                       .parent_names = (const char *[]){ "xo" },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_rx1_usb2_clkref_clk = {
+       .halt_reg = 0x88014,
+       .clkr = {
+               .enable_reg = 0x88014,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_rx1_usb2_clkref_clk",
+                       .parent_names = (const char *[]){ "xo" },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
 static struct gdsc pcie_0_gdsc = {
        .gdscr = 0x6b004,
        .gds_hw_ctrl = 0x0,
@@ -2716,6 +2786,11 @@ static struct clk_regmap *gcc_msm8998_clocks[] = {
        [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
        [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
        [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
+       [GCC_HDMI_CLKREF_CLK] = &gcc_hdmi_clkref_clk.clkr,
+       [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,
+       [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr,
+       [GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr,
+       [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,
 };
 
 static struct gdsc *gcc_msm8998_gdscs[] = {

diff --git a/include/dt-bindings/clock/qcom,gcc-msm8998.h b/include/dt-bindings/clock/qcom,gcc-msm8998.h
index c751a40..958fe83 100644 (file)
--- a/include/dt-bindings/clock/qcom,gcc-msm8998.h
+++ b/include/dt-bindings/clock/qcom,gcc-msm8998.h
@@ -180,6 +180,11 @@
 #define USB30_MASTER_CLK_SRC                                   163
 #define USB30_MOCK_UTMI_CLK_SRC                                        164
 #define USB3_PHY_AUX_CLK_SRC                                   165
+#define GCC_USB3_CLKREF_CLK                                    166
+#define GCC_HDMI_CLKREF_CLK                                    167
+#define GCC_UFS_CLKREF_CLK                                     168
+#define GCC_PCIE_CLKREF_CLK                                    169
+#define GCC_RX1_USB2_CLKREF_CLK                                        170
 
 #define PCIE_0_GDSC                                            0
 #define UFS_GDSC                                               1