Merge tag 'soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull arm-soc: soc specific changes (part 2) from Olof Johansson:
 "This adds support for the spear13xx platform, which has first been
  under review a long time ago and finally been completed after generic
  spear work has gone into the clock, dt and pinctrl branches.

  Also a number of updates for the samsung socs are part of this branch."

Fix up trivial conflicts in drivers/gpio/gpio-samsung.c that look much
worse than they are: the exonys5 init code was refactored in commit
fd454997d687 ("gpio: samsung: refactor gpiolib init for exynos4/5"), and
then commit f10590c9836c ("ARM: EXYNOS: add GPC4 bank instance") added a
new gpio chip define and did tiny updates to the init code.

So the conflict diff looks like hell, but it's actually a fairly simple
change.

* tag 'soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (34 commits)
  ARM: exynos: fix building with CONFIG_OF disabled
  ARM: EXYNOS: Add AUXDATA for i2c controllers
  ARM: dts: Update device tree source files for EXYNOS5250
  ARM: EXYNOS: Add device tree support for interrupt combiner
  ARM: EXYNOS: Add irq_domain support for interrupt combiner
  ARM: EXYNOS: Remove a new bus_type instance for EXYNOS5
  ARM: EXYNOS: update irqs for EXYNOS5250 SoC
  ARM: EXYNOS: Add pre-divider and fout mux clocks for bpll and mpll
  ARM: EXYNOS: add GPC4 bank instance
  ARM: EXYNOS: Redefine IRQ_MCT_L0,1 definition
  ARM: EXYNOS: Modify the GIC physical address for static io-mapping
  ARM: EXYNOS: Add watchdog timer clock instance
  pinctrl: SPEAr1310: Fix pin numbers for clcd_high_res
  SPEAr: Update MAINTAINERS and Documentation
  SPEAr13xx: Add defconfig
  SPEAr13xx: Add compilation support
  SPEAr13xx: Add dts and dtsi files
  pinctrl: Add SPEAr13xx pinctrl drivers
  pinctrl: SPEAr: Create macro for declaring GPIO PINS
  SPEAr13xx: Add common clock framework support
  ...

diff --cc MAINTAINERS
Simple merge

diff --cc arch/arm/Makefile
Simple merge

diff --cc arch/arm/mach-exynos/Kconfig
Simple merge

diff --cc arch/arm/mach-exynos/include/mach/irqs.h
Simple merge

diff --cc arch/arm/mach-exynos/include/mach/map.h
Simple merge

diff --cc arch/arm/mach-exynos/include/mach/regs-pmu.h
Simple merge

diff --cc arch/arm/mach-s3c24xx/Makefile
Simple merge

diff --cc drivers/gpio/gpio-samsung.c
index 421f6af,f88bb9f..7bb0044
--- 1/drivers/gpio/gpio-samsung.c
--- 2/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@@ -2716,219 -2722,6 +2722,222 @@@ static __init void exynos_gpiolib_attac
  }
  #endif /* defined(CONFIG_ARCH_EXYNOS) && defined(CONFIG_OF) */
  
-       chip = &exynos5_gpios_1[20];
 +static __init void exynos4_gpiolib_init(void)
 +{
 +#ifdef CONFIG_CPU_EXYNOS4210
 +      struct samsung_gpio_chip *chip;
 +      int i, nr_chips;
 +      void __iomem *gpio_base1, *gpio_base2, *gpio_base3;
 +      int group = 0;
 +      void __iomem *gpx_base;
 +
 +      /* gpio part1 */
 +      gpio_base1 = ioremap(EXYNOS4_PA_GPIO1, SZ_4K);
 +      if (gpio_base1 == NULL) {
 +              pr_err("unable to ioremap for gpio_base1\n");
 +              goto err_ioremap1;
 +      }
 +
 +      chip = exynos4_gpios_1;
 +      nr_chips = ARRAY_SIZE(exynos4_gpios_1);
 +
 +      for (i = 0; i < nr_chips; i++, chip++) {
 +              if (!chip->config) {
 +                      chip->config = &exynos_gpio_cfg;
 +                      chip->group = group++;
 +              }
 +              exynos_gpiolib_attach_ofnode(chip,
 +                              EXYNOS4_PA_GPIO1, i * 0x20);
 +      }
 +      samsung_gpiolib_add_4bit_chips(exynos4_gpios_1,
 +                                     nr_chips, gpio_base1);
 +
 +      /* gpio part2 */
 +      gpio_base2 = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
 +      if (gpio_base2 == NULL) {
 +              pr_err("unable to ioremap for gpio_base2\n");
 +              goto err_ioremap2;
 +      }
 +
 +      /* need to set base address for gpx */
 +      chip = &exynos4_gpios_2[16];
 +      gpx_base = gpio_base2 + 0xC00;
 +      for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
 +              chip->base = gpx_base;
 +
 +      chip = exynos4_gpios_2;
 +      nr_chips = ARRAY_SIZE(exynos4_gpios_2);
 +
 +      for (i = 0; i < nr_chips; i++, chip++) {
 +              if (!chip->config) {
 +                      chip->config = &exynos_gpio_cfg;
 +                      chip->group = group++;
 +              }
 +              exynos_gpiolib_attach_ofnode(chip,
 +                              EXYNOS4_PA_GPIO2, i * 0x20);
 +      }
 +      samsung_gpiolib_add_4bit_chips(exynos4_gpios_2,
 +                                     nr_chips, gpio_base2);
 +
 +      /* gpio part3 */
 +      gpio_base3 = ioremap(EXYNOS4_PA_GPIO3, SZ_256);
 +      if (gpio_base3 == NULL) {
 +              pr_err("unable to ioremap for gpio_base3\n");
 +              goto err_ioremap3;
 +      }
 +
 +      chip = exynos4_gpios_3;
 +      nr_chips = ARRAY_SIZE(exynos4_gpios_3);
 +
 +      for (i = 0; i < nr_chips; i++, chip++) {
 +              if (!chip->config) {
 +                      chip->config = &exynos_gpio_cfg;
 +                      chip->group = group++;
 +              }
 +              exynos_gpiolib_attach_ofnode(chip,
 +                              EXYNOS4_PA_GPIO3, i * 0x20);
 +      }
 +      samsung_gpiolib_add_4bit_chips(exynos4_gpios_3,
 +                                     nr_chips, gpio_base3);
 +
 +#if defined(CONFIG_CPU_EXYNOS4210) && defined(CONFIG_S5P_GPIO_INT)
 +      s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS);
 +      s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS);
 +#endif
 +
 +      return;
 +
 +err_ioremap3:
 +      iounmap(gpio_base2);
 +err_ioremap2:
 +      iounmap(gpio_base1);
 +err_ioremap1:
 +      return;
 +#endif        /* CONFIG_CPU_EXYNOS4210 */
 +}
 +
 +static __init void exynos5_gpiolib_init(void)
 +{
 +#ifdef CONFIG_SOC_EXYNOS5250
 +      struct samsung_gpio_chip *chip;
 +      int i, nr_chips;
 +      void __iomem *gpio_base1, *gpio_base2, *gpio_base3, *gpio_base4;
 +      int group = 0;
 +      void __iomem *gpx_base;
 +
 +      /* gpio part1 */
 +      gpio_base1 = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
 +      if (gpio_base1 == NULL) {
 +              pr_err("unable to ioremap for gpio_base1\n");
 +              goto err_ioremap1;
 +      }
 +
++      /* need to set base address for gpc4 */
++      exonys5_gpios_1[11].base = gpio_base1 + 0x2E0;
++
 +      /* need to set base address for gpx */
++      chip = &exynos5_gpios_1[21];
 +      gpx_base = gpio_base1 + 0xC00;
 +      for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
 +              chip->base = gpx_base;
 +
 +      chip = exynos5_gpios_1;
 +      nr_chips = ARRAY_SIZE(exynos5_gpios_1);
 +
 +      for (i = 0; i < nr_chips; i++, chip++) {
 +              if (!chip->config) {
 +                      chip->config = &exynos_gpio_cfg;
 +                      chip->group = group++;
 +              }
 +              exynos_gpiolib_attach_ofnode(chip,
 +                              EXYNOS5_PA_GPIO1, i * 0x20);
 +      }
 +      samsung_gpiolib_add_4bit_chips(exynos5_gpios_1,
 +                                     nr_chips, gpio_base1);
 +
 +      /* gpio part2 */
 +      gpio_base2 = ioremap(EXYNOS5_PA_GPIO2, SZ_4K);
 +      if (gpio_base2 == NULL) {
 +              pr_err("unable to ioremap for gpio_base2\n");
 +              goto err_ioremap2;
 +      }
 +
 +      chip = exynos5_gpios_2;
 +      nr_chips = ARRAY_SIZE(exynos5_gpios_2);
 +
 +      for (i = 0; i < nr_chips; i++, chip++) {
 +              if (!chip->config) {
 +                      chip->config = &exynos_gpio_cfg;
 +                      chip->group = group++;
 +              }
 +              exynos_gpiolib_attach_ofnode(chip,
 +                              EXYNOS5_PA_GPIO2, i * 0x20);
 +      }
 +      samsung_gpiolib_add_4bit_chips(exynos5_gpios_2,
 +                                     nr_chips, gpio_base2);
 +
 +      /* gpio part3 */
 +      gpio_base3 = ioremap(EXYNOS5_PA_GPIO3, SZ_4K);
 +      if (gpio_base3 == NULL) {
 +              pr_err("unable to ioremap for gpio_base3\n");
 +              goto err_ioremap3;
 +      }
 +
 +      /* need to set base address for gpv */
 +      exynos5_gpios_3[0].base = gpio_base3;
 +      exynos5_gpios_3[1].base = gpio_base3 + 0x20;
 +      exynos5_gpios_3[2].base = gpio_base3 + 0x60;
 +      exynos5_gpios_3[3].base = gpio_base3 + 0x80;
 +      exynos5_gpios_3[4].base = gpio_base3 + 0xC0;
 +
 +      chip = exynos5_gpios_3;
 +      nr_chips = ARRAY_SIZE(exynos5_gpios_3);
 +
 +      for (i = 0; i < nr_chips; i++, chip++) {
 +              if (!chip->config) {
 +                      chip->config = &exynos_gpio_cfg;
 +                      chip->group = group++;
 +              }
 +              exynos_gpiolib_attach_ofnode(chip,
 +                              EXYNOS5_PA_GPIO3, i * 0x20);
 +      }
 +      samsung_gpiolib_add_4bit_chips(exynos5_gpios_3,
 +                                     nr_chips, gpio_base3);
 +
 +      /* gpio part4 */
 +      gpio_base4 = ioremap(EXYNOS5_PA_GPIO4, SZ_4K);
 +      if (gpio_base4 == NULL) {
 +              pr_err("unable to ioremap for gpio_base4\n");
 +              goto err_ioremap4;
 +      }
 +
 +      chip = exynos5_gpios_4;
 +      nr_chips = ARRAY_SIZE(exynos5_gpios_4);
 +
 +      for (i = 0; i < nr_chips; i++, chip++) {
 +              if (!chip->config) {
 +                      chip->config = &exynos_gpio_cfg;
 +                      chip->group = group++;
 +              }
 +              exynos_gpiolib_attach_ofnode(chip,
 +                              EXYNOS5_PA_GPIO4, i * 0x20);
 +      }
 +      samsung_gpiolib_add_4bit_chips(exynos5_gpios_4,
 +                                     nr_chips, gpio_base4);
 +      return;
 +
 +err_ioremap4:
 +      iounmap(gpio_base3);
 +err_ioremap3:
 +      iounmap(gpio_base2);
 +err_ioremap2:
 +      iounmap(gpio_base1);
 +err_ioremap1:
 +      return;
 +
 +#endif        /* CONFIG_SOC_EXYNOS5250 */
 +}
 +
  /* TODO: cleanup soc_is_* */
  static __init int samsung_gpiolib_init(void)
  {