drm/amd/pm: enable TEMP_DEPENDENT_VMIN for navi1x
authorAlex Deucher <alexander.deucher@amd.com>
Tue, 28 Feb 2023 19:41:30 +0000 (14:41 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 22 Mar 2023 05:07:04 +0000 (01:07 -0400)
May help stability with some navi1x boards.

Hopefully this helps with stability with multiple monitors
and would allow us to re-enable MPC_SPLIT_DYNAMIC in the
DC code for better power savings.

Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2196
Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

index 95da6dd..c400051 100644 (file)
@@ -304,7 +304,8 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
                                | FEATURE_MASK(FEATURE_GFX_SS_BIT)
                                | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
                                | FEATURE_MASK(FEATURE_FW_CTF_BIT)
-                               | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
+                               | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT)
+                               | FEATURE_MASK(FEATURE_TEMP_DEPENDENT_VMIN_BIT);
 
        if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
                *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);