ARM: 8861/1: errata: Workaround errata A12 857271 / A17 857272

This adds support for working around errata A12 857271 / A17 857272.
These errata were causing hangs on rk3288-based Chromebooks and it was
confirmed that this workaround fixed the problems.  In the Chrome OS
3.14 kernel this was treated as two errata: ERRATA_FOOBAR [1] and
ERRATA_CR711784 [2].  Apparently the two errata got lumped together at
some point in time.

Let's actually get the workaround landed.

[1] https://crrev.com/c/342753
[2] https://crbug.com/711784

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Sonny Rao <sonnyrao@chromium.org>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 8869742..96377e3 100644 (file)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1175,6 +1175,14 @@ config ARM_ERRATA_825619
          DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
          and Device/Strongly-Ordered loads and stores might cause deadlock
 
+config ARM_ERRATA_857271
+       bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
+       depends on CPU_V7
+       help
+         This option enables the workaround for the 857271 Cortex-A12
+         (all revs) erratum. Under very rare timing conditions, the CPU might
+         hang. The workaround is expected to have a < 1% performance impact.
+
 config ARM_ERRATA_852421
        bool "ARM errata: A17: DMB ST might fail to create order between stores"
        depends on CPU_V7
@@ -1196,6 +1204,16 @@ config ARM_ERRATA_852423
          config option from the A12 erratum due to the way errata are checked
          for and handled.
 
+config ARM_ERRATA_857272
+       bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"
+       depends on CPU_V7
+       help
+         This option enables the workaround for the 857272 Cortex-A17 erratum.
+         This erratum is not known to be fixed in any A17 revision.
+         This is identical to Cortex-A12 erratum 857271.  It is a separate
+         config option from the A12 erratum due to the way errata are checked
+         for and handled.
+
 endmenu
 
 source "arch/arm/common/Kconfig"

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 339eb17..2966086 100644 (file)
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -392,6 +392,11 @@ __ca12_errata:
        orr     r10, r10, #1 << 24              @ set bit #24
        mcr     p15, 0, r10, c15, c0, 1         @ write diagnostic register
 #endif
+#ifdef CONFIG_ARM_ERRATA_857271
+       mrc     p15, 0, r10, c15, c0, 1         @ read diagnostic register
+       orr     r10, r10, #3 << 10              @ set bits #10 and #11
+       mcr     p15, 0, r10, c15, c0, 1         @ write diagnostic register
+#endif
        b       __errata_finish
 
 __ca17_errata:
@@ -407,6 +412,11 @@ __ca17_errata:
        orrle   r10, r10, #1 << 12              @ set bit #12
        mcrle   p15, 0, r10, c15, c0, 1         @ write diagnostic register
 #endif
+#ifdef CONFIG_ARM_ERRATA_857272
+       mrc     p15, 0, r10, c15, c0, 1         @ read diagnostic register
+       orr     r10, r10, #3 << 10              @ set bits #10 and #11
+       mcr     p15, 0, r10, c15, c0, 1         @ write diagnostic register
+#endif
        b       __errata_finish
 
 __v7_pj4b_setup: