crypto: ccree - add HW engine config check

Add check to verify the stated device tree HW configuration
matches the HW.

Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

diff --git a/drivers/crypto/ccree/cc_driver.c b/drivers/crypto/ccree/cc_driver.c
index 667bc73..980aa04 100644 (file)
--- a/drivers/crypto/ccree/cc_driver.c
+++ b/drivers/crypto/ccree/cc_driver.c
@@ -408,6 +408,24 @@ static int init_cc_resources(struct platform_device *plat_dev)
                }
                sig_cidr = val;
 
+               /* Check HW engine configuration */
+               val = cc_ioread(new_drvdata, CC_REG(HOST_REMOVE_INPUT_PINS));
+               switch (val) {
+               case CC_PINS_FULL:
+                       /* This is fine */
+                       break;
+               case CC_PINS_SLIM:
+                       if (new_drvdata->std_bodies & CC_STD_NIST) {
+                               dev_warn(dev, "703 mode forced due to HW configuration.\n");
+                               new_drvdata->std_bodies = CC_STD_OSCCA;
+                       }
+                       break;
+               default:
+                       dev_err(dev, "Unsupported engines configration.\n");
+                       rc = -EINVAL;
+                       goto post_clk_err;
+               }
+
                /* Check security disable state */
                val = cc_ioread(new_drvdata, CC_REG(SECURITY_DISABLED));
                val &= CC_SECURITY_DISABLED_MASK;

diff --git a/drivers/crypto/ccree/cc_driver.h b/drivers/crypto/ccree/cc_driver.h
index 579eeca..7cd9938 100644 (file)
--- a/drivers/crypto/ccree/cc_driver.h
+++ b/drivers/crypto/ccree/cc_driver.h
@@ -53,6 +53,9 @@ enum cc_std_body {
 
 #define CC_COHERENT_CACHE_PARAMS 0xEEE
 
+#define CC_PINS_FULL   0x0
+#define CC_PINS_SLIM   0x9F
+
 /* Maximum DMA mask supported by IP */
 #define DMA_BIT_MASK_LEN 48
 

diff --git a/drivers/crypto/ccree/cc_host_regs.h b/drivers/crypto/ccree/cc_host_regs.h
index ad1acb1..efe3e1d 100644 (file)
--- a/drivers/crypto/ccree/cc_host_regs.h
+++ b/drivers/crypto/ccree/cc_host_regs.h
@@ -206,6 +206,23 @@
 #define CC_HOST_POWER_DOWN_EN_REG_OFFSET       0xA78UL
 #define CC_HOST_POWER_DOWN_EN_VALUE_BIT_SHIFT  0x0UL
 #define CC_HOST_POWER_DOWN_EN_VALUE_BIT_SIZE   0x1UL
+#define CC_HOST_REMOVE_INPUT_PINS_REG_OFFSET   0x0A7CUL
+#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_AES_ENGINE_BIT_SHIFT  0x0UL
+#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_AES_ENGINE_BIT_SIZE   0x1UL
+#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_AES_MAC_ENGINE_BIT_SHIFT      0x1UL
+#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_AES_MAC_ENGINE_BIT_SIZE       0x1UL
+#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_GHASH_ENGINE_BIT_SHIFT        0x2UL
+#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_GHASH_ENGINE_BIT_SIZE 0x1UL
+#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_DES_ENGINE_BIT_SHIFT  0x3UL
+#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_DES_ENGINE_BIT_SIZE   0x1UL
+#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_HASH_ENGINE_BIT_SHIFT 0x4UL
+#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_HASH_ENGINE_BIT_SIZE  0x1UL
+#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_SM3_ENGINE_BIT_SHIFT  0x5UL
+#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_SM3_ENGINE_BIT_SIZE   0x1UL
+#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_SM4_ENGINE_BIT_SHIFT  0x6UL
+#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_SM4_ENGINE_BIT_SIZE   0x1UL
+#define CC_HOST_REMOVE_INPUT_PINS_OTP_DISCONNECTED_BIT_SHIFT   0x7UL
+#define CC_HOST_REMOVE_INPUT_PINS_OTP_DISCONNECTED_BIT_SIZE    0x1UL
 // --------------------------------------
 // BLOCK: ID_REGISTERS
 // --------------------------------------