stmmac: intel: Drop duplicate ID in the list of PCI device IDs

The PCI device IDs are defined with a prefix PCI_DEVICE_ID.
There is no need to repeat the ID part at the end of each definition.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Wong Vee Khee <vee.khee.wong@linux.intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
index add95e2..8ba87c0 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
@@ -1048,41 +1048,41 @@ static int __maybe_unused intel_eth_pci_resume(struct device *dev)
 static SIMPLE_DEV_PM_OPS(intel_eth_pm_ops, intel_eth_pci_suspend,
                         intel_eth_pci_resume);
 
-#define PCI_DEVICE_ID_INTEL_QUARK_ID                   0x0937
-#define PCI_DEVICE_ID_INTEL_EHL_RGMII1G_ID             0x4b30
-#define PCI_DEVICE_ID_INTEL_EHL_SGMII1G_ID             0x4b31
-#define PCI_DEVICE_ID_INTEL_EHL_SGMII2G5_ID            0x4b32
+#define PCI_DEVICE_ID_INTEL_QUARK              0x0937
+#define PCI_DEVICE_ID_INTEL_EHL_RGMII1G                0x4b30
+#define PCI_DEVICE_ID_INTEL_EHL_SGMII1G                0x4b31
+#define PCI_DEVICE_ID_INTEL_EHL_SGMII2G5       0x4b32
 /* Intel(R) Programmable Services Engine (Intel(R) PSE) consist of 2 MAC
  * which are named PSE0 and PSE1
  */
-#define PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G_ID                0x4ba0
-#define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G_ID                0x4ba1
-#define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5_ID       0x4ba2
-#define PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G_ID                0x4bb0
-#define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G_ID                0x4bb1
-#define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5_ID       0x4bb2
-#define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_0_ID          0x43ac
-#define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_1_ID          0x43a2
-#define PCI_DEVICE_ID_INTEL_TGL_SGMII1G_ID             0xa0ac
-#define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_0_ID          0x7aac
-#define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_1_ID          0x7aad
+#define PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G   0x4ba0
+#define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G   0x4ba1
+#define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5  0x4ba2
+#define PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G   0x4bb0
+#define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G   0x4bb1
+#define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5  0x4bb2
+#define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_0     0x43ac
+#define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_1     0x43a2
+#define PCI_DEVICE_ID_INTEL_TGL_SGMII1G                0xa0ac
+#define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_0     0x7aac
+#define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_1     0x7aad
 
 static const struct pci_device_id intel_eth_pci_id_table[] = {
-       { PCI_DEVICE_DATA(INTEL, QUARK_ID, &quark_info) },
-       { PCI_DEVICE_DATA(INTEL, EHL_RGMII1G_ID, &ehl_rgmii1g_info) },
-       { PCI_DEVICE_DATA(INTEL, EHL_SGMII1G_ID, &ehl_sgmii1g_info) },
-       { PCI_DEVICE_DATA(INTEL, EHL_SGMII2G5_ID, &ehl_sgmii1g_info) },
-       { PCI_DEVICE_DATA(INTEL, EHL_PSE0_RGMII1G_ID, &ehl_pse0_rgmii1g_info) },
-       { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII1G_ID, &ehl_pse0_sgmii1g_info) },
-       { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII2G5_ID, &ehl_pse0_sgmii1g_info) },
-       { PCI_DEVICE_DATA(INTEL, EHL_PSE1_RGMII1G_ID, &ehl_pse1_rgmii1g_info) },
-       { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII1G_ID, &ehl_pse1_sgmii1g_info) },
-       { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII2G5_ID, &ehl_pse1_sgmii1g_info) },
-       { PCI_DEVICE_DATA(INTEL, TGL_SGMII1G_ID, &tgl_sgmii1g_phy0_info) },
-       { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_0_ID, &tgl_sgmii1g_phy0_info) },
-       { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_1_ID, &tgl_sgmii1g_phy1_info) },
-       { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_0_ID, &adls_sgmii1g_phy0_info) },
-       { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_1_ID, &adls_sgmii1g_phy1_info) },
+       { PCI_DEVICE_DATA(INTEL, QUARK, &quark_info) },
+       { PCI_DEVICE_DATA(INTEL, EHL_RGMII1G, &ehl_rgmii1g_info) },
+       { PCI_DEVICE_DATA(INTEL, EHL_SGMII1G, &ehl_sgmii1g_info) },
+       { PCI_DEVICE_DATA(INTEL, EHL_SGMII2G5, &ehl_sgmii1g_info) },
+       { PCI_DEVICE_DATA(INTEL, EHL_PSE0_RGMII1G, &ehl_pse0_rgmii1g_info) },
+       { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII1G, &ehl_pse0_sgmii1g_info) },
+       { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII2G5, &ehl_pse0_sgmii1g_info) },
+       { PCI_DEVICE_DATA(INTEL, EHL_PSE1_RGMII1G, &ehl_pse1_rgmii1g_info) },
+       { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII1G, &ehl_pse1_sgmii1g_info) },
+       { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII2G5, &ehl_pse1_sgmii1g_info) },
+       { PCI_DEVICE_DATA(INTEL, TGL_SGMII1G, &tgl_sgmii1g_phy0_info) },
+       { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_0, &tgl_sgmii1g_phy0_info) },
+       { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_1, &tgl_sgmii1g_phy1_info) },
+       { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_0, &adls_sgmii1g_phy0_info) },
+       { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_1, &adls_sgmii1g_phy1_info) },
        {}
 };
 MODULE_DEVICE_TABLE(pci, intel_eth_pci_id_table);