drm/amdgpu: drop support for per ASIC read registers

Only per family registers are still used.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 68ce1e8..83ef798 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -280,10 +280,6 @@ static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
        return true;
 }
 
-static struct amdgpu_allowed_register_entry vega10_allowed_read_registers[] = {
-       /* todo */
-};
-
 static struct amdgpu_allowed_register_entry soc15_allowed_read_registers[] = {
        { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS)},
        { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS2)},
@@ -341,32 +337,9 @@ static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
                            u32 sh_num, u32 reg_offset, u32 *value)
 {
-       struct amdgpu_allowed_register_entry *asic_register_table = NULL;
-       struct amdgpu_allowed_register_entry *asic_register_entry;
-       uint32_t size, i;
+       uint32_t i;
 
        *value = 0;
-       switch (adev->asic_type) {
-       case CHIP_VEGA10:
-               asic_register_table = vega10_allowed_read_registers;
-               size = ARRAY_SIZE(vega10_allowed_read_registers);
-               break;
-       default:
-               return -EINVAL;
-       }
-
-       if (asic_register_table) {
-               for (i = 0; i < size; i++) {
-                       asic_register_entry = asic_register_table + i;
-                       if (reg_offset != asic_register_entry->reg_offset)
-                               continue;
-                       *value = soc15_get_register_value(adev,
-                                                         asic_register_entry->grbm_indexed,
-                                                         se_num, sh_num, reg_offset);
-                       return 0;
-               }
-       }
-
        for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
                if (reg_offset != soc15_allowed_read_registers[i].reg_offset)
                        continue;

diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 0decc44..5a275bc 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -463,12 +463,6 @@ static void vi_detect_hw_virtualization(struct amdgpu_device *adev)
        }
 }
 
-static const struct amdgpu_allowed_register_entry tonga_allowed_read_registers[] = {
-};
-
-static const struct amdgpu_allowed_register_entry cz_allowed_read_registers[] = {
-};
-
 static const struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = {
        {mmGRBM_STATUS},
        {mmGRBM_STATUS2},
@@ -647,43 +641,9 @@ static uint32_t vi_get_register_value(struct amdgpu_device *adev,
 static int vi_read_register(struct amdgpu_device *adev, u32 se_num,
                            u32 sh_num, u32 reg_offset, u32 *value)
 {
-       const struct amdgpu_allowed_register_entry *asic_register_table = NULL;
-       const struct amdgpu_allowed_register_entry *asic_register_entry;
-       uint32_t size, i;
+       uint32_t i;
 
        *value = 0;
-       switch (adev->asic_type) {
-       case CHIP_TOPAZ:
-               asic_register_table = tonga_allowed_read_registers;
-               size = ARRAY_SIZE(tonga_allowed_read_registers);
-               break;
-       case CHIP_FIJI:
-       case CHIP_TONGA:
-       case CHIP_POLARIS11:
-       case CHIP_POLARIS10:
-       case CHIP_POLARIS12:
-       case CHIP_CARRIZO:
-       case CHIP_STONEY:
-               asic_register_table = cz_allowed_read_registers;
-               size = ARRAY_SIZE(cz_allowed_read_registers);
-               break;
-       default:
-               return -EINVAL;
-       }
-
-       if (asic_register_table) {
-               for (i = 0; i < size; i++) {
-                       bool indexed = asic_register_entry->grbm_indexed;
-
-                       asic_register_entry = asic_register_table + i;
-                       if (reg_offset != asic_register_entry->reg_offset)
-                               continue;
-                       *value = vi_get_register_value(adev, indexed, se_num,
-                                                      sh_num, reg_offset);
-                       return 0;
-               }
-       }
-
        for (i = 0; i < ARRAY_SIZE(vi_allowed_read_registers); i++) {
                bool indexed = vi_allowed_read_registers[i].grbm_indexed;