Blackfin arch: Finalize the generic gpio support - add gpio_to_irq and irq_to_gpio
authorMichael Hennerich <michael.hennerich@analog.com>
Tue, 24 Jul 2007 07:35:53 +0000 (15:35 +0800)
committerBryan Wu <bryan.wu@analog.com>
Tue, 24 Jul 2007 07:35:53 +0000 (15:35 +0800)
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
include/asm-blackfin/gpio.h
include/asm-blackfin/mach-bf533/irq.h
include/asm-blackfin/mach-bf537/irq.h
include/asm-blackfin/mach-bf548/irq.h
include/asm-blackfin/mach-bf561/irq.h

index 7480cfa..e714363 100644 (file)
@@ -421,6 +421,19 @@ unsigned short gpio_get_value(unsigned short gpio);
 void gpio_direction_input(unsigned short gpio);
 void gpio_direction_output(unsigned short gpio);
 
+#include <asm-generic/gpio.h>          /* cansleep wrappers */
+#include <asm/irq.h>
+
+static inline int gpio_to_irq(unsigned gpio)
+{
+       return (gpio + GPIO_IRQ_BASE);
+}
+
+static inline int irq_to_gpio(unsigned irq)
+{
+       return (irq - GPIO_IRQ_BASE);
+}
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* __ARCH_BLACKFIN_GPIO_H__ */
index 9879e68..452fb82 100644 (file)
@@ -128,6 +128,8 @@ Core        Emulation               **
 #define IRQ_PF14               47
 #define IRQ_PF15               48
 
+#define GPIO_IRQ_BASE          IRQ_PF0
+
 #ifdef CONFIG_IRQCHIP_DEMUX_GPIO
 #define        NR_IRQS         (IRQ_PF15+1)
 #else
index 8af2a83..36c44bc 100644 (file)
@@ -160,6 +160,8 @@ Core        Emulation               **
 #define IRQ_PH14        96
 #define IRQ_PH15        97
 
+#define GPIO_IRQ_BASE  IRQ_PF0
+
 #ifdef CONFIG_IRQCHIP_DEMUX_GPIO
 #define NR_IRQS     (IRQ_PH15+1)
 #else
index e548d3c..21f06f7 100644 (file)
@@ -337,6 +337,8 @@ Events         (highest priority)  EMU         0
 #define IRQ_PJ14       BFIN_PJ_IRQ(14)         /* N/A */
 #define IRQ_PJ15       BFIN_PJ_IRQ(15)         /* N/A */
 
+#define GPIO_IRQ_BASE  IRQ_PA0
+
 #ifdef CONFIG_IRQCHIP_DEMUX_GPIO
 #define NR_IRQS     (IRQ_PJ15+1)
 #else
index a753ce7..1278992 100644 (file)
 #define IRQ_PF46               119
 #define IRQ_PF47               120
 
+#define GPIO_IRQ_BASE          IRQ_PF0
+
 #ifdef CONFIG_IRQCHIP_DEMUX_GPIO
 #define NR_IRQS                        (IRQ_PF47 + 1)
 #else