clk: renesas: r9a07g044: Add {M2, M2_DIV2} Clocks support

Add support for {M2, M2_DIV2} clocks which is sourced from pll3_533.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220430114156.6260-6-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index 0c9fa1f..d350d6d 100644 (file)
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -32,6 +32,7 @@ enum clk_ids {
        CLK_PLL3,
        CLK_PLL3_400,
        CLK_PLL3_533,
+       CLK_M2_DIV2,
        CLK_PLL3_DIV2,
        CLK_PLL3_DIV2_2,
        CLK_PLL3_DIV2_4,
@@ -86,7 +87,7 @@ static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" };
 static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" };
 
 static const struct {
-       struct cpg_core_clk common[48];
+       struct cpg_core_clk common[50];
 #ifdef CONFIG_CLK_R9A07G054
        struct cpg_core_clk drp[0];
 #endif
@@ -163,6 +164,8 @@ static const struct {
                DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8,
                        CLK_DIVIDER_HIWORD_MASK),
                DEF_FIXED("M1", R9A07G044_CLK_M1, CLK_PLL5_FOUTPOSTDIV, 1, 1),
+               DEF_FIXED("M2", R9A07G044_CLK_M2, CLK_PLL3_533, 1, 2),
+               DEF_FIXED("M2_DIV2", CLK_M2_DIV2, R9A07G044_CLK_M2, 1, 2),
        },
 #ifdef CONFIG_CLK_R9A07G054
        .drp = {