variables:
- windows_vm: vs2017-win2016
+ windows_vm: windows-2019
ubuntu_vm: ubuntu-18.04
macos_vm: macOS-10.15
- ci_runner_image: trini/u-boot-gitlab-ci-runner:focal-20210921-05Oct2021
+ ci_runner_image: trini/u-boot-gitlab-ci-runner:focal-20211006-14Nov2021
# Add '-u 0' options for Azure pipelines, otherwise we get "permission
# denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer",
# since our $(ci_runner_image) user is not root.
options: $(container_option)
steps:
- script: |
- ./tools/buildman/buildman --fetch-arch arm
- export PATH=~/.buildman-toolchains/gcc-9.2.0-nolibc/arm-linux-gnueabi/bin/:$PATH
+ export PATH=/opt/gcc-11.1.0-nolibc/arm-linux-gnueabi/bin:$PATH
test/nokia_rx51_test.sh
- job: test_py
--- /dev/null
+--find-maintainer-files --maintainer-path=.
# Grab our configured image. The source for this is found at:
# https://source.denx.de/u-boot/gitlab-ci-runner
-image: trini/u-boot-gitlab-ci-runner:focal-20210921-05Oct2021
+image: trini/u-boot-gitlab-ci-runner:focal-20211006-14Nov2021
# We run some tests in different order, to catch some failures quicker.
stages:
Run tests for Nokia RX-51 (aka N900):
stage: testsuites
script:
- - ./tools/buildman/buildman --fetch-arch arm;
- export PATH=~/.buildman-toolchains/gcc-9.2.0-nolibc/arm-linux-gnueabi/bin/:$PATH;
+ - export PATH=/opt/gcc-11.1.0-nolibc/arm-linux-gnueabi/bin:$PATH;
test/nokia_rx51_test.sh
# Test sandbox with test.py
Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@free-electrons.com>
Dirk Behme <dirk.behme@googlemail.com>
Fabio Estevam <fabio.estevam@nxp.com>
+Heinrich Schuchardt <xypron.glpk@gmx.de> <heinrich.schuchardt@canonical.com>
Jagan Teki <402jagan@gmail.com>
Jagan Teki <jaganna@gmail.com>
Jagan Teki <jaganna@xilinx.com>
source "api/Kconfig"
+source "boot/Kconfig"
+
source "common/Kconfig"
source "cmd/Kconfig"
F: doc/device-tree-bindings/mmc/snps,dw-mmc.txt
F: drivers/mmc/snps_dw_mmc.c
+APPLE M1 SOC SUPPORT
+M: Mark Kettenis <kettenis@openbsd.org>
+S: Maintained
+F: arch/arm/include/asm/arch-m1/
+F: arch/arm/mach-apple/
+F: configs/apple_m1_defconfig
+F: drivers/iommu/apple_dart.c
+F: include/configs/apple.h
+
ARM
M: Tom Rini <trini@konsulko.com>
S: Maintained
F: drivers/mmc/msm_sdhci.c
F: drivers/phy/msm8916-usbh-phy.c
F: drivers/serial/serial_msm.c
+F: drivers/serial/serial_msm_geni.c
F: drivers/smem/msm_smem.c
+F: drivers/spmi/spmi-msm.c
F: drivers/usb/host/ehci-msm.c
ARM STI
F: include/dm/
F: test/dm/
+EFI APP
+M: Simon Glass <sjg@chromium.org>
+M: Heinrich Schuchardt <xypron.glpk@gmx.de>
+S: Maintained
+W: https://u-boot.readthedocs.io/en/latest/develop/uefi/u-boot_on_efi.html
+F: board/efi/efi-x86_app
+F: configs/efi-x86_app*
+F: doc/develop/uefi/u-boot_on_efi.rst
+F: lib/efi/efi_app.c
+F: scripts/build-efi.sh
+
EFI PAYLOAD
M: Heinrich Schuchardt <xypron.glpk@gmx.de>
R: Alexander Graf <agraf@csgraf.de>
F: configs/j721e_hs_evm_r5_defconfig
F: configs/j721e_hs_evm_a72_defconfig
+TPM DRIVERS
+M: Ilias Apalodimas <ilias.apalodimas@linaro.org>
+S: Maintained
+F: drivers/tpm/
+
TQ GROUP
#M: Martin Krause <martin.krause@tq-systems.de>
S: Orphaned (Since 2016-02)
# SPDX-License-Identifier: GPL-2.0+
-VERSION = 2021
-PATCHLEVEL = 10
+VERSION = 2022
+PATCHLEVEL = 01
SUBLEVEL =
-EXTRAVERSION =
+EXTRAVERSION = -rc2
NAME =
# *DOCUMENTATION*
libs-$(CONFIG_API) += api/
libs-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/
+libs-y += boot/
libs-y += cmd/
libs-y += common/
libs-$(CONFIG_OF_EMBED) += dts/
ifeq ($(CONFIG_SPL_FRAMEWORK),y)
INPUTS-$(CONFIG_OF_SEPARATE) += u-boot-dtb.img
endif
-INPUTS-$(CONFIG_OF_HOSTFILE) += u-boot.dtb
+INPUTS-$(CONFIG_SANDBOX) += u-boot.dtb
ifneq ($(CONFIG_SPL_TARGET),)
INPUTS-$(CONFIG_SPL) += $(CONFIG_SPL_TARGET:"%"=%)
endif
# Avoid 'Not enough room for program headers' error on binutils 2.28 onwards.
LDFLAGS_u-boot += $(call ld-option, --no-dynamic-linker)
+# ld.lld support
+LDFLAGS_u-boot += -z notext
+
LDFLAGS_u-boot += --build-id=none
ifeq ($(CONFIG_ARC)$(CONFIG_NIOS2)$(CONFIG_X86)$(CONFIG_XTENSA),)
ifeq ($(CONFIG_DEPRECATED),y)
$(warning "You have deprecated configuration options enabled in your .config! Please check your configuration.")
endif
-ifeq ($(CONFIG_OF_EMBED),y)
+ifeq ($(CONFIG_OF_EMBED)$(CONFIG_EFI_APP),y)
@echo >&2 "===================== WARNING ======================"
@echo >&2 "CONFIG_OF_EMBED is enabled. This option should only"
@echo >&2 "be used for debugging purposes. Please use"
-a spl-bss-pad=$(if $(CONFIG_SPL_SEPARATE_BSS),,1) \
-a tpl-bss-pad=$(if $(CONFIG_TPL_SEPARATE_BSS),,1) \
-a spl-dtb=$(CONFIG_SPL_OF_REAL) \
- -a tpl-dtb=$(CONFIG_SPL_OF_REAL) \
+ -a tpl-dtb=$(CONFIG_TPL_OF_REAL) \
$(BINMAN_$(@F))
OBJCOPYFLAGS_u-boot.ldr.hex := -I binary -O ihex
else
ifneq ($(CONFIG_USE_SPL_FIT_GENERATOR),)
U_BOOT_ITS := u-boot.its
-ifeq ($(CONFIG_SPL_FIT_GENERATOR),"arch/arm/mach-imx/mkimage_fit_atf.sh")
-U_BOOT_ITS_DEPS += u-boot-nodtb.bin
-endif
ifeq ($(CONFIG_SPL_FIT_GENERATOR),"arch/arm/mach-rockchip/make_fit_atf.py")
U_BOOT_ITS_DEPS += u-boot
endif
u-boot-dtb.img u-boot.img u-boot.kwb u-boot.pbl u-boot-ivt.img: \
$(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin \
- $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_OF_HOSTFILE)$(CONFIG_BINMAN_STANDALONE_FDT),dts/dt.dtb) \
+ $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SANDBOX)$(CONFIG_BINMAN_STANDALONE_FDT),dts/dt.dtb) \
,$(UBOOT_BIN)) FORCE
$(call if_changed,mkimage)
$(BOARD_SIZE_CHECK)
ifdef U_BOOT_ITS
u-boot.itb: u-boot-nodtb.bin \
- $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_OF_HOSTFILE),dts/dt.dtb) \
+ $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SANDBOX),dts/dt.dtb) \
$(U_BOOT_ITS) FORCE
$(call if_changed,mkfitimage)
$(BOARD_SIZE_CHECK)
-Wl,-Map,u-boot.map; \
$(if $(ARCH_POSTLINK), $(MAKE) -f $(ARCH_POSTLINK) $@, true)
else
+# Note: Linking efi-x86_app64 causes a segfault in the linker at present
+# when using x86_64-linux-gnu-ld.bfd
+# For now, disable --whole-archive which makes things link, although not
+# correctly
quiet_cmd_u-boot__ ?= LD $@
cmd_u-boot__ ?= $(LD) $(KBUILD_LDFLAGS) $(LDFLAGS_u-boot) -o $@ \
-T u-boot.lds $(u-boot-init) \
- --whole-archive \
+ $(if $(CONFIG_EFI_APP_64BIT),,--whole-archive) \
$(u-boot-main) \
- --no-whole-archive \
+ $(if $(CONFIG_EFI_APP_64BIT),,--no-whole-archive) \
$(PLATFORM_LIBS) -Map u-boot.map; \
$(if $(ARCH_POSTLINK), $(MAKE) -f $(ARCH_POSTLINK) $@, true)
endif
$(filter-out include, $(shell ls -1 $d 2>/dev/null))))
CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h tools/version.h \
- boot* u-boot* MLO* SPL System.map fit-dtb.blob* \
+ u-boot* MLO* SPL System.map fit-dtb.blob* \
u-boot-ivt.img.log u-boot-dtb.imx.log SPL.log u-boot.imx.log \
lpc32xx-* bl31.c bl31.elf bl31_*.bin image.map tispl.bin* \
idbloader.img flash.bin flash.log defconfig keep-syms-lto.c
/xtensa Files generic to Xtensa architecture
/api Machine/arch-independent API for external apps
/board Board-dependent files
+/boot Support for images and booting
/cmd U-Boot commands functions
/common Misc architecture-independent functions
/configs Board default configuration files
controller register space
- Serial Ports:
- CONFIG_PL011_SERIAL
-
- Define this if you want support for Amba PrimeCell PL011 UARTs.
-
CONFIG_PL011_CLOCK
If you have Amba PrimeCell PL011 UARTs, set this variable to
U-Boot needs to get its device tree from somewhere. This can
be done using one of the three options below:
- CONFIG_OF_EMBED
- If this variable is defined, U-Boot will embed a device tree
- binary in its image. This device tree file should be in the
- board directory and called <soc>-<board>.dts. The binary file
- is then picked up in board_init_f() and made available through
- the global data structure as gd->fdt_blob.
-
CONFIG_OF_SEPARATE
If this variable is defined, U-Boot will build a device tree
binary. It will be called u-boot.dtb. Architecture-specific
SCSI devices found during the last scan.
- NETWORK Support (PCI):
- CONFIG_E1000
- Support for Intel 8254x/8257x gigabit chips.
-
CONFIG_E1000_SPI
Utility code for direct access to the SPI bus on Intel 8257x.
This does not do anything useful unless you set at least one
of CONFIG_CMD_E1000 or CONFIG_E1000_SPI_GENERIC.
- CONFIG_E1000_SPI_GENERIC
- Allow generic access to the SPI bus on the Intel 8257x, for
- example with the "sspi" command.
-
CONFIG_NATSEMI
Support for National dp83815 chips.
whether the enumeration has succeded at high speed or full
speed.
- CONFIG_SYS_CONSOLE_IS_IN_ENV
- Define this if you want stdin, stdout &/or stderr to
- be set to usbtty.
-
If you have a USB-IF assigned VendorID then you may wish to
define your own vendor specific values either in BoardName.h
or directly in usbd_vendor_info.h. If you don't define
Support drawing of RLE8-compressed bitmaps on the LCD.
- CONFIG_I2C_EDID
-
- Enables an 'i2c edid' command which can read EDID
- information over I2C from an attached LCD display.
-
- MII/PHY support:
CONFIG_PHY_CLOCK_FREQ (ppc4xx)
CONFIG_SPL
Enable building of SPL globally.
- CONFIG_SPL_LDSCRIPT
- LDSCRIPT for linking the SPL binary.
-
CONFIG_SPL_MAX_FOOTPRINT
Maximum size in memory allocated to the SPL, BSS included.
When defined, the linker checks that the actual memory
CONFIG_SYS_SPL_MALLOC_SIZE
The size of the malloc pool used in SPL.
- CONFIG_SPL_OS_BOOT
- Enable booting directly to an OS from SPL.
- See also: doc/README.falcon
-
CONFIG_SPL_DISPLAY_PRINT
For ARM, enable an optional function to print more information
about the running system.
config GIC_V3_ITS
bool "ARM GICV3 ITS"
- select REGMAP
- select SYSCON
select IRQ
help
ARM GICV3 Interrupt translation service (ITS).
select DM
select GPIO_EXTRA_HEADER
+config ARCH_APPLE
+ bool "Apple SoCs"
+ select ARM64
+ select BLK
+ select CLK
+ select CMD_USB
+ select DM
+ select DM_KEYBOARD
+ select DM_SERIAL
+ select DM_USB
+ select DM_VIDEO
+ select IOMMU
+ select LINUX_KERNEL_IMAGE_HEADER
+ select OF_CONTROL
+ select OF_BOARD
+ select POSITION_INDEPENDENT
+ select USB
+ imply CMD_DM
+ imply CMD_GPT
+ imply DISTRO_DEFAULTS
+
config ARCH_OWL
bool "Actions Semi OWL SoCs"
select DM
select OF_CONTROL
select OF_SEPARATE
select SPECIFY_CONSOLE_INDEX
+ select SPL_SEPARATE_BSS if SPL
select SPL_STACK_R if SPL
select SPL_SYS_MALLOC_SIMPLE if SPL
select SPL_SYS_THUMB_BUILD if !ARM64
imply SPL_MMC if MMC
imply SPL_POWER
imply SPL_SERIAL
+ imply SYSRESET
+ imply SYSRESET_WATCHDOG
+ imply SYSRESET_WATCHDOG_AUTO
imply USB_GADGET
+ imply WDT
config ARCH_U8500
bool "ST-Ericsson U8500 Series"
select CPU_V7M
select DM
select DM_SERIAL
- select GPIO_EXTRA_HEADER
imply CMD_DM
config ARCH_STI
select DM_GPIO
select DM_RESET
select DM_SERIAL
- select GPIO_EXTRA_HEADER
select MISC
select OF_CONTROL
select OF_LIBFDT
image headers.
endif
+source "arch/arm/mach-apple/Kconfig"
+
source "arch/arm/mach-aspeed/Kconfig"
source "arch/arm/mach-at91/Kconfig"
# Machine directory name. This list is sorted alphanumerically
# by CONFIG_* macro name.
+machine-$(CONFIG_ARCH_APPLE) += apple
machine-$(CONFIG_ARCH_ASPEED) += aspeed
machine-$(CONFIG_ARCH_AT91) += at91
machine-$(CONFIG_ARCH_BCM283X) += bcm283x
select SYS_HAS_SERDES
select SYS_FSL_DDR_BE
select SYS_FSL_MMDC
- select SYS_FSL_ERRATUM_A010315
+ select SYS_FSL_ERRATUM_A010315 if PCIE_LAYERSCAPE
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A008997
select SYS_FSL_ERRATUM_A009007
select SYS_FSL_ERRATUM_A009663 if !TFABOOT
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A009942 if !TFABOOT
- select SYS_FSL_ERRATUM_A010315
+ select SYS_FSL_ERRATUM_A010315 if PCIE_LAYERSCAPE
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_DDR4
config ARCH_LX2162A
bool
select ARMV8_SET_SMPEN
+ select FSL_LAYERSCAPE
select FSL_LSCH3
select GICV3
select NXP_LSCH3_2
config ARCH_LX2160A
bool
select ARMV8_SET_SMPEN
+ select FSL_LAYERSCAPE
select FSL_LSCH3
select GICV3
select HAS_FSL_XHCI_USB if USB_HOST
fdt_status_disabled(blob, off);
/* Disable GPU node */
- off = fdt_node_offset_by_compatible(blob, -1, "fsl,ls1028a-gpu");
+ off = fdt_node_offset_by_compatible(blob, -1, "vivante,gc");
if (off != -FDT_ERR_NOTFOUND)
fdt_status_disabled(blob, off);
}
SET_SATA_ICID(1, "fsl,ls1028a-ahci", FSL_SATA1_STREAM_ID),
SET_EDMA_ICID(FSL_EDMA_STREAM_ID),
SET_QDMA_ICID("fsl,ls1028a-qdma", FSL_DMA_STREAM_ID),
- SET_GPU_ICID("fsl,ls1028a-gpu", FSL_GPU_STREAM_ID),
+ SET_GPU_ICID("vivante,gc", FSL_GPU_STREAM_ID),
SET_DISPLAY_ICID(FSL_DISPLAY_STREAM_ID),
#ifdef CONFIG_FSL_CAAM
SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
#include <asm/system.h>
#include <asm/arch/mp.h>
#include <asm/arch/soc.h>
+#include <linux/compat.h>
#include <linux/delay.h>
#include <linux/psci.h>
+#include <malloc.h>
#include "cpu.h"
#include <asm/arch-fsl-layerscape/soc.h>
-#include <efi_loader.h>
DECLARE_GLOBAL_DATA_PTR;
int i, timeout = 10;
u64 *table;
#ifdef CONFIG_EFI_LOADER
- u64 reloc_addr = U32_MAX;
- efi_status_t ret;
+ void *reloc_addr;
#endif
#ifdef COUNTER_FREQUENCY_REAL
* Keep this after the __real_cntfrq update, so we have it when we
* copy the complete section here.
*/
- ret = efi_allocate_pages(EFI_ALLOCATE_MAX_ADDRESS,
- EFI_RESERVED_MEMORY_TYPE,
- efi_size_in_pages(secondary_boot_code_size),
- &reloc_addr);
- if (ret == EFI_SUCCESS) {
- debug("Relocating spin table from %llx to %llx (size %lx)\n",
- (u64)secondary_boot_code_start, reloc_addr,
+ reloc_addr = memalign(PAGE_SIZE,
+ round_up(secondary_boot_code_size, PAGE_SIZE));
+ if (reloc_addr) {
+ debug("Relocating spin table from %p to %p (size %lx)\n",
+ secondary_boot_code_start, reloc_addr,
secondary_boot_code_size);
- memcpy((void *)reloc_addr, secondary_boot_code_start,
+ memcpy(reloc_addr, secondary_boot_code_start,
secondary_boot_code_size);
- flush_dcache_range(reloc_addr,
- reloc_addr + secondary_boot_code_size);
+ flush_dcache_range((unsigned long)reloc_addr,
+ (unsigned long)reloc_addr +
+ secondary_boot_code_size);
/* set new entry point for secondary cores */
- secondary_boot_addr += (void *)reloc_addr -
+ secondary_boot_addr += reloc_addr -
secondary_boot_code_start;
flush_dcache_range((unsigned long)&secondary_boot_addr,
(unsigned long)&secondary_boot_addr + 8);
/* this will be used to reserve the memory */
- secondary_boot_code_start = (void *)reloc_addr;
+ secondary_boot_code_start = reloc_addr;
}
#endif
#endif
#ifdef CONFIG_GIC_V3_ITS
-int ls_gic_rd_tables_init(void *blob)
+#define PENDTABLE_MAX_SZ ALIGN(BIT(ITS_MAX_LPI_NRBITS), SZ_64K)
+#define PROPTABLE_MAX_SZ ALIGN(BIT(ITS_MAX_LPI_NRBITS) / 8, SZ_64K)
+#define GIC_LPI_SIZE ALIGN(cpu_numcores() * PENDTABLE_MAX_SZ + \
+ PROPTABLE_MAX_SZ, SZ_1M)
+static int fdt_add_resv_mem_gic_rd_tables(void *blob, u64 base, size_t size)
{
- struct fdt_memory lpi_base;
- fdt_addr_t addr;
- fdt_size_t size;
- int offset, ret;
+ int err;
+ struct fdt_memory gic_rd_tables;
- offset = fdt_path_offset(gd->fdt_blob, "/syscon@0x80000000");
- addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, offset, "reg",
- 0, &size, false);
+ gic_rd_tables.start = base;
+ gic_rd_tables.end = base + size - 1;
+ err = fdtdec_add_reserved_memory(blob, "gic-rd-tables", &gic_rd_tables,
+ NULL, 0, NULL, 0);
+ if (err < 0)
+ debug("%s: failed to add reserved memory: %d\n", __func__, err);
- lpi_base.start = addr;
- lpi_base.end = addr + size - 1;
- ret = fdtdec_add_reserved_memory(blob, "lpi_rd_table", &lpi_base, NULL,
- 0, NULL, 0);
- if (ret) {
- debug("%s: failed to add reserved memory\n", __func__);
+ return err;
+}
+
+int ls_gic_rd_tables_init(void *blob)
+{
+ u64 gic_lpi_base;
+ int ret;
+
+ gic_lpi_base = ALIGN(gd->arch.resv_ram - GIC_LPI_SIZE, SZ_64K);
+ ret = fdt_add_resv_mem_gic_rd_tables(blob, gic_lpi_base, GIC_LPI_SIZE);
+ if (ret)
return ret;
- }
- ret = gic_lpi_tables_init();
+ ret = gic_lpi_tables_init(gic_lpi_base, cpu_numcores());
if (ret)
debug("%s: failed to init gic-lpi-tables\n", __func__);
#define DWC3_GSBUSCFG0_CACHETYPE(n) (((n) & 0xffff) \
<< DWC3_GSBUSCFG0_CACHETYPE_SHIFT)
-void enable_dwc3_snooping(void)
+static void enable_dwc3_snooping(void)
{
- int ret;
- u32 val;
- struct udevice *bus;
- struct uclass *uc;
+ static const char * const compatibles[] = {
+ "fsl,layerscape-dwc3",
+ "fsl,ls1028a-dwc3",
+ };
fdt_addr_t dwc3_base;
+ ofnode node;
+ u32 val;
+ int i;
- ret = uclass_get(UCLASS_USB, &uc);
- if (ret)
- return;
-
- uclass_foreach_dev(bus, uc) {
- if (!strcmp(bus->driver->of_match->compatible, "fsl,layerscape-dwc3")) {
- dwc3_base = devfdt_get_addr(bus);
- if (dwc3_base == FDT_ADDR_T_NONE) {
- dev_err(bus, "dwc3 regs missing\n");
+ for (i = 0; i < ARRAY_SIZE(compatibles); i++) {
+ ofnode_for_each_compatible_node(node, compatibles[i]) {
+ dwc3_base = ofnode_get_addr(node);
+ if (dwc3_base == FDT_ADDR_T_NONE)
continue;
- }
+
val = in_le32(dwc3_base + DWC3_GSBUSCFG0);
val &= ~DWC3_GSBUSCFG0_CACHETYPE(~0);
val |= DWC3_GSBUSCFG0_CACHETYPE(0x2222);
exynos5800-peach-pi.dtb \
exynos5422-odroidxu3.dtb
dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb
+dtb-$(CONFIG_TARGET_A5Y17LTE) += exynos78x0-axy17lte.dtb
+dtb-$(CONFIG_TARGET_A3Y17LTE) += exynos78x0-axy17lte.dtb
+dtb-$(CONFIG_TARGET_A7Y17LTE) += exynos78x0-axy17lte.dtb
+
+dtb-$(CONFIG_ARCH_APPLE) += \
+ t8103-j274.dtb \
+ t8103-j293.dtb
dtb-$(CONFIG_ARCH_DAVINCI) += \
da850-evm.dtb \
dtb-$(CONFIG_TARGET_DRAGONBOARD410C) += dragonboard410c.dtb
dtb-$(CONFIG_TARGET_DRAGONBOARD820C) += dragonboard820c.dtb
+dtb-$(CONFIG_TARGET_STARQLTECHN) += starqltechn.dtb
dtb-$(CONFIG_TARGET_STEMMY) += ste-ux500-samsung-stemmy.dtb
imx6ul-liteboard.dtb \
imx6ul-phytec-segin-ff-rdk-nand.dtb \
imx6ul-pico-hobbit.dtb \
- imx6ul-pico-pi.dtb
+ imx6ul-pico-pi.dtb \
+ imx6ul-kontron-n631x-s.dtb \
+ imx6ull-kontron-n641x-s.dtb
dtb-$(CONFIG_MX6ULL) += \
imx6ull-14x14-evk.dtb \
imx6ull-colibri.dtb \
+ imx6ull-colibri-emmc.dtb \
imx6ull-myir-mys-6ulx-eval.dtb \
imx6ull-seeed-npi-imx6ull-dev-board.dtb \
imx6ull-phytec-segin-ff-rdk-emmc.dtb \
imx8mm-evk.dtb \
imx8mm-icore-mx8mm-ctouch2.dtb \
imx8mm-icore-mx8mm-edimm2.2.dtb \
+ imx8mm-kontron-n801x-s.dtb \
+ imx8mm-kontron-n801x-s-lvds.dtb \
imx8mm-venice.dtb \
imx8mm-venice-gw71xx-0x.dtb \
imx8mm-venice-gw72xx-0x.dtb \
dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE) += imx8mm-cl-iot-gate.dtb
+dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE_OPTEE) += imx8mm-cl-iot-gate-optee.dtb
+
dtb-$(CONFIG_TARGET_EA_LPC3250DEVKITV2) += lpc3250-ea3250.dtb
targets += $(dtb-y)
// SPDX-License-Identifier: GPL-2.0+ or X11
/*
- * Copyright (C) 2018 Grinn Sp. z o.o. -- http://www.grinn-global.com/
+ * Copyright (C) 2018-2021 Grinn Sp. z o.o. -- http://www.grinn-global.com/
* Author: Marcin Niestroj <m.niestroj@grinn-global.com>
*/
/ {
chosen {
stdout-path = &uart0;
+ tick-timer = &timer2;
};
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Samsung Exynos78x0 SoC device tree source
+ *
+ * Copyright (c) 2020 Dzmitry Sankouski (dsankouski@gmail.com)
+ */
+
+/dts-v1/;
+#include "exynos78x0.dtsi"
+/ {
+ compatible = "samsung,exynos78x0", "samsung,exynos7880", "samsung,exynos7870";
+
+ aliases {
+ console = &uart2;
+ };
+
+ chosen {
+ stdout-path = &uart2;
+ };
+};
+
+&gpioi2c0 {
+ status = "okay";
+};
+
+&fin_pll {
+ clock-frequency = <26000000>;
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Samsung's Exynos7880 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ * Copyright (c) 2020 Dzmitry Sankouski (dsankouski@gmail.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/ {
+ /* ALIVE */
+ gpio@139F0000 {
+ etc0: etc0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ etc1: etc1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpa0: gpa0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpa1: gpa1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpa2: gpa2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpa3: gpa3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpq0: gpq0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+ /* CCORE */
+ gpio@10630000 {
+ gpm0: gpm0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+ /* DISP/AUD */
+ gpio@148C0000 {
+ gpz0: gpz0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpz1: gpz1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpz2: gpz2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+ /* FSYS0 */
+ gpio@13750000 {
+ gpr0: gpr0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpr1: gpr1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpr2: gpr2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpr3: gpr3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpr4: gpr4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+ /* TOP */
+ gpio@139B0000 {
+ gpb0: gpb0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpc0: gpc0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpc1: gpc1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpc4: gpc4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpc5: gpc5 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpc6: gpc6 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpc8: gpc8 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpc9: gpc9 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpd1: gpd1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpd2: gpd2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpd3: gpd3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpd4: gpd4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpd5: gpd5 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpe0: gpe0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpf0: gpf0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpf1: gpf1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpf2: gpf2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpf3: gpf3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpf4: gpf4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Samsung's Exynos7880 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ * Copyright (c) 2020 Dzmitry Sankouski (dsankouski@gmail.com)
+ *
+ * Samsung's Exynos7880 SoC pin-mux and pin-config options are listed as device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/ {
+ /* ALIVE */
+ pinctrl@139F0000 {
+ uart2_bus: uart2-bus {
+ samsung,pins = "gpa1-1", "gpa1-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ };
+
+ dwmmc2_cd_ext_irq: dwmmc2_cd_ext_irq {
+ samsung,pins = "gpa3-3";
+ samsung,pin-function = <0xf>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <4>;
+ };
+
+ key_power: key-power {
+ samsung,pins = "gpa0-0";
+ samsung,pin-function = <0xf>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ key_voldown: key-voldown {
+ samsung,pins = "gpa2-1";
+ samsung,pin-function = <0xf>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ key_volup: key-volup {
+ samsung,pins = "gpa2-0";
+ samsung,pin-function = <0xf>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ key_home: key-home {
+ samsung,pins = "gpa1-7";
+ samsung,pin-function = <0xf>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+ };
+
+ /* TOP */
+ pinctrl@139B0000 {
+ i2c0_bus: i2c0-bus {
+ samsung,pins = "gpc1-1", "gpc1-0";
+ samsung,pin-function = <2>;
+ };
+
+ sd0_rst: sd0_rst {
+ samsung,pins = "gpc0-2";
+ samsung,pin-function = <0>;
+ };
+ };
+
+ /* DISP/AUD */
+ pinctrl@148C0000 {
+ i2s_pmic_bus: i2s-pmic-bus {
+ samsung,pins = "gpz1-0", "gpz1-1", "gpz1-2", "gpz1-3", "gpz1-4";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <1>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2s_pmic_bus_idle: i2s-pmic-bus_idle {
+ samsung,pins = "gpz1-0", "gpz1-1", "gpz1-2", "gpz1-3", "gpz1-4";
+ samsung,pin-function = <0>;
+ samsung,pin-pud = <1>;
+ samsung,pin-drv = <0>;
+ };
+ };
+
+ /* FSYS0 */
+ pinctrl@13750000 {
+ sd0_clk: sd0-clk {
+ samsung,pins = "gpr0-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <2>;
+ };
+
+ sd0_cmd: sd0-cmd {
+ samsung,pins = "gpr0-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <2>;
+ };
+
+ sd0_rdqs: sd0-rdqs {
+ samsung,pins = "gpr0-2";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <2>;
+ };
+
+ sd0_clk_fast_slew_rate_1x: sd0-clk_fast_slew_rate_1x {
+ samsung,pins = "gpr0-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ sd0_clk_fast_slew_rate_2x: sd0-clk_fast_slew_rate_2x {
+ samsung,pins = "gpr0-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <1>;
+ };
+
+ sd0_clk_fast_slew_rate_3x: sd0-clk_fast_slew_rate_3x {
+ samsung,pins = "gpr0-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <2>;
+ };
+
+ sd0_clk_fast_slew_rate_4x: sd0-clk_fast_slew_rate_4x {
+ samsung,pins = "gpr0-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd0_clk_fast_slew_rate_5x: sd0-clk_fast_slew_rate_5x {
+ samsung,pins = "gpr0-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <4>;
+ };
+
+ sd0_clk_fast_slew_rate_6x: sd0-clk_fast_slew_rate_6x {
+ samsung,pins = "gpr0-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <5>;
+ };
+
+ sd0_bus1: sd0-bus-width1 {
+ samsung,pins = "gpr1-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <2>;
+ };
+
+ sd0_bus4: sd0-bus-width4 {
+ samsung,pins = "gpr1-1", "gpr1-2", "gpr1-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <2>;
+ };
+
+ sd0_bus8: sd0-bus-width8 {
+ samsung,pins = "gpr1-4", "gpr1-5", "gpr1-6", "gpr1-7";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <2>;
+ };
+
+ sd1_clk: sd1-clk {
+ samsung,pins = "gpr2-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <2>;
+ };
+
+ sd1_cmd: sd1-cmd {
+ samsung,pins = "gpr2-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <2>;
+ };
+
+ sd1_bus1: sd1-bus-width1 {
+ samsung,pins = "gpr3-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <2>;
+ samsung,pin-con-pdn = <2>;
+ samsung,pin-pud-pdn = <3>;
+ };
+
+ sd1_bus4: sd1-bus-width4 {
+ samsung,pins = "gpr3-1", "gpr3-2", "gpr3-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <2>;
+ samsung,pin-con-pdn = <2>;
+ samsung,pin-pud-pdn = <3>;
+ };
+
+ sd2_clk: sd2-clk {
+ samsung,pins = "gpr4-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <2>;
+ };
+
+ sd2_cmd: sd2-cmd {
+ samsung,pins = "gpr4-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <2>;
+ };
+
+ sd2_bus1: sd2-bus-width1 {
+ samsung,pins = "gpr4-2";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <2>;
+ };
+
+ sd2_bus4: sd2-bus-width4 {
+ samsung,pins = "gpr4-3", "gpr4-4", "gpr4-5";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <2>;
+ };
+
+ sd2_clk_output: sd2-clk-output {
+ samsung,pins = "gpr4-0";
+ samsung,pin-function = <1>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <2>;
+ };
+
+ sd2_cmd_output: sd2-cmd-output {
+ samsung,pins = "gpr4-1";
+ samsung,pin-function = <1>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <2>;
+ };
+
+ sd2_clk_fast_slew_rate_1x: sd2-clk_fast_slew_rate_1x {
+ samsung,pins = "gpr4-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ sd2_clk_fast_slew_rate_2x: sd2-clk_fast_slew_rate_2x {
+ samsung,pins = "gpr4-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <1>;
+ };
+
+ sd2_clk_fast_slew_rate_3x: sd2-clk_fast_slew_rate_3x {
+ samsung,pins = "gpr4-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <2>;
+ };
+
+ sd2_clk_fast_slew_rate_4x: sd2-clk_fast_slew_rate_4x {
+ samsung,pins = "gpr4-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <3>;
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Samsung Exynos7880 SoC device tree source
+ *
+ * Copyright (c) 2020 Dzmitry Sankouski (dsankouski@gmail.com)
+ */
+
+/dts-v1/;
+#include "skeleton.dtsi"
+#include "exynos78x0-pinctrl.dtsi"
+#include "exynos78x0-gpio.dtsi"
+/ {
+ compatible = "samsung,exynos7880";
+
+ fin_pll: xxti {
+ compatible = "fixed-clock";
+ clock-output-names = "fin_pll";
+ u-boot,dm-pre-reloc;
+ #clock-cells = <0>;
+ };
+
+ /* Dummy clock for uart */
+ fin_uart: uart_dummy_fin {
+ compatible = "fixed-clock";
+ clock-output-names = "fin_uart";
+ clock-frequency = <132710400>;
+ u-boot,dm-pre-reloc;
+ #clock-cells = <0>;
+ };
+
+ uart2: serial@13820000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x13820000 0x100>;
+ u-boot,dm-pre-reloc;
+ clocks = <&fin_uart>, <&fin_uart>; // driver uses 1st clock
+ clock-names = "uart", "clk_uart_baud0";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_bus>;
+ };
+
+ gpioi2c0: i2c-0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "i2c-gpio";
+ status = "disabled";
+ gpios = <
+ &gpc1 0 0 /* sda */
+ &gpc1 1 0 /* scl */
+ >;
+ i2c-gpio,delay-us = <5>;
+
+ s2mu004@3d {
+ compatible = "samsung,s2mu004mfd";
+ };
+ };
+
+ /* ALIVE */
+ pinctrl_0: pinctrl@139F0000 {
+ compatible = "samsung,exynos78x0-pinctrl";
+ reg = <0x139F0000 0x1000>;
+ };
+
+ /* DISP/AUD */
+ pinctrl_2: pinctrl@148C0000 {
+ compatible = "samsung,exynos78x0-pinctrl";
+ reg = <0x148C0000 0x1000>;
+ };
+
+ /* FSYS0 */
+ pinctrl_4: pinctrl@13750000 {
+ compatible = "samsung,exynos78x0-pinctrl";
+ reg = <0x13750000 0x1000>;
+ };
+
+ /* ALIVE */
+ gpio_0: gpio@139F0000 {
+ compatible = "samsung,exynos78x0-gpio";
+ reg = <0x139F0000 0x1000>;
+ };
+
+ /* DISP/AUD */
+ gpio_2: gpio@148C0000 {
+ compatible = "samsung,exynos78x0-gpio";
+ reg = <0x148C0000 0x1000>;
+ };
+
+ /* FSYS0 */
+ gpio_4: gpio@13750000 {
+ compatible = "samsung,exynos78x0-gpio";
+ reg = <0x13750000 0x1000>;
+ };
+
+ /* TOP */
+ gpio_6: gpio@139B0000 {
+ compatible = "samsung,exynos78x0-gpio";
+ reg = <0x139B0000 0x1000>;
+ };
+};
interrupts = <0 64 0x4>;
clock-names = "dspi";
clocks = <&clockgen 4 0>;
- num-cs = <6>;
+ spi-num-chipselects = <6>;
big-endian;
status = "disabled";
};
compatible = "fsl,ls1012a-ahci";
reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
0x0 0x20140520 0x0 0x4>; /* ecc sata addr */
- reg-names = "sata-base", "ecc-addr";
+ reg-names = "ahci", "sata-ecc";
interrupts = <0 69 4>;
clocks = <&clockgen 4 0>;
status = "disabled";
/ {
aliases {
- mmc0 = &esdhc1;
- mmc1 = &esdhc0;
i2c0 = &i2c0;
i2c1 = &i2c3;
i2c2 = &i2c4;
- rtc0 = &rtc;
- ethernet2 = &enetc2;
- ethernet3 = &enetc6;
+ ethernet2 = &enetc_port2;
+ ethernet3 = &enetc_port3;
};
binman: binman {
+ multiple-images;
+ };
+};
+
+&binman {
+ u_boot_rom: u-boot-rom {
filename = "u-boot.rom";
pad-byte = <0xff>;
};
};
+&binman {
+ u-boot-update {
+ filename = "u-boot.update";
+
+ fit {
+ description = "FIT update image";
+
+ images {
+ u-boot-bin {
+ description = "U-Boot";
+ type = "firmware";
+ os = "u-boot";
+ arch = "arm";
+ compression = "none";
+ load = <0>; /* unused */
+
+ blob {
+ filename = "u-boot.rom";
+ };
+ };
+ };
+ };
+ };
+};
+
#ifdef CONFIG_SL28_ENABLE_SER0_CONSOLE
/ {
chosen {
#endif
#ifdef CONFIG_SL28_SPL_LOADS_ATF_BL31
-&binman {
+&u_boot_rom {
fit {
images {
bl31 {
#endif
#ifdef CONFIG_SL28_SPL_LOADS_OPTEE_BL32
-&binman {
+&u_boot_rom {
fit {
images {
bl32 {
};
#endif
-&i2c0 {
- rtc: rtc@32 {
- };
-};
-
&fspi {
u-boot,dm-pre-reloc;
flash@0 {
u-boot,dm-pre-reloc;
};
-&esdhc0 {
+&esdhc {
u-boot,dm-pre-reloc;
};
u-boot,dm-pre-reloc;
};
-&serial0 {
+&duart0 {
+ u-boot,dm-pre-reloc;
+};
+
+/*
+ * u-boot will enable the device in the linux device tree in place. Because
+ * we are using the linux device tree, we have to enable the PCI controller
+ * ourselves.
+ */
+&pcie1 {
+ status = "okay";
+};
+
+&pcie2 {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+};
+
+&soc {
u-boot,dm-pre-reloc;
};
/ {
aliases {
- ethernet0 = &enetc1;
+ ethernet0 = &enetc_port1;
};
};
* None of the four SerDes lanes are used by the module, instead they are
* all led out to the carrier for customer use.
*
- * Copyright (C) 2020 Michael Walle <michael@walle.cc>
+ * Copyright (C) 2021 Michael Walle <michael@walle.cc>
*
*/
compatible = "kontron,sl28-var1", "kontron,sl28", "fsl,ls1028a";
};
-&enetc0 {
- status = "disabled";
- /delete-property/ phy-handle;
-};
-
-&enetc1 {
- phy-handle = <&phy0>;
- phy-mode = "rgmii-id";
- status = "okay";
-};
+&enetc_mdio_pf3 {
+ /* Delete unused phy node */
+ /delete-node/ ethernet-phy@5;
-/delete-node/ &phy0;
-&mdio0 {
phy0: ethernet-phy@4 {
reg = <0x4>;
eee-broken-1000t;
eee-broken-100tx;
-
qca,clk-out-frequency = <125000000>;
qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
qca,keep-pll-enabled;
-
vddio-supply = <&vddio>;
vddio: vddio-regulator {
};
};
};
+
+&enetc_port0 {
+ status = "disabled";
+ /* Delete the phy-handle to the old phy0 label */
+ /delete-property/ phy-handle;
+};
+
+&enetc_port1 {
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+};
ethernet1 = &mscc_felix_port1;
};
};
+
+&mscc_felix_port0 {
+ label = "gbe0";
+};
+
+&mscc_felix_port1 {
+ label = "gbe1";
+};
/*
* Device Tree file for the Kontron SMARC-sAL28 board.
*
- * This is for the network variant 2 which has no ethernet support in the
- * bootloader.
+ * This is for the network variant 2 which has two ethernet ports. These
+ * ports are connected to the internal switch.
*
- * Copyright (C) 2020 Michael Walle <michael@walle.cc>
+ * Copyright (C) 2021 Michael Walle <michael@walle.cc>
*
*/
compatible = "kontron,sl28-var2", "kontron,sl28", "fsl,ls1028a";
};
-&enetc0 {
+&enetc_mdio_pf3 {
+ phy1: ethernet-phy@4 {
+ reg = <0x4>;
+ eee-broken-1000t;
+ eee-broken-100tx;
+ };
+};
+
+&enetc_port0 {
status = "disabled";
+ /*
+ * In the base device tree the PHY at address 5 was assigned for
+ * this port. On this module this PHY is connected to a switch
+ * port instead. Therefore, delete the phy-handle property here.
+ */
/delete-property/ phy-handle;
};
-&enetc2 {
+&enetc_port2 {
status = "okay";
};
};
&mscc_felix_port0 {
- label = "gbe0";
+ label = "swp0";
+ managed = "in-band-status";
phy-handle = <&phy0>;
phy-mode = "sgmii";
status = "okay";
};
&mscc_felix_port1 {
- label = "gbe1";
+ label = "swp1";
+ managed = "in-band-status";
phy-handle = <&phy1>;
phy-mode = "sgmii";
status = "okay";
};
&mscc_felix_port4 {
- ethernet = <&enetc2>;
+ ethernet = <&enetc_port2>;
status = "okay";
};
-
-/delete-node/ &phy0;
-&mdio0 {
- phy0: ethernet-phy@5 {
- reg = <0x5>;
- eee-broken-1000t;
- eee-broken-100tx;
- };
-
- phy1: ethernet-phy@4 {
- reg = <0x4>;
- eee-broken-1000t;
- eee-broken-100tx;
- };
-};
/ {
aliases {
- ethernet0 = &enetc0;
+ ethernet0 = &enetc_port0;
};
};
/ {
aliases {
- ethernet0 = &enetc0;
- ethernet1 = &enetc1;
+ ethernet0 = &enetc_port0;
+ ethernet1 = &enetc_port1;
};
};
* This is for the network variant 4 which has two ethernet ports. It
* extends the base and provides one more port connected via RGMII.
*
- * Copyright (C) 2019 Michael Walle <michael@walle.cc>
+ * Copyright (C) 2021 Michael Walle <michael@walle.cc>
*
*/
compatible = "kontron,sl28-var4", "kontron,sl28", "fsl,ls1028a";
};
-&enetc1 {
- phy-handle = <&phy1>;
- phy-mode = "rgmii-id";
- status = "okay";
-};
-
-&mdio0 {
+&enetc_mdio_pf3 {
phy1: ethernet-phy@4 {
reg = <0x4>;
eee-broken-1000t;
eee-broken-100tx;
-
qca,clk-out-frequency = <125000000>;
qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
qca,keep-pll-enabled;
-
vddio-supply = <&vddio>;
vddio: vddio-regulator {
};
};
};
+
+&enetc_port1 {
+ phy-handle = <&phy1>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+};
/*
* Device Tree file for the Kontron SMARC-sAL28 board.
*
- * Copyright (C) 2019 Michael Walle <michael@walle.cc>
+ * Copyright (C) 2021 Michael Walle <michael@walle.cc>
*
*/
/dts-v1/;
#include "fsl-ls1028a.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
/ {
model = "Kontron SMARC-sAL28";
compatible = "kontron,sl28", "fsl,ls1028a";
aliases {
- serial0 = &serial0;
- serial1 = &serial1;
+ crypto = &crypto;
+ serial0 = &duart0;
+ serial1 = &duart1;
serial2 = &lpuart1;
spi0 = &fspi;
spi1 = &dspi2;
+ mmc0 = &esdhc1;
+ mmc1 = &esdhc;
+ rtc0 = &rtc;
+ rtc1 = &ftm_alarm0;
+ };
+
+ buttons0 {
+ compatible = "gpio-keys";
+
+ power-button {
+ interrupts-extended = <&sl28cpld_intc
+ 4 IRQ_TYPE_EDGE_BOTH>;
+ linux,code = <KEY_POWER>;
+ label = "Power";
+ };
+
+ sleep-button {
+ interrupts-extended = <&sl28cpld_intc
+ 5 IRQ_TYPE_EDGE_BOTH>;
+ linux,code = <KEY_SLEEP>;
+ label = "Sleep";
+ };
+ };
+
+ buttons1 {
+ compatible = "gpio-keys-polled";
+ poll-interval = <200>;
+
+ lid-switch {
+ linux,input-type = <EV_SW>;
+ linux,code = <SW_LID>;
+ gpios = <&sl28cpld_gpio3 4 GPIO_ACTIVE_LOW>;
+ label = "Lid";
+ };
};
chosen {
};
};
+&can0 {
+ status = "okay";
+};
+
&dspi2 {
status = "okay";
};
-&enetc0 {
- phy-handle = <&phy0>;
- phy-mode = "sgmii";
+&duart0 {
+ status = "okay";
+};
+
+&duart1 {
status = "okay";
};
-&enetc2 {
- status = "disabled";
+&enetc_mdio_pf3 {
+ phy0: ethernet-phy@5 {
+ reg = <0x5>;
+ eee-broken-1000t;
+ eee-broken-100tx;
+ };
};
-&enetc6 {
- status = "disabled";
+&enetc_port0 {
+ phy-handle = <&phy0>;
+ phy-mode = "sgmii";
+ managed = "in-band-status";
+ status = "okay";
};
-&esdhc0 {
+&esdhc {
sd-uhs-sdr104;
sd-uhs-sdr50;
sd-uhs-sdr25;
status = "okay";
flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
compatible = "jedec,spi-nor";
m25p,fast-read;
spi-max-frequency = <133000000>;
/* The following setting enables 1-1-2 (CMD-ADDR-DATA) mode */
spi-rx-bus-width = <2>; /* 2 SPI Rx lines */
spi-tx-bus-width = <1>; /* 1 SPI Tx line */
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ reg = <0x000000 0x010000>;
+ label = "rcw";
+ read-only;
+ };
+
+ partition@10000 {
+ reg = <0x010000 0x1d0000>;
+ label = "failsafe bootloader";
+ read-only;
+ };
+
+ partition@200000 {
+ reg = <0x200000 0x010000>;
+ label = "configuration store";
+ };
+
+ partition@210000 {
+ reg = <0x210000 0x1d0000>;
+ label = "bootloader";
+ };
+
+ partition@3e0000 {
+ reg = <0x3e0000 0x020000>;
+ label = "bootloader environment";
+ };
+ };
};
};
+&gpio1 {
+ gpio-line-names =
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "TDO", "TCK",
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio2 {
+ gpio-line-names =
+ "", "", "", "", "", "", "TMS", "TDI",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
&i2c0 {
status = "okay";
- rtc@32 {
+ rtc: rtc@32 {
compatible = "microcrystal,rv8803";
reg = <0x32>;
};
+ sl28cpld@4a {
+ compatible = "kontron,sl28cpld";
+ reg = <0x4a>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ watchdog@4 {
+ compatible = "kontron,sl28cpld-wdt";
+ reg = <0x4>;
+ kontron,assert-wdt-timeout-pin;
+ };
+
+ hwmon@b {
+ compatible = "kontron,sl28cpld-fan";
+ reg = <0xb>;
+ };
+
+ sl28cpld_pwm0: pwm@c {
+ compatible = "kontron,sl28cpld-pwm";
+ reg = <0xc>;
+ #pwm-cells = <2>;
+ };
+
+ sl28cpld_pwm1: pwm@e {
+ compatible = "kontron,sl28cpld-pwm";
+ reg = <0xe>;
+ #pwm-cells = <2>;
+ };
+
+ sl28cpld_gpio0: gpio@10 {
+ compatible = "kontron,sl28cpld-gpio";
+ reg = <0x10>;
+ interrupts-extended = <&gpio2 6
+ IRQ_TYPE_EDGE_FALLING>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names =
+ "GPIO0_CAM0_PWR_N", "GPIO1_CAM1_PWR_N",
+ "GPIO2_CAM0_RST_N", "GPIO3_CAM1_RST_N",
+ "GPIO4_HDA_RST_N", "GPIO5_PWM_OUT",
+ "GPIO6_TACHIN", "GPIO7";
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ sl28cpld_gpio1: gpio@15 {
+ compatible = "kontron,sl28cpld-gpio";
+ reg = <0x15>;
+ interrupts-extended = <&gpio2 6
+ IRQ_TYPE_EDGE_FALLING>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names =
+ "GPIO8", "GPIO9", "GPIO10", "GPIO11",
+ "", "", "", "";
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ sl28cpld_gpio2: gpio@1a {
+ compatible = "kontron,sl28cpld-gpo";
+ reg = <0x1a>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names =
+ "LCD0 voltage enable",
+ "LCD0 backlight enable",
+ "eMMC reset", "LVDS bridge reset",
+ "LVDS bridge power-down",
+ "SDIO power enable",
+ "", "";
+ };
+
+ sl28cpld_gpio3: gpio@1b {
+ compatible = "kontron,sl28cpld-gpi";
+ reg = <0x1b>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names =
+ "Power button", "Force recovery", "Sleep",
+ "Battery low", "Lid state", "Charging",
+ "Charger present", "";
+ };
+
+ sl28cpld_intc: interrupt-controller@1c {
+ compatible = "kontron,sl28cpld-intc";
+ reg = <0x1c>;
+ interrupts-extended = <&gpio2 6
+ IRQ_TYPE_EDGE_FALLING>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
&lpuart1 {
status = "okay";
};
-
-&mdio0 {
- status = "okay";
- phy0: ethernet-phy@5 {
- reg = <0x5>;
- eee-broken-1000t;
- eee-broken-100tx;
- };
-};
-
-&sata {
- status = "okay";
-};
-
-&serial0 {
- status = "okay";
-};
-
-&serial1 {
- status = "okay";
-};
-
-&usb1 {
- status = "okay";
-};
-
-&usb2 {
- status = "okay";
-};
#include "fsl-sch-30842.dtsi"
};
-&enetc0 {
+&enetc_port0 {
status = "okay";
phy-mode = "usxgmii";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
};
#include "fsl-sch-30842.dtsi"
};
-&enetc0 {
+&enetc_port0 {
status = "okay";
phy-mode = "2500base-x";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
};
#include "fsl-sch-30841.dtsi"
};
-&enetc2 {
+&enetc_port2 {
status = "okay";
};
&mscc_felix_port0 {
status = "okay";
phy-mode = "2500base-x";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@00}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@00}>;
};
&mscc_felix_port1 {
status = "okay";
phy-mode = "2500base-x";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@01}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@01}>;
};
&mscc_felix_port2 {
status = "okay";
phy-mode = "2500base-x";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
};
&mscc_felix_port3 {
status = "okay";
phy-mode = "2500base-x";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>;
};
&mscc_felix_port4 {
- ethernet = <&enetc2>;
+ ethernet = <&enetc_port2>;
status = "okay";
};
#include "fsl-sch-30841.dtsi"
};
-&enetc2 {
+&enetc_port2 {
status = "okay";
};
&mscc_felix_port0 {
status = "okay";
phy-mode = "2500base-x";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
};
&mscc_felix_port3 {
status = "okay";
phy-mode = "2500base-x";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>;
};
&mscc_felix_port4 {
- ethernet = <&enetc2>;
+ ethernet = <&enetc_port2>;
status = "okay";
};
#include "fsl-sch-24801.dtsi"
};
-&enetc0 {
+&enetc_port0 {
status = "okay";
phy-mode = "sgmii";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>;
};
#include "fsl-sch-24801.dtsi"
};
-&enetc2 {
+&enetc_port2 {
status = "okay";
};
&mscc_felix_port0 {
status = "okay";
phy-mode = "sgmii";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>;
};
&mscc_felix_port1 {
status = "okay";
phy-mode = "sgmii";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@1c}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@1c}>;
};
&mscc_felix_port2 {
status = "okay";
phy-mode = "sgmii";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1e}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1e}>;
};
&mscc_felix_port3 {
status = "okay";
phy-mode = "sgmii";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1f}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1f}>;
};
&mscc_felix_port4 {
- ethernet = <&enetc2>;
+ ethernet = <&enetc_port2>;
status = "okay";
};
#include "fsl-sch-24801.dtsi"
};
-&enetc2 {
+&enetc_port2 {
status = "okay";
};
&mscc_felix_port0 {
status = "okay";
phy-mode = "sgmii";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>;
};
&mscc_felix_port1 {
status = "okay";
phy-mode = "sgmii";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1d}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1d}>;
};
&mscc_felix_port2 {
status = "okay";
phy-mode = "sgmii";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1e}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1e}>;
};
&mscc_felix_port3 {
status = "okay";
phy-mode = "sgmii";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1f}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1f}>;
};
&mscc_felix_port4 {
- ethernet = <&enetc2>;
+ ethernet = <&enetc_port2>;
status = "okay";
};
/ {
chosen {
- stdout-path = &serial0;
+ stdout-path = &duart0;
};
};
#include "fsl-sch-30841.dtsi"
};
-&enetc2 {
+&enetc_port2 {
status = "okay";
};
&mscc_felix_port0 {
status = "okay";
phy-mode = "usxgmii";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@00}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@00}>;
};
&mscc_felix_port1 {
status = "okay";
phy-mode = "usxgmii";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@01}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@01}>;
};
&mscc_felix_port2 {
status = "okay";
phy-mode = "usxgmii";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>;
};
&mscc_felix_port3 {
status = "okay";
phy-mode = "usxgmii";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@03}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@03}>;
};
&mscc_felix_port4 {
- ethernet = <&enetc2>;
+ ethernet = <&enetc_port2>;
status = "okay";
};
#include "fsl-sch-28021.dtsi"
};
-&enetc2 {
+&enetc_port2 {
status = "okay";
};
&mscc_felix_port0 {
status = "okay";
phy-mode = "qsgmii";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@08}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@08}>;
};
&mscc_felix_port1 {
status = "okay";
phy-mode = "qsgmii";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@09}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@09}>;
};
&mscc_felix_port2 {
status = "okay";
phy-mode = "qsgmii";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0a}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0a}>;
};
&mscc_felix_port3 {
status = "okay";
phy-mode = "qsgmii";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0b}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0b}>;
};
&mscc_felix_port4 {
- ethernet = <&enetc2>;
+ ethernet = <&enetc_port2>;
status = "okay";
};
#include "fsl-sch-30842.dtsi"
};
-&enetc2 {
+&enetc_port2 {
status = "okay";
};
&mscc_felix_port1 {
status = "okay";
phy-mode = "2500base-x";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>;
};
&mscc_felix_port4 {
- ethernet = <&enetc2>;
+ ethernet = <&enetc_port2>;
status = "okay";
};
#include "fsl-sch-30842.dtsi"
};
-&enetc2 {
+&enetc_port2 {
status = "okay";
};
&mscc_felix_port2 {
status = "okay";
phy-mode = "2500base-x";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@60/phy@02}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@60/phy@02}>;
};
&mscc_felix_port4 {
- ethernet = <&enetc2>;
+ ethernet = <&enetc_port2>;
status = "okay";
};
};
};
-&esdhc0 {
+&esdhc {
status = "okay";
};
&i2c0 {
status = "okay";
- u-boot,dm-pre-reloc;
fpga@66 {
#address-cells = <1>;
reg = <0x54>;
#mux-control-cells = <1>;
mux-reg-masks = <0x54 0xf0>;
- mdio-parent-bus = <&mdio0>;
+ mdio-parent-bus = <&enetc_mdio_pf3>;
/* on-board MDIO with a single RGMII PHY */
mdio@00 {
status = "okay";
};
-&serial0 {
+&duart0 {
status = "okay";
};
-&serial1 {
+&duart1 {
status = "okay";
};
-&usb1 {
+&pcie1 {
+ status = "okay";
+};
+
+&pcie2 {
status = "okay";
};
-&usb2 {
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
status = "okay";
};
-&enetc1 {
+&enetc_port1 {
status = "okay";
phy-mode = "rgmii-id";
phy-handle = <&qds_phy0>;
};
-&mdio0 {
+&enetc_mdio_pf3 {
status = "okay";
};
compatible = "fsl,ls1028a-rdb", "fsl,ls1028a";
aliases {
spi0 = &fspi;
- ethernet0 = &enetc0;
- ethernet1 = &enetc2;
+ ethernet0 = &enetc_port0;
+ ethernet1 = &enetc_port2;
ethernet2 = &mscc_felix_port0;
ethernet3 = &mscc_felix_port1;
ethernet4 = &mscc_felix_port2;
status = "okay";
};
-&esdhc0 {
+&esdhc {
status = "okay";
};
&i2c0 {
status = "okay";
- u-boot,dm-pre-reloc;
i2c-mux@77 {
status = "okay";
};
-&serial0 {
+&duart0 {
status = "okay";
};
-&serial1 {
+&duart1 {
status = "okay";
};
-&usb1 {
+&pcie1 {
+ status = "okay";
+};
+
+&pcie2 {
status = "okay";
};
-&usb2 {
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
status = "okay";
};
-&enetc0 {
+&enetc_port0 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&rdb_phy0>;
};
-&enetc2 {
+&enetc_port2 {
status = "okay";
};
};
&mscc_felix_port4 {
- ethernet = <&enetc2>;
+ ethernet = <&enetc_port2>;
status = "okay";
};
-&mdio0 {
+&enetc_mdio_pf3 {
status = "okay";
rdb_phy0: phy@2 {
reg = <2>;
-// SPDX-License-Identifier: GPL-2.0+ OR X11
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * NXP ls1028a SOC common device tree source
+ * Device Tree Include file for NXP Layerscape-1028A family SoC.
*
- * Copyright 2019-2020 NXP
+ * Copyright 2018-2020 NXP
+ *
+ * Harninder Rai <harninder.rai@nxp.com>
*
*/
+#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "fsl,ls1028a";
#address-cells = <2>;
#size-cells = <2>;
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x0>;
+ enable-method = "psci";
+ clocks = <&clockgen QORIQ_CLK_CMUX 0>;
+ next-level-cache = <&l2>;
+ cpu-idle-states = <&CPU_PW20>;
+ #cooling-cells = <2>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x1>;
+ enable-method = "psci";
+ clocks = <&clockgen QORIQ_CLK_CMUX 0>;
+ next-level-cache = <&l2>;
+ cpu-idle-states = <&CPU_PW20>;
+ #cooling-cells = <2>;
+ };
+
+ l2: l2-cache {
+ compatible = "cache";
+ };
+ };
+
+ idle-states {
+ /*
+ * PSCI node is not added default, U-boot will add missing
+ * parts if it determines to use PSCI.
+ */
+ entry-method = "psci";
+
+ CPU_PW20: cpu-pw20 {
+ compatible = "arm,idle-state";
+ idle-state-name = "PW20";
+ arm,psci-suspend-param = <0x0>;
+ entry-latency-us = <2000>;
+ exit-latency-us = <2000>;
+ min-residency-us = <6000>;
+ };
+ };
+
sysclk: sysclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-output-names = "sysclk";
};
- clockgen: clocking@1300000 {
- compatible = "fsl,ls1028a-clockgen";
- reg = <0x0 0x1300000 0x0 0xa0000>;
- #clock-cells = <2>;
- clocks = <&sysclk>;
+ osc_27m: clock-osc-27m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+ clock-output-names = "phy_27m";
};
- memory@01080000 {
- device_type = "memory";
- reg = <0x00000000 0x01080000 0 0x80000000>;
- /* DRAM space - 1, size : 2 GB DRAM */
+ dpclk: clock-controller@f1f0000 {
+ compatible = "fsl,ls1028a-plldig";
+ reg = <0x0 0xf1f0000 0x0 0xffff>;
+ #clock-cells = <0>;
+ clocks = <&osc_27m>;
};
- gic: interrupt-controller@6000000 {
- compatible = "arm,gic-v3";
- reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
- <0x0 0x06040000 0 0x40000>;
- #interrupt-cells = <3>;
- interrupt-controller;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
- IRQ_TYPE_LEVEL_LOW)>;
+ firmware {
+ optee: optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ status = "disabled";
+ };
};
- gic_lpi_base: syscon@0x80000000 {
- compatible = "gic-lpi-base";
- reg = <0x0 0x80000000 0x0 0x100000>;
- max-gic-redistributors = <2>;
+ reboot {
+ compatible ="syscon-reboot";
+ regmap = <&rst>;
+ offset = <0>;
+ mask = <0x02>;
};
timer {
IRQ_TYPE_LEVEL_LOW)>;
};
- fspi: flexspi@20c0000 {
- compatible = "nxp,lx2160a-fspi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0 0x20c0000 0x0 0x10000>,
- <0x0 0x20000000 0x0 0x10000000>;
- reg-names = "fspi_base", "fspi_mmap";
- clocks = <&clockgen 4 3>, <&clockgen 4 3>;
- clock-names = "fspi_en", "fspi";
- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
+ pmu {
+ compatible = "arm,cortex-a72-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
- serial0: serial@21c0500 {
- device_type = "serial";
- compatible = "fsl,ns16550", "ns16550a";
- reg = <0x0 0x21c0500 0x0 0x100>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
+ gic: interrupt-controller@6000000 {
+ compatible= "arm,gic-v3";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */
+ <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */
+ #interrupt-cells= <3>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ its: gic-its@6020000 {
+ compatible = "arm,gic-v3-its";
+ msi-controller;
+ reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */
+ };
};
- serial1: serial@21c0600 {
- device_type = "serial";
- compatible = "fsl,ns16550", "ns16550a";
- reg = <0x0 0x21c0600 0x0 0x100>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
+ thermal-zones {
+ ddr-controller {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = <&tmu 0>;
- pcie1: pcie@3400000 {
- compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
- reg = <0x00 0x03400000 0x0 0x80000
- 0x00 0x03480000 0x0 0x40000 /* lut registers */
- 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
- 0x80 0x00000000 0x0 0x20000>; /* configuration space */
- reg-names = "dbi", "lut", "ctrl", "config";
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- num-lanes = <4>;
- bus-range = <0x0 0xff>;
- ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000 /* downstream I/O */
- 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
- };
+ trips {
+ ddr-ctrler-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ ddr-ctrler-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ core-cluster {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = <&tmu 1>;
- pcie2: pcie@3500000 {
- compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
- reg = <0x00 0x03500000 0x0 0x80000
- 0x00 0x03580000 0x0 0x40000 /* lut registers */
- 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */
- 0x88 0x00000000 0x0 0x20000>; /* configuration space */
- reg-names = "dbi", "lut", "ctrl", "config";
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- num-lanes = <4>;
- bus-range = <0x0 0xff>;
- ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000 /* downstream I/O */
- 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ trips {
+ core_cluster_alert: core-cluster-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ core_cluster_crit: core-cluster-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&core_cluster_alert>;
+ cooling-device =
+ <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
};
- pcie@1f0000000 {
- compatible = "pci-host-ecam-generic";
- /* ECAM bus 0, HW has more space reserved but not populated */
- bus-range = <0x0 0x0>;
- reg = <0x01 0xf0000000 0x0 0x100000>;
- #address-cells = <3>;
+ soc: soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
#size-cells = <2>;
- device_type = "pci";
- ranges= <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000>;
- enetc0: pci@0,0 {
- reg = <0x000000 0 0 0 0>;
+ ranges;
+
+ ddr: memory-controller@1080000 {
+ compatible = "fsl,qoriq-memory-controller";
+ reg = <0x0 0x1080000 0x0 0x1000>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ little-endian;
+ };
+
+ dcfg: syscon@1e00000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,ls1028a-dcfg", "syscon", "simple-mfd";
+ reg = <0x0 0x1e00000 0x0 0x10000>;
+ ranges = <0x0 0x0 0x1e00000 0x10000>;
+ little-endian;
+
+ fspi_clk: clock-controller@900 {
+ compatible = "fsl,ls1028a-flexspi-clk";
+ reg = <0x900 0x4>;
+ #clock-cells = <0>;
+ clocks = <&clockgen QORIQ_CLK_HWACCEL 0>;
+ clock-output-names = "fspi_clk";
+ };
+ };
+
+ rst: syscon@1e60000 {
+ compatible = "syscon";
+ reg = <0x0 0x1e60000 0x0 0x10000>;
+ little-endian;
+ };
+
+ scfg: syscon@1fc0000 {
+ compatible = "fsl,ls1028a-scfg", "syscon";
+ reg = <0x0 0x1fc0000 0x0 0x10000>;
+ big-endian;
+ };
+
+ clockgen: clock-controller@1300000 {
+ compatible = "fsl,ls1028a-clockgen";
+ reg = <0x0 0x1300000 0x0 0xa0000>;
+ #clock-cells = <2>;
+ clocks = <&sysclk>;
+ };
+
+ i2c0: i2c@2000000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2000000 0x0 0x10000>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(4)>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@2010000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2010000 0x0 0x10000>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(4)>;
status = "disabled";
};
- enetc1: pci@0,1 {
- reg = <0x000100 0 0 0 0>;
+
+ i2c2: i2c@2020000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2020000 0x0 0x10000>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(4)>;
status = "disabled";
};
- enetc2: pci@0,2 {
- reg = <0x000200 0 0 0 0>;
+
+ i2c3: i2c@2030000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2030000 0x0 0x10000>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(4)>;
status = "disabled";
- phy-mode = "internal";
+ };
- fixed-link {
- speed = <2500>;
- full-duplex;
- };
+ i2c4: i2c@2040000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2040000 0x0 0x10000>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(4)>;
+ status = "disabled";
};
- mdio0: pci@0,3 {
- #address-cells=<0>;
- #size-cells=<1>;
- reg = <0x000300 0 0 0 0>;
+
+ i2c5: i2c@2050000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2050000 0x0 0x10000>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(4)>;
status = "disabled";
+ };
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
+ i2c6: i2c@2060000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2060000 0x0 0x10000>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(4)>;
+ status = "disabled";
};
- mscc_felix: pci@0,5 {
- reg = <0x000500 0 0 0 0>;
+ i2c7: i2c@2070000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2070000 0x0 0x10000>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(4)>;
status = "disabled";
+ };
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
+ fspi: spi@20c0000 {
+ compatible = "nxp,lx2160a-fspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x20c0000 0x0 0x10000>,
+ <0x0 0x20000000 0x0 0x10000000>;
+ reg-names = "fspi_base", "fspi_mmap";
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&fspi_clk>, <&fspi_clk>;
+ clock-names = "fspi_en", "fspi";
+ status = "disabled";
+ };
- mscc_felix_port0: port@0 {
- reg = <0>;
- status = "disabled";
- };
+ dspi0: spi@2100000 {
+ compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2100000 0x0 0x10000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "dspi";
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
+ dmas = <&edma0 0 62>, <&edma0 0 60>;
+ dma-names = "tx", "rx";
+ spi-num-chipselects = <4>;
+ little-endian;
+ status = "disabled";
+ };
- mscc_felix_port1: port@1 {
- reg = <1>;
- status = "disabled";
- };
+ dspi1: spi@2110000 {
+ compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2110000 0x0 0x10000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "dspi";
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
+ dmas = <&edma0 0 58>, <&edma0 0 56>;
+ dma-names = "tx", "rx";
+ spi-num-chipselects = <4>;
+ little-endian;
+ status = "disabled";
+ };
- mscc_felix_port2: port@2 {
- reg = <2>;
- status = "disabled";
- };
+ dspi2: spi@2120000 {
+ compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2120000 0x0 0x10000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "dspi";
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
+ dmas = <&edma0 0 54>, <&edma0 0 2>;
+ dma-names = "tx", "rx";
+ spi-num-chipselects = <3>;
+ little-endian;
+ status = "disabled";
+ };
- mscc_felix_port3: port@3 {
- reg = <3>;
- status = "disabled";
- };
+ esdhc: mmc@2140000 {
+ compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
+ reg = <0x0 0x2140000 0x0 0x10000>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <0>; /* fixed up by bootloader */
+ clocks = <&clockgen QORIQ_CLK_HWACCEL 1>;
+ voltage-ranges = <1800 1800 3300 3300>;
+ sdhci,auto-cmd12;
+ little-endian;
+ bus-width = <4>;
+ status = "disabled";
+ };
- mscc_felix_port4: port@4 {
- reg = <4>;
- phy-mode = "internal";
- status = "disabled";
+ esdhc1: mmc@2150000 {
+ compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
+ reg = <0x0 0x2150000 0x0 0x10000>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <0>; /* fixed up by bootloader */
+ clocks = <&clockgen QORIQ_CLK_HWACCEL 1>;
+ voltage-ranges = <1800 1800>;
+ sdhci,auto-cmd12;
+ non-removable;
+ little-endian;
+ bus-width = <4>;
+ status = "disabled";
+ };
- fixed-link {
- speed = <2500>;
- full-duplex;
- };
- };
+ can0: can@2180000 {
+ compatible = "fsl,lx2160ar1-flexcan";
+ reg = <0x0 0x2180000 0x0 0x10000>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
- mscc_felix_port5: port@5 {
- reg = <5>;
- phy-mode = "internal";
- status = "disabled";
+ can1: can@2190000 {
+ compatible = "fsl,lx2160ar1-flexcan";
+ reg = <0x0 0x2190000 0x0 0x10000>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
+ duart0: serial@21c0500 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x00 0x21c0500 0x0 0x100>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
+ status = "disabled";
+ };
- };
+ duart1: serial@21c0600 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x00 0x21c0600 0x0 0x100>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
+ status = "disabled";
+ };
+
+
+ lpuart0: serial@2260000 {
+ compatible = "fsl,ls1028a-lpuart";
+ reg = <0x0 0x2260000 0x0 0x1000>;
+ interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
+ clock-names = "ipg";
+ dma-names = "rx","tx";
+ dmas = <&edma0 1 32>,
+ <&edma0 1 33>;
+ status = "disabled";
+ };
+
+ lpuart1: serial@2270000 {
+ compatible = "fsl,ls1028a-lpuart";
+ reg = <0x0 0x2270000 0x0 0x1000>;
+ interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
+ clock-names = "ipg";
+ dma-names = "rx","tx";
+ dmas = <&edma0 1 30>,
+ <&edma0 1 31>;
+ status = "disabled";
+ };
+
+ lpuart2: serial@2280000 {
+ compatible = "fsl,ls1028a-lpuart";
+ reg = <0x0 0x2280000 0x0 0x1000>;
+ interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
+ clock-names = "ipg";
+ dma-names = "rx","tx";
+ dmas = <&edma0 1 28>,
+ <&edma0 1 29>;
+ status = "disabled";
+ };
+
+ lpuart3: serial@2290000 {
+ compatible = "fsl,ls1028a-lpuart";
+ reg = <0x0 0x2290000 0x0 0x1000>;
+ interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
+ clock-names = "ipg";
+ dma-names = "rx","tx";
+ dmas = <&edma0 1 26>,
+ <&edma0 1 27>;
+ status = "disabled";
+ };
+
+ lpuart4: serial@22a0000 {
+ compatible = "fsl,ls1028a-lpuart";
+ reg = <0x0 0x22a0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
+ clock-names = "ipg";
+ dma-names = "rx","tx";
+ dmas = <&edma0 1 24>,
+ <&edma0 1 25>;
+ status = "disabled";
+ };
+
+ lpuart5: serial@22b0000 {
+ compatible = "fsl,ls1028a-lpuart";
+ reg = <0x0 0x22b0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
+ clock-names = "ipg";
+ dma-names = "rx","tx";
+ dmas = <&edma0 1 22>,
+ <&edma0 1 23>;
+ status = "disabled";
+ };
+
+ edma0: dma-controller@22c0000 {
+ #dma-cells = <2>;
+ compatible = "fsl,ls1028a-edma", "fsl,vf610-edma";
+ reg = <0x0 0x22c0000 0x0 0x10000>,
+ <0x0 0x22d0000 0x0 0x10000>,
+ <0x0 0x22e0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "edma-tx", "edma-err";
+ dma-channels = <32>;
+ clock-names = "dmamux0", "dmamux1";
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
+ };
+
+ gpio1: gpio@2300000 {
+ compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
+ reg = <0x0 0x2300000 0x0 0x10000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ little-endian;
+ };
+
+ gpio2: gpio@2310000 {
+ compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
+ reg = <0x0 0x2310000 0x0 0x10000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ little-endian;
+ };
+
+ gpio3: gpio@2320000 {
+ compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
+ reg = <0x0 0x2320000 0x0 0x10000>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ little-endian;
+ };
+
+ usb0: usb@3100000 {
+ compatible = "fsl,ls1028a-dwc3", "snps,dwc3";
+ reg = <0x0 0x3100000 0x0 0x10000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
+ snps,dis_rxdet_inp3_quirk;
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ };
+
+ usb1: usb@3110000 {
+ compatible = "fsl,ls1028a-dwc3", "snps,dwc3";
+ reg = <0x0 0x3110000 0x0 0x10000>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
+ snps,dis_rxdet_inp3_quirk;
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ };
+
+ sata: sata@3200000 {
+ compatible = "fsl,ls1028a-ahci";
+ reg = <0x0 0x3200000 0x0 0x10000>,
+ <0x7 0x100520 0x0 0x4>;
+ reg-names = "ahci", "sata-ecc";
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
+ status = "disabled";
+ };
+
+ pcie1: pcie@3400000 {
+ compatible = "fsl,ls1028a-pcie";
+ reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
+ <0x80 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
+ interrupt-names = "pme", "aer";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ dma-coherent;
+ num-viewport = <8>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ msi-parent = <&its>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
+ status = "disabled";
+ };
+
+ pcie2: pcie@3500000 {
+ compatible = "fsl,ls1028a-pcie";
+ reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
+ <0x88 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pme", "aer";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ dma-coherent;
+ num-viewport = <8>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ msi-parent = <&its>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
+ status = "disabled";
+ };
+
+ smmu: iommu@5000000 {
+ compatible = "arm,mmu-500";
+ reg = <0 0x5000000 0 0x800000>;
+ #global-interrupts = <8>;
+ #iommu-cells = <1>;
+ stream-match-mask = <0x7c00>;
+ /* global secure fault */
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ /* combined secure interrupt */
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ /* global non-secure fault */
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ /* combined non-secure interrupt */
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ /* performance counter interrupts 0-7 */
+ <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
+ /* per context interrupt, 64 interrupts */
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ crypto: crypto@8000000 {
+ compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
+ fsl,sec-era = <10>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x8000000 0x100000>;
+ reg = <0x00 0x8000000 0x0 0x100000>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
+
+ sec_jr0: jr@10000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x10000 0x10000>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr1: jr@20000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x10000>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr2: jr@30000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x10000>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ sec_jr3: jr@40000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x10000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ qdma: dma-controller@8380000 {
+ compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma";
+ reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
+ <0x0 0x8390000 0x0 0x10000>, /* Status regs */
+ <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "qdma-error", "qdma-queue0",
+ "qdma-queue1", "qdma-queue2", "qdma-queue3";
+ dma-channels = <8>;
+ block-number = <1>;
+ block-offset = <0x10000>;
+ fsl,dma-queues = <2>;
+ status-sizes = <64>;
+ queue-sizes = <64 64>;
+ };
+
+ cluster1_core0_watchdog: watchdog@c000000 {
+ compatible = "arm,sp805", "arm,primecell";
+ reg = <0x0 0xc000000 0x0 0x1000>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(16)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(16)>;
+ clock-names = "wdog_clk", "apb_pclk";
+ };
+
+ cluster1_core1_watchdog: watchdog@c010000 {
+ compatible = "arm,sp805", "arm,primecell";
+ reg = <0x0 0xc010000 0x0 0x1000>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(16)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(16)>;
+ clock-names = "wdog_clk", "apb_pclk";
};
- enetc6: pci@0,6 {
- reg = <0x000600 0 0 0 0>;
+ sai1: audio-controller@f100000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,vf610-sai";
+ reg = <0x0 0xf100000 0x0 0x10000>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dma-names = "tx", "rx";
+ dmas = <&edma0 1 4>,
+ <&edma0 1 3>;
+ fsl,sai-asynchronous;
status = "disabled";
- phy-mode = "internal";
};
- };
- i2c0: i2c@2000000 {
- compatible = "fsl,vf610-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0 0x2000000 0x0 0x10000>;
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "i2c";
- clocks = <&clockgen 4 0>;
- status = "disabled";
- };
+ sai2: audio-controller@f110000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,vf610-sai";
+ reg = <0x0 0xf110000 0x0 0x10000>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dma-names = "tx", "rx";
+ dmas = <&edma0 1 6>,
+ <&edma0 1 5>;
+ fsl,sai-asynchronous;
+ status = "disabled";
+ };
- i2c1: i2c@2010000 {
- compatible = "fsl,vf610-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0 0x2010000 0x0 0x10000>;
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "i2c";
- clocks = <&clockgen 4 0>;
- status = "disabled";
- };
+ sai3: audio-controller@f120000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,vf610-sai";
+ reg = <0x0 0xf120000 0x0 0x10000>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dma-names = "tx", "rx";
+ dmas = <&edma0 1 8>,
+ <&edma0 1 7>;
+ fsl,sai-asynchronous;
+ status = "disabled";
+ };
- i2c2: i2c@2020000 {
- compatible = "fsl,vf610-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0 0x2020000 0x0 0x10000>;
- interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "i2c";
- clocks = <&clockgen 4 0>;
- status = "disabled";
- };
+ sai4: audio-controller@f130000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,vf610-sai";
+ reg = <0x0 0xf130000 0x0 0x10000>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dma-names = "tx", "rx";
+ dmas = <&edma0 1 10>,
+ <&edma0 1 9>;
+ fsl,sai-asynchronous;
+ status = "disabled";
+ };
- i2c3: i2c@2030000 {
- compatible = "fsl,vf610-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0 0x2030000 0x0 0x10000>;
- interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "i2c";
- clocks = <&clockgen 4 0>;
- status = "disabled";
- };
+ sai5: audio-controller@f140000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,vf610-sai";
+ reg = <0x0 0xf140000 0x0 0x10000>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dma-names = "tx", "rx";
+ dmas = <&edma0 1 12>,
+ <&edma0 1 11>;
+ fsl,sai-asynchronous;
+ status = "disabled";
+ };
- i2c4: i2c@2040000 {
- compatible = "fsl,vf610-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0 0x2040000 0x0 0x10000>;
- interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "i2c";
- clocks = <&clockgen 4 0>;
- status = "disabled";
- };
+ sai6: audio-controller@f150000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,vf610-sai";
+ reg = <0x0 0xf150000 0x0 0x10000>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dma-names = "tx", "rx";
+ dmas = <&edma0 1 14>,
+ <&edma0 1 13>;
+ fsl,sai-asynchronous;
+ status = "disabled";
+ };
- i2c5: i2c@2050000 {
- compatible = "fsl,vf610-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0 0x2050000 0x0 0x10000>;
- interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "i2c";
- clocks = <&clockgen 4 0>;
- status = "disabled";
- };
+ tmu: tmu@1f80000 {
+ compatible = "fsl,qoriq-tmu";
+ reg = <0x0 0x1f80000 0x0 0x10000>;
+ interrupts = <0 23 0x4>;
+ fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
+ fsl,tmu-calibration = <0x00000000 0x00000024
+ 0x00000001 0x0000002b
+ 0x00000002 0x00000031
+ 0x00000003 0x00000038
+ 0x00000004 0x0000003f
+ 0x00000005 0x00000045
+ 0x00000006 0x0000004c
+ 0x00000007 0x00000053
+ 0x00000008 0x00000059
+ 0x00000009 0x00000060
+ 0x0000000a 0x00000066
+ 0x0000000b 0x0000006d
- i2c6: i2c@2060000 {
- compatible = "fsl,vf610-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0 0x2060000 0x0 0x10000>;
- interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "i2c";
- clocks = <&clockgen 4 0>;
- status = "disabled";
- };
+ 0x00010000 0x0000001c
+ 0x00010001 0x00000024
+ 0x00010002 0x0000002c
+ 0x00010003 0x00000035
+ 0x00010004 0x0000003d
+ 0x00010005 0x00000045
+ 0x00010006 0x0000004d
+ 0x00010007 0x00000055
+ 0x00010008 0x0000005e
+ 0x00010009 0x00000066
+ 0x0001000a 0x0000006e
- i2c7: i2c@2070000 {
- compatible = "fsl,vf610-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0 0x2070000 0x0 0x10000>;
- interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "i2c";
- clocks = <&clockgen 4 0>;
- status = "disabled";
- };
+ 0x00020000 0x00000018
+ 0x00020001 0x00000022
+ 0x00020002 0x0000002d
+ 0x00020003 0x00000038
+ 0x00020004 0x00000043
+ 0x00020005 0x0000004d
+ 0x00020006 0x00000058
+ 0x00020007 0x00000063
+ 0x00020008 0x0000006e
- lpuart0: serial@2260000 {
- compatible = "fsl,ls1021a-lpuart";
- reg = <0x0 0x2260000 0x0 0x1000>;
- interrupts = <0 232 0x4>;
- clocks = <&sysclk>;
- clock-names = "ipg";
- little-endian;
- status = "disabled";
- };
+ 0x00030000 0x00000010
+ 0x00030001 0x0000001c
+ 0x00030002 0x00000029
+ 0x00030003 0x00000036
+ 0x00030004 0x00000042
+ 0x00030005 0x0000004f
+ 0x00030006 0x0000005b
+ 0x00030007 0x00000068>;
+ little-endian;
+ #thermal-sensor-cells = <1>;
+ };
- lpuart1: serial@2270000 {
- compatible = "fsl,ls1021a-lpuart";
- reg = <0x0 0x2270000 0x0 0x1000>;
- interrupts = <0 233 0x4>;
- clocks = <&sysclk>;
- clock-names = "ipg";
- little-endian;
- status = "disabled";
- };
+ pcie@1f0000000 { /* Integrated Endpoint Root Complex */
+ compatible = "pci-host-ecam-generic";
+ reg = <0x01 0xf0000000 0x0 0x100000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ msi-parent = <&its>;
+ device_type = "pci";
+ bus-range = <0x0 0x0>;
+ dma-coherent;
+ msi-map = <0 &its 0x17 0xe>;
+ iommu-map = <0 &smmu 0x17 0xe>;
+ /* PF0-6 BAR0 - non-prefetchable memory */
+ ranges = <0x82000000 0x1 0xf8000000 0x1 0xf8000000 0x0 0x160000
+ /* PF0-6 BAR2 - prefetchable memory */
+ 0xc2000000 0x1 0xf8160000 0x1 0xf8160000 0x0 0x070000
+ /* PF0: VF0-1 BAR0 - non-prefetchable memory */
+ 0x82000000 0x1 0xf81d0000 0x1 0xf81d0000 0x0 0x020000
+ /* PF0: VF0-1 BAR2 - prefetchable memory */
+ 0xc2000000 0x1 0xf81f0000 0x1 0xf81f0000 0x0 0x020000
+ /* PF1: VF0-1 BAR0 - non-prefetchable memory */
+ 0x82000000 0x1 0xf8210000 0x1 0xf8210000 0x0 0x020000
+ /* PF1: VF0-1 BAR2 - prefetchable memory */
+ 0xc2000000 0x1 0xf8230000 0x1 0xf8230000 0x0 0x020000
+ /* BAR4 (PF5) - non-prefetchable memory */
+ 0x82000000 0x1 0xfc000000 0x1 0xfc000000 0x0 0x400000>;
- lpuart2: serial@2280000 {
- compatible = "fsl,ls1021a-lpuart";
- reg = <0x0 0x2280000 0x0 0x1000>;
- interrupts = <0 234 0x4>;
- clocks = <&sysclk>;
- clock-names = "ipg";
- little-endian;
- status = "disabled";
- };
+ enetc_port0: ethernet@0,0 {
+ compatible = "fsl,enetc";
+ reg = <0x000000 0 0 0 0>;
+ status = "disabled";
+ };
- lpuart3: serial@2290000 {
- compatible = "fsl,ls1021a-lpuart";
- reg = <0x0 0x2290000 0x0 0x1000>;
- interrupts = <0 235 0x4>;
- clocks = <&sysclk>;
- clock-names = "ipg";
- little-endian;
- status = "disabled";
- };
+ enetc_port1: ethernet@0,1 {
+ compatible = "fsl,enetc";
+ reg = <0x000100 0 0 0 0>;
+ status = "disabled";
+ };
- lpuart4: serial@22a0000 {
- compatible = "fsl,ls1021a-lpuart";
- reg = <0x0 0x22a0000 0x0 0x1000>;
- interrupts = <0 236 0x4>;
- clocks = <&sysclk>;
- clock-names = "ipg";
- little-endian;
- status = "disabled";
- };
+ enetc_port2: ethernet@0,2 {
+ compatible = "fsl,enetc";
+ reg = <0x000200 0 0 0 0>;
+ phy-mode = "internal";
+ status = "disabled";
- lpuart5: serial@22b0000 {
- compatible = "fsl,ls1021a-lpuart";
- reg = <0x0 0x22b0000 0x0 0x1000>;
- interrupts = <0 237 0x4>;
- clocks = <&sysclk>;
- clock-names = "ipg";
- little-endian;
- status = "disabled";
- };
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ };
+ };
- usb1: usb3@3100000 {
- compatible = "fsl,layerscape-dwc3";
- reg = <0x0 0x3100000 0x0 0x10000>;
- interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
- dr_mode = "host";
- status = "disabled";
- };
+ enetc_mdio_pf3: mdio@0,3 {
+ compatible = "fsl,enetc-mdio";
+ reg = <0x000300 0 0 0 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
- usb2: usb3@3110000 {
- compatible = "fsl,layerscape-dwc3";
- reg = <0x0 0x3110000 0x0 0x10000>;
- interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
- dr_mode = "host";
- status = "disabled";
- };
+ ethernet@0,4 {
+ compatible = "fsl,enetc-ptp";
+ reg = <0x000400 0 0 0 0>;
+ clocks = <&clockgen QORIQ_CLK_HWACCEL 3>;
+ little-endian;
+ fsl,extts-fifo;
+ };
- dspi0: dspi@2100000 {
- compatible = "fsl,vf610-dspi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0 0x2100000 0x0 0x10000>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "dspi";
- clocks = <&clockgen 4 0>;
- num-cs = <5>;
- litte-endian;
- status = "disabled";
- };
+ mscc_felix: ethernet-switch@0,5 {
+ reg = <0x000500 0 0 0 0>;
+ /* IEP INT_B */
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
- dspi1: dspi@2110000 {
- compatible = "fsl,vf610-dspi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0 0x2110000 0x0 0x10000>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "dspi";
- clocks = <&clockgen 4 0>;
- num-cs = <5>;
- little-endian;
- status = "disabled";
- };
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
- dspi2: dspi@2120000 {
- compatible = "fsl,vf610-dspi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0 0x2120000 0x0 0x10000>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "dspi";
- clocks = <&clockgen 4 0>;
- num-cs = <5>;
- little-endian;
- status = "disabled";
- };
+ /* External ports */
+ mscc_felix_port0: port@0 {
+ reg = <0>;
+ status = "disabled";
+ };
- esdhc0: esdhc@2140000 {
- compatible = "fsl,esdhc";
- reg = <0x0 0x2140000 0x0 0x10000>;
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- big-endian;
- bus-width = <4>;
- status = "disabled";
- };
+ mscc_felix_port1: port@1 {
+ reg = <1>;
+ status = "disabled";
+ };
- esdhc1: esdhc@2150000 {
- compatible = "fsl,esdhc";
- reg = <0x0 0x2150000 0x0 0x10000>;
- interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
- big-endian;
- non-removable;
- bus-width = <4>;
- status = "disabled";
- };
+ mscc_felix_port2: port@2 {
+ reg = <2>;
+ status = "disabled";
+ };
- gpio0: gpio@2300000 {
- compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
- reg = <0x0 0x2300000 0x0 0x10000>;
- interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- little-endian;
- };
+ mscc_felix_port3: port@3 {
+ reg = <3>;
+ status = "disabled";
+ };
- gpio1: gpio@2310000 {
- compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
- reg = <0x0 0x2310000 0x0 0x10000>;
- interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- little-endian;
- };
+ /* Internal ports */
+ mscc_felix_port4: port@4 {
+ reg = <4>;
+ phy-mode = "internal";
+ status = "disabled";
- gpio2: gpio@2320000 {
- compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
- reg = <0x0 0x2320000 0x0 0x10000>;
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- little-endian;
- };
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ };
+ };
+
+ mscc_felix_port5: port@5 {
+ reg = <5>;
+ phy-mode = "internal";
+ status = "disabled";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+ };
+
+ enetc_port3: ethernet@0,6 {
+ compatible = "fsl,enetc";
+ reg = <0x000600 0 0 0 0>;
+ phy-mode = "internal";
+ status = "disabled";
- sata: sata@3200000 {
- compatible = "fsl,ls1028a-ahci";
- reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
- 0x7 0x100520 0x0 0x4>; /* ecc sata addr*/
- reg-names = "sata-base", "ecc-addr";
- interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ rcec@1f,0 {
+ reg = <0x00f800 0 0 0 0>;
+ /* IEP INT_A */
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ /* Integrated Endpoint Register Block */
+ ierb@1f0800000 {
+ compatible = "fsl,ls1028a-enetc-ierb";
+ reg = <0x01 0xf0800000 0x0 0x10000>;
+ };
+
+ rcpm: power-controller@1e34040 {
+ compatible = "fsl,ls1028a-rcpm", "fsl,qoriq-rcpm-2.1+";
+ reg = <0x0 0x1e34040 0x0 0x1c>;
+ #fsl,rcpm-wakeup-cells = <7>;
+ little-endian;
+ };
+
+ ftm_alarm0: timer@2800000 {
+ compatible = "fsl,ls1028a-ftm-alarm";
+ reg = <0x0 0x2800000 0x0 0x10000>;
+ fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
- cluster1_core0_watchdog: wdt@c000000 {
- compatible = "arm,sp805-wdt";
- reg = <0x0 0xc000000 0x0 0x1000>;
+ malidp0: display@f080000 {
+ compatible = "arm,mali-dp500";
+ reg = <0x0 0xf080000 0x0 0x10000>;
+ interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
+ <0 223 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "DE", "SE";
+ clocks = <&dpclk>,
+ <&clockgen QORIQ_CLK_HWACCEL 2>,
+ <&clockgen QORIQ_CLK_HWACCEL 2>,
+ <&clockgen QORIQ_CLK_HWACCEL 2>;
+ clock-names = "pxlclk", "mclk", "aclk", "pclk";
+ arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
+ arm,malidp-arqos-value = <0xd000d000>;
+
+ port {
+ dp0_out: endpoint {
+
+ };
+ };
};
};
interrupts = <0 64 0x4>;
clock-names = "dspi";
clocks = <&clockgen 4 0>;
- num-cs = <6>;
+ spi-num-chipselects = <6>;
big-endian;
status = "disabled";
};
interrupts = <0 65 0x4>;
clock-names = "dspi";
clocks = <&clockgen 4 0>;
- num-cs = <6>;
+ spi-num-chipselects = <6>;
big-endian;
status = "disabled";
};
compatible = "fsl,ls1043a-ahci";
reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
0x0 0x20140520 0x0 0x4>; /* ecc sata addr*/
- reg-names = "sata-base", "ecc-addr";
+ reg-names = "ahci", "sata-ecc";
interrupts = <0 69 4>;
clocks = <&clockgen 4 0>;
status = "disabled";
interrupts = <0 64 0x4>;
clock-names = "dspi";
clocks = <&clockgen 4 0>;
- num-cs = <6>;
+ spi-num-chipselects = <6>;
big-endian;
status = "disabled";
};
interrupts = <0 65 0x4>;
clock-names = "dspi";
clocks = <&clockgen 4 0>;
- num-cs = <6>;
+ spi-num-chipselects = <6>;
big-endian;
status = "disabled";
};
compatible = "fsl,ls1046a-ahci";
reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
0x0 0x20140520 0x0 0x4>; /* ecc sata addr*/
- reg-names = "sata-base", "ecc-addr";
+ reg-names = "ahci", "sata-ecc";
interrupts = <0 69 4>;
clocks = <&clockgen 4 1>;
status = "disabled";
interrupts = <1 9 0x4>;
};
- gic_lpi_base: syscon@0x80000000 {
- compatible = "gic-lpi-base";
- reg = <0x0 0x80000000 0x0 0x100000>;
- max-gic-redistributors = <8>;
- };
-
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
#size-cells = <0>;
reg = <0x0 0x2100000 0x0 0x10000>;
interrupts = <0 26 0x4>; /* Level high type */
- num-cs = <6>;
+ spi-num-chipselects = <6>;
};
qspi: quadspi@1550000 {
reg = <0x0 0x20c0000 0x0 0x10000>,
<0x0 0x20000000 0x0 0x10000000>;
reg-names = "QuadSPI", "QuadSPI-memory";
- num-cs = <4>;
+ status = "disabled";
};
esdhc: esdhc@2140000 {
compatible = "fsl,ls1088a-ahci";
reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
0x7 0x100520 0x0 0x4>; /* ecc sata addr*/
- reg-names = "sata-base", "ecc-addr";
+ reg-names = "ahci", "sata-ecc";
interrupts = <0 133 4>;
status = "disabled";
};
interrupts = <1 9 0x4>;
};
- gic_lpi_base: syscon@0x80000000 {
- compatible = "gic-lpi-base";
- reg = <0x0 0x80000000 0x0 0x100000>;
- max-gic-redistributors = <8>;
- };
-
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
#size-cells = <0>;
reg = <0x0 0x2100000 0x0 0x10000>;
interrupts = <0 26 0x4>; /* Level high type */
- num-cs = <6>;
+ spi-num-chipselects = <6>;
};
qspi: quadspi@1550000 {
interrupts = <1 9 0x4>;
};
- gic_lpi_base: syscon@0x80000000 {
- compatible = "gic-lpi-base";
- reg = <0x0 0x80000000 0x0 0x200000>;
- max-gic-redistributors = <16>;
- };
-
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
#size-cells = <0>;
reg = <0x0 0x2100000 0x0 0x10000>;
interrupts = <0 26 0x4>; /* Level high type */
- num-cs = <6>;
+ spi-num-chipselects = <6>;
};
dspi1: dspi@2110000 {
#size-cells = <0>;
reg = <0x0 0x2110000 0x0 0x10000>;
interrupts = <0 26 0x4>; /* Level high type */
- num-cs = <6>;
+ spi-num-chipselects = <6>;
};
dspi2: dspi@2120000 {
#size-cells = <0>;
reg = <0x0 0x2120000 0x0 0x10000>;
interrupts = <0 241 0x4>; /* Level high type */
- num-cs = <6>;
+ spi-num-chipselects = <6>;
};
gpio0: gpio@2300000 {
};
watchdog0: watchdog@e8a06000 {
- compatible = "arm,sp805-wdt", "arm,primecell";
+ compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xe8a06000 0x0 0x1000>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg_ctrl HI3660_OSC32K>;
};
watchdog1: watchdog@e8a07000 {
- compatible = "arm,sp805-wdt", "arm,primecell";
+ compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xe8a07000 0x0 0x1000>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg_ctrl HI3660_OSC32K>;
soc {
u-boot,dm-pre-reloc;
- aips@50000000 {
+ bus@50000000 {
u-boot,dm-pre-reloc;
};
};
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1>;
+ broken-cd;
status = "okay";
};
clock-names = "core_clk", "mem_iface_clk";
};
- aips@50000000 { /* AIPS1 */
+ bus@50000000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
};
};
- aips@60000000 { /* AIPS2 */
+ bus@60000000 { /* AIPS2 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * Copyright 2020 Foundries.IO
+ */
+
+#include "imx6qdl-u-boot.dtsi"
+
+&wdog1 {
+ status = "okay";
+ u-boot,dm-spl;
+};
clocks = <&clks IMX6QDL_CLK_OCRAM>;
};
- aips1: aips-bus@2000000 {
+ aips1: bus@2000000 {
iomuxc: iomuxc@20e0000 {
compatible = "fsl,imx6dl-iomuxc";
};
};
};
- aips2: aips-bus@2100000 {
+ aips2: bus@2100000 {
i2c4: i2c@21f8000 {
#address-cells = <1>;
#size-cells = <0>;
soc {
u-boot,dm-pre-reloc;
- aips-bus@2100000 {
+ bus@2100000 {
u-boot,dm-pre-reloc;
};
};
clocks = <&clks IMX6QDL_CLK_OCRAM>;
};
- aips-bus@2000000 { /* AIPS1 */
+ bus@2000000 { /* AIPS1 */
spba-bus@2000000 {
ecspi5: spi@2018000 {
#address-cells = <1>;
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
- regulator-always-on;
+ gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
&usbh1 {
vbus-supply = <®_usb_h1_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh1>;
status = "okay";
};
>;
};
+ pinctrl_usbh1: usbh1grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
+ >;
+ };
+
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
- regulator-always-on;
+ gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
};
reg_usb_otg_vbus: regulator@3 {
&usbh1 {
vbus-supply = <®_usb_h1_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh1>;
status = "okay";
};
>;
};
+ pinctrl_usbh1: usbh1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
+ >;
+ };
+
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
+
+ reg_usb_h1_vbus: regulator-usbh1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_h1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
};
&gpmi {
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
- status = "okay"; };
+ status = "okay";
+};
&usbh1 {
+ vbus-supply = <®_usb_h1_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh1>;
status = "okay";
};
>;
};
+ pinctrl_usbh1: usbh1grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
+ >;
+ };
+
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x13059
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
- regulator-always-on;
+ gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
- regulator-always-on;
+ gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
&usbh1 {
vbus-supply = <®_usb_h1_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
status = "okay";
};
>;
};
+ pinctrl_usbh1: usbh1grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
+ >;
+ };
+
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
regulator-name = "usb_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
- regulator-always-on;
+ gpio = <&gpio4 5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
};
};
&usbh1 {
vbus-supply = <®_usb_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh1>;
status = "okay";
};
>;
};
+ pinctrl_usbh1: usbh1grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
+ >;
+ };
+
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059
u-boot,dm-spl;
u-boot,dm-pre-reloc;
- aips-bus@2000000 {
+ bus@2000000 {
u-boot,dm-spl;
spba-bus@2000000 {
u-boot,dm-spl;
};
};
- aips-bus@2100000 {
+ bus@2100000 {
u-boot,dm-spl;
};
};
status = "disabled";
};
- aips-bus@2000000 { /* AIPS1 */
+ bus@2000000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
};
};
- aips-bus@2100000 { /* AIPS2 */
+ bus@2100000 { /* AIPS2 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
clocks = <&clks IMX6QDL_CLK_OCRAM>;
};
- aips-bus@2100000 {
+ bus@2100000 {
pre1: pre@21c8000 {
compatible = "fsl,imx6qp-pre";
reg = <0x021c8000 0x1000>;
interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
};
- aips1: aips-bus@02000000 {
+ aips1: bus@02000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
};
};
- aips2: aips-bus@02100000 {
+ aips2: bus@02100000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
arm,data-latency = <4 2 3>;
};
- aips1: aips-bus@02000000 {
+ aips1: bus@02000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
};
};
- aips2: aips-bus@02100000 {
+ aips2: bus@02100000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
};
- aips1: aips-bus@2000000 {
+ aips1: bus@2000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
};
};
- aips2: aips-bus@2100000 {
+ aips2: bus@2100000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
};
};
- aips3: aips-bus@2200000 {
+ aips3: bus@2200000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ */
+
+#include "imx6ul-kontron-n6x1x-s-u-boot.dtsi"
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
+ */
+
+/dts-v1/;
+
+#include "imx6ul-kontron-n631x-som.dtsi"
+#include "imx6ul-kontron-n6x1x-s.dtsi"
+
+/ {
+ model = "Kontron N631X S";
+ compatible = "kontron,imx6ul-n631x-s", "kontron,imx6ul-n631x-som",
+ "fsl,imx6ul";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
+ */
+
+#include "imx6ul.dtsi"
+#include "imx6ul-kontron-n6x1x-som-common.dtsi"
+
+/ {
+ model = "Kontron N631X SOM";
+ compatible = "kontron,imx6ul-n631x-som", "fsl,imx6ul";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ */
+
+#if defined(CONFIG_FIT)
+
+/ {
+ binman: binman {
+ filename = "flash.bin";
+ pad-byte = <0x00>;
+
+ spl: blob-ext@1 {
+ offset = <0x0>;
+ filename = "SPL";
+ };
+
+ uboot: blob-ext@2 {
+ offset = <0x11000>;
+ filename = "u-boot.img";
+ };
+ };
+};
+
+#endif /* CONFIG_FIT */
+
+/*
+ * To make the PHYs work, we need to set the reset pin once. Afterwards
+ * in Linux we can't assign the shared reset GPIO to the PHYs, as this
+ * would cause Linux to reset both PHYs every time one of them gets
+ * reinitialized.
+ *
+ * Also we disable the second ethernet as it currently doesn't work with
+ * the devicetree setup in U-Boot.
+ */
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>;
+ phy-mode = "rmii";
+ phy-handle = <ðphy1>;
+ phy-reset-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@1 {
+ reg = <1>;
+ micrel,led-mode = <0>;
+ clocks = <&clks IMX6UL_CLK_ENET_REF>;
+ clock-names = "rmii-ref";
+ };
+ };
+};
+
+&fec2 {
+ status = "disabled";
+ /delete-property/ phy-handle;
+ /delete-node/ mdio;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include "imx6ul-kontron-n6x1x-som.dtsi"
+
+/ {
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led1 {
+ label = "debug-led1";
+ gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ linux,default-trigger = "heartbeat";
+ };
+
+ led2 {
+ label = "debug-led2";
+ gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led3 {
+ label = "debug-led3";
+ gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ };
+
+ pwm-beeper {
+ compatible = "pwm-beeper";
+ pwms = <&pwm8 0 5000>;
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_5v: regulator-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_vref_adc: regulator-vref-adc {
+ compatible = "regulator-fixed";
+ regulator-name = "vref-adc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&adc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc1>;
+ num-channels = <3>;
+ vref-supply = <®_vref_adc>;
+ status = "okay";
+};
+
+&can2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ status = "okay";
+};
+
+&ecspi1 {
+ cs-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ status = "okay";
+
+ eeprom@0 {
+ compatible = "anvo,anv32e61w", "atmel,at25";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ spi-cpha;
+ spi-cpol;
+ pagesize = <1>;
+ size = <8192>;
+ address-width = <16>;
+ };
+};
+
+&fec1 {
+ pinctrl-0 = <&pinctrl_enet1>;
+ /delete-node/ mdio;
+};
+
+&fec2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>;
+ phy-mode = "rmii";
+ phy-handle = <ðphy2>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@1 {
+ reg = <1>;
+ micrel,led-mode = <0>;
+ clocks = <&clks IMX6UL_CLK_ENET_REF>;
+ clock-names = "rmii-ref";
+ };
+
+ ethphy2: ethernet-phy@2 {
+ reg = <2>;
+ micrel,led-mode = <0>;
+ clocks = <&clks IMX6UL_CLK_ENET2_REF>;
+ clock-names = "rmii-ref";
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+};
+
+&i2c4 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ status = "okay";
+
+ rtc@32 {
+ compatible = "epson,rx8900";
+ reg = <0x32>;
+ };
+};
+
+&pwm8 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm8>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ linux,rs485-enabled-at-boot-time;
+ rs485-rx-during-tx;
+ rs485-rts-active-low;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ fsl,uart-has-rtscts;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ status = "okay";
+};
+
+&usbotg1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1>;
+ dr_mode = "otg";
+ srp-disable;
+ hnp-disable;
+ adp-disable;
+ over-current-active-low;
+ vbus-supply = <®_usb_otg1_vbus>;
+ status = "okay";
+};
+
+&usbotg2 {
+ dr_mode = "host";
+ disable-over-current;
+ vbus-supply = <®_5v>;
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
+ keep-power-in-suspend;
+ wakeup-source;
+ vmmc-supply = <®_3v3>;
+ voltage-ranges = <3300 3300>;
+ bus-width = <4>;
+ no-1-8-v;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+ non-removable;
+ keep-power-in-suspend;
+ wakeup-source;
+ vmmc-supply = <®_3v3>;
+ voltage-ranges = <3300 3300>;
+ bus-width = <4>;
+ no-1-8-v;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>;
+
+ pinctrl_adc1: adc1grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
+ MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
+ MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0xb0
+ >;
+ };
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x100b1
+ MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x100b1
+ MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x100b1
+ MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x100b1 /* ECSPI1-CS1 */
+ >;
+ };
+
+ pinctrl_enet2: enet2grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
+ MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
+ MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
+ MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
+ MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
+ MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
+ MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
+ MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b009
+ >;
+ };
+
+ pinctrl_enet2_mdio: enet2mdiogrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
+ MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp{
+ fsl,pins = <
+ MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
+ MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
+ >;
+ };
+
+ pinctrl_gpio: gpiogrp {
+ fsl,pins = <
+ MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* DOUT1 */
+ MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */
+ MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */
+ MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */
+ >;
+ };
+
+ pinctrl_gpio_leds: gpioledsgrp {
+ fsl,pins = <
+ MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b0b0 /* LED H14 */
+ MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* LED H15 */
+ MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* LED H16 */
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0
+ MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001f8b0
+ MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001f8b0
+ >;
+ };
+
+ pinctrl_pwm8: pwm8grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x110b0
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x1b0b1
+ MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x1b0b1
+ MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x1b0b1
+ /*
+ * mux unused RTS to make sure it doesn't cause
+ * any interrupts when it is undefined
+ */
+ MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
+ MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1
+ MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbotg1: usbotg1 {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b0b0
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
+ MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x100b1 /* SD1_CD */
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x30b0
+ >;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led1 {
+ label = "debug-led1";
+ gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ linux,default-trigger = "heartbeat";
+ };
+
+ led2 {
+ label = "debug-led2";
+ gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led3 {
+ label = "debug-led3";
+ gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ };
+
+ pwm-beeper {
+ compatible = "pwm-beeper";
+ pwms = <&pwm8 0 5000>;
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_5v: regulator-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_vref_adc: regulator-vref-adc {
+ compatible = "regulator-fixed";
+ regulator-name = "vref-adc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&adc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc1>;
+ num-channels = <3>;
+ vref-supply = <®_vref_adc>;
+ status = "okay";
+};
+
+&can2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ status = "okay";
+};
+
+&ecspi1 {
+ cs-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ status = "okay";
+
+ eeprom@0 {
+ compatible = "anvo,anv32e61w", "atmel,at25";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ spi-cpha;
+ spi-cpol;
+ pagesize = <1>;
+ size = <8192>;
+ address-width = <16>;
+ };
+};
+
+&fec1 {
+ pinctrl-0 = <&pinctrl_enet1>;
+ /delete-node/ mdio;
+};
+
+&fec2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>;
+ phy-mode = "rmii";
+ phy-handle = <ðphy2>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@1 {
+ reg = <1>;
+ micrel,led-mode = <0>;
+ clocks = <&clks IMX6UL_CLK_ENET_REF>;
+ clock-names = "rmii-ref";
+ };
+
+ ethphy2: ethernet-phy@2 {
+ reg = <2>;
+ micrel,led-mode = <0>;
+ clocks = <&clks IMX6UL_CLK_ENET2_REF>;
+ clock-names = "rmii-ref";
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+};
+
+&i2c4 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ status = "okay";
+
+ rtc@32 {
+ compatible = "epson,rx8900";
+ reg = <0x32>;
+ };
+};
+
+&pwm8 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm8>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ linux,rs485-enabled-at-boot-time;
+ rs485-rx-during-tx;
+ rs485-rts-active-low;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ fsl,uart-has-rtscts;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ status = "okay";
+};
+
+&usbotg1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1>;
+ dr_mode = "otg";
+ srp-disable;
+ hnp-disable;
+ adp-disable;
+ over-current-active-low;
+ vbus-supply = <®_usb_otg1_vbus>;
+ status = "okay";
+};
+
+&usbotg2 {
+ dr_mode = "host";
+ disable-over-current;
+ vbus-supply = <®_5v>;
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
+ keep-power-in-suspend;
+ wakeup-source;
+ vmmc-supply = <®_3v3>;
+ voltage-ranges = <3300 3300>;
+ bus-width = <4>;
+ no-1-8-v;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+ non-removable;
+ keep-power-in-suspend;
+ wakeup-source;
+ vmmc-supply = <®_3v3>;
+ voltage-ranges = <3300 3300>;
+ bus-width = <4>;
+ no-1-8-v;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>;
+
+ pinctrl_adc1: adc1grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
+ MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
+ MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0xb0
+ >;
+ };
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x100b1
+ MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x100b1
+ MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x100b1
+ MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x100b1 /* ECSPI1-CS1 */
+ >;
+ };
+
+ pinctrl_enet2: enet2grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
+ MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
+ MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
+ MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
+ MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
+ MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
+ MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
+ MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b009
+ >;
+ };
+
+ pinctrl_enet2_mdio: enet2mdiogrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
+ MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp{
+ fsl,pins = <
+ MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
+ MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
+ >;
+ };
+
+ pinctrl_gpio: gpiogrp {
+ fsl,pins = <
+ MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* DOUT1 */
+ MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */
+ MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */
+ MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */
+ >;
+ };
+
+ pinctrl_gpio_leds: gpioledsgrp {
+ fsl,pins = <
+ MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b0b0 /* LED H14 */
+ MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* LED H15 */
+ MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* LED H16 */
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0
+ MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001f8b0
+ MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001f8b0
+ >;
+ };
+
+ pinctrl_pwm8: pwm8grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x110b0
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x1b0b1
+ MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x1b0b1
+ MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x1b0b1
+ /*
+ * mux unused RTS to make sure it doesn't cause
+ * any interrupts when it is undefined
+ */
+ MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
+ MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1
+ MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbotg1: usbotg1 {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b0b0
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
+ MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x100b1 /* SD1_CD */
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x30b0
+ >;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ chosen {
+ stdout-path = &uart4;
+ };
+
+ memory@80000000 {
+ reg = <0x80000000 0x10000000>;
+ device_type = "memory";
+ };
+};
+
+&ecspi2 {
+ cs-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi2>;
+ status = "okay";
+
+ spi-flash@0 {
+ compatible = "mxicy,mx25v8035f", "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>;
+ phy-mode = "rmii";
+ phy-handle = <ðphy1>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@1 {
+ reg = <1>;
+ micrel,led-mode = <0>;
+ clocks = <&clks IMX6UL_CLK_ENET_REF>;
+ clock-names = "rmii-ref";
+ };
+ };
+};
+
+&fec2 {
+ phy-mode = "rmii";
+ status = "disabled";
+};
+
+&qspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi>;
+ status = "okay";
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-nand";
+ spi-max-frequency = <104000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ reg = <0>;
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reset_out>;
+
+ pinctrl_ecspi2: ecspi2grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x100b1
+ MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x100b1
+ MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x100b1
+ MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x100b1
+ >;
+ };
+
+ pinctrl_enet1: enet1grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
+ MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
+ MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
+ MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b009
+ >;
+ };
+
+ pinctrl_enet1_mdio: enet1mdiogrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
+ MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
+ >;
+ };
+
+ pinctrl_qspi: qspigrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
+ MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
+ MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
+ MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
+ MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
+ MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
+ >;
+ };
+
+ pinctrl_reset_out: rstoutgrp {
+ fsl,pins = <
+ MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0
+ >;
+ };
+};
status = "disabled";
};
- aips1: aips-bus@2000000 {
+ aips1: bus@2000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
};
};
- aips2: aips-bus@2100000 {
+ aips2: bus@2100000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021 Toradex AG
+ */
+
+#include "imx6ull-colibri.dtsi"
+#include "imx6ull-colibri-u-boot.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6ULL 1GB (eMMC)";
+ compatible = "toradex,colibri-imx6ull-emmc", "toradex,colibri-imx6ull", "fsl,imx6ull";
+
+ aliases {
+ mmc0 = &usdhc2;
+ mmc1 = &usdhc1;
+ };
+};
+
+/* eMMC */
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2emmc>;
+ assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>;
+ assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
+ assigned-clock-rates = <0>, <198000000>;
+ bus-width = <8>;
+ keep-power-in-suspend;
+ no-1-8-v;
+ non-removable;
+ vmmc-supply = <®_module_3v3>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_usdhc2emmc: usdhc2emmcgrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
+ >;
+ };
+};
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Copyright 2018-2019 Toradex AG
+ * Copyright 2018-2021 Toradex AG
*/
#include "imx6ull-colibri.dtsi"
model = "Toradex Colibri iMX6ULL";
compatible = "toradex,colibri-imx6ull", "fsl,imx6ull";
};
+
+/* NAND */
+&gpmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpmi_nand>;
+ nand-on-flash-bbt;
+ nand-ecc-mode = "hw";
+ nand-ecc-strength = <8>;
+ nand-ecc-step-size = <512>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_gpmi_nand: gpmi-nand-grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x100a9
+ MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x100a9
+ MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x100a9
+ MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x100a9
+ MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x100a9
+ MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x100a9
+ MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x100a9
+ MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x100a9
+ MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x100a9
+ MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x100a9
+ MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x100a9
+ MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x100a9
+ MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x100a9
+ MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x100a9
+ >;
+ };
+};
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Copyright 2019 Toradex AG
+ * Copyright 2019-2021 Toradex AG
*/
/dts-v1/;
};
};
-/* NAND */
-&gpmi {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpmi_nand>;
- nand-on-flash-bbt;
- nand-ecc-mode = "hw";
- nand-ecc-strength = <8>;
- nand-ecc-step-size = <512>;
- status = "okay";
-};
-
/*
* I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
*/
>;
};
- pinctrl_gpmi_nand: gpmi-nand-grp {
- fsl,pins = <
- MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x100a9
- MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x100a9
- MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x100a9
- MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x100a9
- MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x100a9
- MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x100a9
- MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x100a9
- MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x100a9
- MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x100a9
- MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x100a9
- MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x100a9
- MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x100a9
- MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x100a9
- MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x100a9
- >;
- };
-
pinctrl_i2c1: i2c1-grp {
fsl,pins = <
MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ */
+
+#include "imx6ul-kontron-n6x1x-s-u-boot.dtsi"
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (C) 2019 Kontron Electronics GmbH
+ */
+
+/dts-v1/;
+
+#include "imx6ull-kontron-n641x-som.dtsi"
+#include "imx6ul-kontron-n6x1x-s.dtsi"
+
+/ {
+ model = "Kontron N641X S";
+ compatible = "kontron,imx6ull-n641x-s", "kontron,imx6ull-n641x-som",
+ "fsl,imx6ull";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ */
+
+#include "imx6ull.dtsi"
+#include "imx6ul-kontron-n6x1x-som-common.dtsi"
+
+/ {
+ model = "Kontron N641X SOM";
+ compatible = "kontron,imx6ull-n641x-som", "fsl,imx6ull";
+};
/ {
soc {
- aips3: aips-bus@2200000 {
+ aips3: bus@2200000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
<0x31006000 0x2000>;
};
- aips1: aips-bus@30000000 {
+ aips1: bus@30000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
};
};
- aips2: aips-bus@30400000 {
+ aips2: bus@30400000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
};
};
- aips3: aips-bus@30800000 {
+ aips3: bus@30800000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+/ {
+ binman: binman {
+ multiple-images;
+ };
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog1>;
+ u-boot,dm-spl;
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+};
+
+&{/soc@0} {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+&clk {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ assigned-clock-rates;
+};
+
+&osc_24m {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&aips1 {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&aips2 {
+ u-boot,dm-spl;
+};
+
+&aips3 {
+ u-boot,dm-spl;
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+};
+
+&pinctrl_uart3 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_gpio {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+ u-boot,dm-spl;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&gpio5 {
+ u-boot,dm-spl;
+};
+
+&uart3 {
+ u-boot,dm-spl;
+};
+
+&usdhc1 {
+ u-boot,dm-spl;
+};
+
+&usdhc2 {
+ u-boot,dm-spl;
+};
+
+&usdhc3 {
+ u-boot,dm-spl;
+};
+
+&i2c1 {
+ u-boot,dm-spl;
+};
+
+&i2c2 {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b} {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b/regulators} {
+ u-boot,dm-spl;
+};
+
+&pinctrl_i2c2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_pmic {
+ u-boot,dm-spl;
+};
+
+&fec1 {
+ phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+};
+
+&wdog1 {
+ u-boot,dm-spl;
+};
+
+&binman {
+ u-boot-spl-ddr {
+ filename = "u-boot-spl-ddr.bin";
+ pad-byte = <0xff>;
+ align-size = <4>;
+ align = <4>;
+
+ u-boot-spl {
+ align-end = <4>;
+ };
+
+ blob_1: blob-ext@1 {
+ filename = "lpddr4_pmu_train_1d_imem.bin";
+ size = <0x8000>;
+ };
+
+ blob_2: blob-ext@2 {
+ filename = "lpddr4_pmu_train_1d_dmem.bin";
+ size = <0x4000>;
+ };
+
+ blob_3: blob-ext@3 {
+ filename = "lpddr4_pmu_train_2d_imem.bin";
+ size = <0x8000>;
+ };
+
+ blob_4: blob-ext@4 {
+ filename = "lpddr4_pmu_train_2d_dmem.bin";
+ size = <0x4000>;
+ };
+ };
+
+ flash {
+ mkimage {
+ args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000";
+
+ blob {
+ filename = "u-boot-spl-ddr.bin";
+ };
+ };
+ };
+
+ itb {
+ filename = "u-boot.itb";
+
+ fit {
+ description = "Configuration to load ATF before U-Boot";
+ #address-cells = <1>;
+ fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
+
+ images {
+ uboot {
+ description = "U-Boot (64-bit)";
+ type = "standalone";
+ arch = "arm64";
+ compression = "none";
+ load = <CONFIG_SYS_TEXT_BASE>;
+
+ uboot_blob: blob-ext {
+ filename = "u-boot-nodtb.bin";
+ };
+ };
+
+ atf {
+ description = "ARM Trusted Firmware";
+ type = "firmware";
+ arch = "arm64";
+ compression = "none";
+ load = <0x920000>;
+ entry = <0x920000>;
+
+ atf_blob: blob-ext {
+ filename = "bl2.bin";
+ };
+ };
+
+ fip {
+ description = "Trusted Firmware FIP";
+ type = "firmware";
+ arch = "arm64";
+ compression = "none";
+ load = <0x40310000>;
+
+ fip_blob: blob-ext{
+ filename = "fip.bin";
+ };
+ };
+
+ fdt {
+ description = "NAME";
+ type = "flat_dt";
+ compression = "none";
+
+ uboot_fdt_blob: blob-ext {
+ filename = "u-boot.dtb";
+ };
+ };
+ };
+
+ configurations {
+ default = "conf";
+
+ conf {
+ description = "NAME";
+ firmware = "uboot";
+ loadables = "atf", "fip";
+ fdt = "fdt";
+ };
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ */
+
+#include "imx8mm-cl-iot-gate.dts"
};
};
- fip {
- description = "Trusted Firmware FIP";
- type = "firmware";
- arch = "arm64";
- compression = "none";
- load = <0x40310000>;
-
- fip_blob: blob-ext{
- filename = "fip.bin";
- };
- };
-
fdt {
description = "NAME";
type = "flat_dt";
conf {
description = "NAME";
firmware = "uboot";
- loadables = "atf", "fip";
+ loadables = "atf";
fdt = "fdt";
};
};
};
- flash {
+ spl {
+ filename = "spl.bin";
+
mkimage {
args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000";
};
};
};
+
+ imx-boot {
+ filename = "flash.bin";
+ pad-byte = <0x00>;
+
+ spl: blob-ext@1 {
+ offset = <0x0>;
+ filename = "spl.bin";
+ };
+
+ uboot: blob-ext@2 {
+ offset = <0x57c00>;
+ filename = "u-boot.itb";
+ };
+ };
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Kontron Electronics GmbH
+ */
+
+#include "imx8mm-kontron-n801x-s.dts"
+
+/ {
+ model = "Kontron i.MX8MM N801X S LVDS";
+ compatible = "kontron,imx8mm-n801x-s-lvds", "fsl,imx8mm";
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm1 0 50000>; /* period = 5000000 ns => f = 200 Hz */
+ power-supply = <®_vdd_24v>;
+ brightness-levels = <0 100>;
+ num-interpolated-steps = <100>;
+ default-brightness-level = <100>;
+ status = "okay";
+ };
+
+ reg_panel_pwr: regpanel-pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "reg_panel_pwr";
+ regulator-always-on;
+ gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_panel_rst: regpanel-rst {
+ compatible = "regulator-fixed";
+ regulator-name = "reg_panel_rst";
+ regulator-always-on;
+ gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_panel_stby: regpanel-stby {
+ compatible = "regulator-fixed";
+ regulator-name = "reg_panel_stby";
+ regulator-always-on;
+ gpio = <&gpio3 21 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_panel_hinv: regpanel-hinv {
+ compatible = "regulator-fixed";
+ regulator-name = "reg_panel_hinv";
+ regulator-always-on;
+ gpio = <&gpio3 24 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_panel_vinv: regpanel-vinv {
+ compatible = "regulator-fixed";
+ regulator-name = "reg_panel_vinv";
+ gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_vdd_24v: regulator-24v {
+ compatible = "regulator-fixed";
+ regulator-name = "reg-vdd-24v";
+ regulator-min-microvolt = <24000000>;
+ regulator-max-microvolt = <24000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ status = "okay";
+ };
+};
+
+&i2c2 {
+ status = "okay";
+
+ gt911@5d {
+ compatible = "goodix,gt928";
+ reg = <0x5d>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_touch>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <22 8>;
+ reset-gpios = <&gpio3 23 0>;
+ irq-gpios = <&gpio3 22 0>;
+ };
+};
+
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_panel: panelgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x19 /* TFT-PWR - family */
+ MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19 /* RESET family */
+ MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 /* STBY family */
+ MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x19 /* HINV panel */
+ MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 /* VINV panel */
+ >;
+ };
+
+ pinctrl_pwm1: pwm1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x6
+ >;
+ };
+
+ pinctrl_touch: touchgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19 /* Touch Interrupt */
+ MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19 /* Touch Reset */
+ >;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Kontron Electronics GmbH
+ */
+
+#include "imx8mm-u-boot.dtsi"
+
+/ {
+ aliases {
+ usb0 = &usbotg1;
+ usb1 = &usbotg2;
+ };
+
+ binman: binman {
+ multiple-images;
+ };
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog1>;
+ u-boot,dm-spl;
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+};
+
+&fec1 {
+ phy-mode = "rgmii-rxid";
+};
+
+&i2c1 {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&i2c2 {
+ status = "okay";
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_ecspi1 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_i2c1 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_pmic {
+ u-boot,dm-spl;
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141
+ /* Disable Pullup for SD_VSEL */
+ MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x41
+ >;
+};
+
+&pinctrl_uart3 {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_usdhc1 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1_100mhz {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1_200mhz {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+ u-boot,dm-spl;
+};
+
+&pca9450 {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
+ u-boot,dm-spl;
+};
+
+&ecspi1 {
+ u-boot,dm-spl;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&gpio5 {
+ u-boot,dm-spl;
+};
+
+&uart3 {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&usdhc1 {
+ u-boot,dm-spl;
+};
+
+&usdhc2 {
+ u-boot,dm-spl;
+};
+
+&wdog1 {
+ u-boot,dm-spl;
+};
+
+&binman {
+ u-boot-spl-ddr {
+ filename = "u-boot-spl-ddr.bin";
+ pad-byte = <0xff>;
+ align-size = <4>;
+ align = <4>;
+
+ u-boot-spl {
+ align-end = <4>;
+ };
+
+ blob_1: blob-ext@1 {
+ filename = "lpddr4_pmu_train_1d_imem.bin";
+ size = <0x8000>;
+ };
+
+ blob_2: blob-ext@2 {
+ filename = "lpddr4_pmu_train_1d_dmem.bin";
+ size = <0x4000>;
+ };
+
+ blob_3: blob-ext@3 {
+ filename = "lpddr4_pmu_train_2d_imem.bin";
+ size = <0x8000>;
+ };
+
+ blob_4: blob-ext@4 {
+ filename = "lpddr4_pmu_train_2d_dmem.bin";
+ size = <0x4000>;
+ };
+ };
+
+ spl {
+ filename = "spl.bin";
+
+ mkimage {
+ args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000";
+
+ blob {
+ filename = "u-boot-spl-ddr.bin";
+ };
+ };
+ };
+
+ itb {
+ filename = "u-boot.itb";
+
+ fit {
+ description = "Configuration to load ATF before U-Boot";
+ #address-cells = <1>;
+ fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
+
+ images {
+ uboot {
+ description = "U-Boot (64-bit)";
+ type = "standalone";
+ arch = "arm64";
+ compression = "none";
+ load = <CONFIG_SYS_TEXT_BASE>;
+
+ uboot_blob: blob-ext {
+ filename = "u-boot-nodtb.bin";
+ };
+ };
+
+ atf {
+ description = "ARM Trusted Firmware";
+ type = "firmware";
+ arch = "arm64";
+ compression = "none";
+ load = <0x920000>;
+ entry = <0x920000>;
+
+ atf_blob: blob-ext {
+ filename = "bl31.bin";
+ };
+ };
+
+ fdt {
+ description = "NAME";
+ type = "flat_dt";
+ compression = "none";
+
+ uboot_fdt_blob: blob-ext {
+ filename = "u-boot.dtb";
+ };
+ };
+ };
+
+ configurations {
+ default = "conf";
+
+ conf {
+ description = "NAME";
+ firmware = "uboot";
+ loadables = "atf";
+ fdt = "fdt";
+ };
+ };
+ };
+ };
+
+ imx-boot {
+ filename = "flash.bin";
+ pad-byte = <0x00>;
+
+ spl: blob-ext@1 {
+ offset = <0x0>;
+ filename = "spl.bin";
+ };
+
+ uboot: blob-ext@2 {
+ offset = <0x57c00>;
+ filename = "u-boot.itb";
+ };
+ };
+
+ u-boot-update {
+ filename = "firmware-update.itb";
+
+ fit {
+ description = "Configuration for firmware update file";
+
+ images {
+ flash-bin {
+ description = "U-Boot flash image";
+ type = "firmware";
+ os = "u-boot";
+ arch = "arm";
+ compress = "none";
+ load = <0>; /* unused */
+
+ blob {
+ filename = "flash.bin";
+ };
+
+ };
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2019 Kontron Electronics GmbH
+ */
+
+/dts-v1/;
+
+#include "imx8mm-kontron-n801x-som.dtsi"
+#include <dt-bindings/net/mscc-phy-vsc8531.h>
+
+/ {
+ model = "Kontron i.MX8MM N801X S";
+ compatible = "kontron,imx8mm-n801x-s", "kontron,imx8mm-n801x-som", "fsl,imx8mm";
+
+ aliases {
+ ethernet1 = &usbnet;
+ };
+
+ /* fixed crystal dedicated to mcp2515 */
+ osc_can: clock-osc-can {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <16000000>;
+ clock-output-names = "osc-can";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_led>;
+
+ led1 {
+ label = "led1";
+ gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ led2 {
+ label = "led2";
+ gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
+ };
+
+ led3 {
+ label = "led3";
+ gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
+ };
+
+ led4 {
+ label = "led4";
+ gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
+ };
+
+ led5 {
+ label = "led5";
+ gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
+ };
+
+ led6 {
+ label = "led6";
+ gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ pwm-beeper {
+ compatible = "pwm-beeper";
+ pwms = <&pwm2 0 5000 0>;
+ };
+
+ reg_rst_eth2: regulator-rst-eth2 {
+ compatible = "regulator-fixed";
+ regulator-name = "rst-usb-eth2";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_eth2>;
+ gpio = <&gpio3 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ reg_vdd_5v: regulator-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+};
+
+&ecspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi2>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ can0: can@0 {
+ compatible = "microchip,mcp2515";
+ reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can>;
+ clocks = <&osc_can>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
+ spi-max-frequency = <10000000>;
+ vdd-supply = <®_vdd_3v3>;
+ xceiver-supply = <®_vdd_5v>;
+ };
+};
+
+&ecspi3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi3>;
+ cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-connection-type = "rgmii-rxid";
+ phy-handle = <ðphy>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy: ethernet-phy@0 {
+ compatible = "ethernet-phy-id0007.0570";
+ reg = <0>;
+ reset-assert-us = <100>;
+ reset-deassert-us = <100>;
+ reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>;
+ vsc8531,led-0-mode = <VSC8531_LINK_100_1000_ACTIVITY>;
+ vsc8531,led-1-mode = <VSC8531_LINK_ACTIVITY>;
+ vsc8531,led-0-combine-disable;
+ };
+ };
+};
+
+&gpio4 {
+ dsi_mux_sel: dsi_mux_sel {
+ gpio-hog;
+ gpios = <14 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "dsi-mux-sel";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_dsi_sel>;
+ };
+
+ dsi_mux_oe {
+ gpio-hog;
+ gpios = <15 GPIO_ACTIVE_LOW>;
+ output-high;
+ line-name = "dsi-mux-oe";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_dsi_oe>;
+ };
+};
+
+&i2c4 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ status = "okay";
+
+ rtc@32 {
+ compatible = "epson,rx8900";
+ reg = <0x32>;
+ };
+};
+
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm2>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ linux,rs485-enabled-at-boot-time;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&usbotg1 {
+ dr_mode = "otg";
+ over-current-active-low;
+ status = "okay";
+};
+
+&usbotg2 {
+ dr_mode = "host";
+ disable-over-current;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ usb1@1 {
+ compatible = "usb424,9514";
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usbnet: usbether@1 {
+ compatible = "usb424,ec00";
+ reg = <1>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ };
+ };
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+ vmmc-supply = <®_vdd_3v3>;
+ vqmmc-supply = <®_nvcc_sd>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio>;
+
+ pinctrl_can: cangrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19
+ >;
+ };
+
+ pinctrl_dsi_sel: dsiselgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x19
+ >;
+ };
+
+ pinctrl_dsi_oe: dsioegrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x19
+ >;
+ };
+
+ pinctrl_ecspi2: ecspi2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
+ MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
+ MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
+ MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19
+ >;
+ };
+
+ pinctrl_ecspi3: ecspi3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x82
+ MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x82
+ MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x82
+ MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x19
+ >;
+ };
+
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
+ MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+ MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19 /* PHY RST */
+ MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x19 /* ETH IRQ */
+ >;
+ };
+
+ pinctrl_gpio_led: gpioledgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
+ MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x19
+ MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x19
+ MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x19
+ MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x19
+ MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19
+ MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19
+ >;
+ };
+
+ pinctrl_gpio: gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19
+ MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
+ MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
+ MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19
+ MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19
+ MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19
+ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19
+ MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_pwm2: pwm2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140
+ MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x140
+ MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x140
+ MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x140
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140
+ MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140
+ MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140
+ MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140
+ >;
+ };
+
+ pinctrl_usb_eth2: usbeth2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
+ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
+ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
+ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
+ >;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2019 Kontron Electronics GmbH
+ */
+
+#include "imx8mm.dtsi"
+
+/ {
+ model = "Kontron i.MX8MM N801X SoM";
+ compatible = "kontron,imx8mm-n801x-som", "fsl,imx8mm";
+
+ memory@40000000 {
+ device_type = "memory";
+ /*
+ * There are multiple SoM flavors with different DDR sizes.
+ * The smallest is 1GB. For larger sizes the bootloader will
+ * update the reg property.
+ */
+ reg = <0x0 0x40000000 0 0x80000000>;
+ };
+
+ chosen {
+ stdout-path = &uart3;
+ };
+};
+
+&A53_0 {
+ cpu-supply = <®_vdd_arm>;
+};
+
+&A53_1 {
+ cpu-supply = <®_vdd_arm>;
+};
+
+&A53_2 {
+ cpu-supply = <®_vdd_arm>;
+};
+
+&A53_3 {
+ cpu-supply = <®_vdd_arm>;
+};
+
+&ddrc {
+ operating-points-v2 = <&ddrc_opp_table>;
+
+ ddrc_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-25M {
+ opp-hz = /bits/ 64 <25000000>;
+ };
+
+ opp-100M {
+ opp-hz = /bits/ 64 <100000000>;
+ };
+
+ opp-750M {
+ opp-hz = /bits/ 64 <750000000>;
+ };
+ };
+};
+
+&ecspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ spi-flash@0 {
+ compatible = "mxicy,mx25r1635f", "jedec,spi-nor";
+ spi-max-frequency = <80000000>;
+ reg = <0>;
+ };
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ pca9450: pmic@25 {
+ compatible = "nxp,pca9450a";
+ reg = <0x25>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+
+ regulators {
+ reg_vdd_soc: BUCK1 {
+ regulator-name = "buck1";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <850000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ nxp,dvs-run-voltage = <850000>;
+ nxp,dvs-standby-voltage = <800000>;
+ };
+
+ reg_vdd_arm: BUCK2 {
+ regulator-name = "buck2";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <950000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ nxp,dvs-run-voltage = <950000>;
+ nxp,dvs-standby-voltage = <850000>;
+ };
+
+ reg_vdd_dram: BUCK3 {
+ regulator-name = "buck3";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <950000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_vdd_3v3: BUCK4 {
+ regulator-name = "buck4";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_vdd_1v8: BUCK5 {
+ regulator-name = "buck5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_nvcc_dram: BUCK6 {
+ regulator-name = "buck6";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_nvcc_snvs: LDO1 {
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_vdd_snvs: LDO2 {
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_vdda: LDO3 {
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_vdd_phy: LDO4 {
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_nvcc_sd: LDO5 {
+ regulator-name = "ldo5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+ };
+};
+
+&uart3 { /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ vmmc-supply = <®_vdd_3v3>;
+ vqmmc-supply = <®_vdd_1v8>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
+ MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
+ MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
+ MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_pmic: pmicgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141
+ MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x141
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
+ MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
+ MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0
+ MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0
+ MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0
+ MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0
+ MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
+ MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
+ MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4
+ MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4
+ MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4
+ MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4
+ MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
+ MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
+ MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6
+ MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6
+ MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6
+ MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6
+ MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
+ MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+ >;
+ };
+};
* Copyright 2021 Gateworks Corporation
*/
-#include "imx8mm-u-boot.dtsi"
-
-&gpio1 {
- u-boot,dm-spl;
-};
-
-&gpio2 {
- u-boot,dm-spl;
-};
-
-&gpio3 {
- u-boot,dm-spl;
-};
-
-&gpio4 {
- u-boot,dm-spl;
-};
-
-&gpio5 {
- u-boot,dm-spl;
-};
-
-&uart2 {
- u-boot,dm-spl;
-};
-
-&pinctrl_uart2 {
- u-boot,dm-spl;
-};
-
-&usdhc3 {
- u-boot,dm-spl;
-};
-
-&pinctrl_usdhc3 {
- u-boot,dm-spl;
-};
-
-&i2c1 {
- u-boot,dm-spl;
-};
-
-&pinctrl_i2c1 {
- u-boot,dm-spl;
-};
-
-&i2c2 {
- u-boot,dm-spl;
-};
-
-&pinctrl_i2c2 {
- u-boot,dm-spl;
-};
+#include "imx8mm-venice-u-boot.dtsi"
&fec1 {
phy-reset-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
phy-reset-post-delay = <1>;
};
+&pinctrl_fec1 {
+ u-boot,dm-spl;
+};
+
&{/soc@0/bus@30800000/i2c@30a20000/pmic@69} {
u-boot,dm-spl;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@69/regulators} {
u-boot,dm-spl;
};
+
+&pinctrl_pmic {
+ u-boot,dm-spl;
+};
reg = <0x69>;
regulators {
+ /* vdd_0p95: DRAM/GPU/VPU */
buck1 {
- regulator-name = "vdd_0p95";
- regulator-min-microvolt = <805000>;
+ regulator-name = "buck1";
+ regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1000000>;
- regulator-max-microamp = <2500000>;
+ regulator-min-microamp = <3800000>;
+ regulator-max-microamp = <6800000>;
regulator-boot-on;
+ regulator-always-on;
};
+ /* vdd_soc */
buck2 {
- regulator-name = "vdd_soc";
- regulator-min-microvolt = <805000>;
+ regulator-name = "buck2";
+ regulator-min-microvolt = <800000>;
regulator-max-microvolt = <900000>;
- regulator-max-microamp = <1000000>;
+ regulator-min-microamp = <2200000>;
+ regulator-max-microamp = <5200000>;
regulator-boot-on;
+ regulator-always-on;
};
+ /* vdd_arm */
buck3_reg: buck3 {
- regulator-name = "vdd_arm";
- regulator-min-microvolt = <805000>;
+ regulator-name = "buck3";
+ regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1000000>;
- regulator-max-microamp = <2200000>;
- regulator-boot-on;
+ regulator-min-microamp = <3800000>;
+ regulator-max-microamp = <6800000>;
+ regulator-always-on;
};
+ /* vdd_1p8 */
buck4 {
- regulator-name = "vdd_1p8";
+ regulator-name = "buck4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
- regulator-max-microamp = <500000>;
+ regulator-min-microamp = <2200000>;
+ regulator-max-microamp = <5200000>;
regulator-boot-on;
+ regulator-always-on;
};
+ /* nvcc_snvs_1p8 */
ldo1 {
- regulator-name = "nvcc_snvs_1p8";
+ regulator-name = "ldo1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
- regulator-max-microamp = <300000>;
regulator-boot-on;
+ regulator-always-on;
};
+ /* vdd_snvs_0p8 */
ldo2 {
- regulator-name = "vdd_snvs_0p8";
+ regulator-name = "ldo2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-boot-on;
+ regulator-always-on;
};
+ /* vdd_0p9 */
ldo3 {
- regulator-name = "vdd_0p95";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <800000>;
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
regulator-boot-on;
+ regulator-always-on;
};
+ /* vdd_1p8 */
ldo4 {
- regulator-name = "vdd_1p8";
+ regulator-name = "ldo4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
+ regulator-always-on;
};
};
};
* Copyright 2020 Gateworks Corporation
*/
-#include "imx8mm-u-boot.dtsi"
-
-&gpio1 {
- u-boot,dm-spl;
-};
-
-&gpio2 {
- u-boot,dm-spl;
-};
-
-&gpio3 {
- u-boot,dm-spl;
-};
-
-&gpio4 {
- u-boot,dm-spl;
-};
-
-&gpio5 {
- u-boot,dm-spl;
-};
-
-&uart2 {
- u-boot,dm-spl;
-};
-
-&pinctrl_uart2 {
- u-boot,dm-spl;
-};
-
-&usdhc2 {
- u-boot,dm-spl;
-};
-
-&pinctrl_usdhc2 {
- u-boot,dm-spl;
-};
-
-&usdhc3 {
- u-boot,dm-spl;
-};
-
-&pinctrl_usdhc3 {
- u-boot,dm-spl;
-};
-
-&i2c1 {
- u-boot,dm-spl;
-};
-
-&pinctrl_i2c1 {
- u-boot,dm-spl;
-};
-
-&i2c2 {
- u-boot,dm-spl;
-};
-
-&pinctrl_i2c2 {
- u-boot,dm-spl;
-};
+#include "imx8mm-venice-u-boot.dtsi"
&fec1 {
phy-reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
phy-reset-post-delay = <1>;
};
+&pinctrl_fec1 {
+ u-boot,dm-spl;
+};
+
&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b} {
u-boot,dm-spl;
};
>;
};
};
-
-&cpu_alert0 {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "passive";
-};
-
-&cpu_crit0 {
- temperature = <105000>;
- hysteresis = <2000>;
- type = "critical";
-};
* Copyright 2021 Gateworks Corporation
*/
-#include "imx8mm-u-boot.dtsi"
-
-&gpio1 {
- u-boot,dm-spl;
-};
-
-&gpio2 {
- u-boot,dm-spl;
-};
-
-&gpio3 {
- u-boot,dm-spl;
-};
-
-&gpio4 {
- u-boot,dm-spl;
-};
-
-&gpio5 {
- u-boot,dm-spl;
-};
-
-&uart2 {
- u-boot,dm-spl;
-};
-
-&pinctrl_uart2 {
- u-boot,dm-spl;
-};
-
-&usdhc3 {
- u-boot,dm-spl;
-};
-
-&pinctrl_usdhc3 {
- u-boot,dm-spl;
-};
-
-&i2c1 {
- u-boot,dm-spl;
-};
-
-&pinctrl_i2c1 {
- u-boot,dm-spl;
-};
-
-&i2c2 {
- u-boot,dm-spl;
-};
-
-&pinctrl_i2c2 {
- u-boot,dm-spl;
-};
+#include "imx8mm-venice-u-boot.dtsi"
&fec1 {
phy-reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
>;
};
};
-
-&cpu_alert0 {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "passive";
-};
-
-&cpu_crit0 {
- temperature = <105000>;
- hysteresis = <2000>;
- type = "critical";
-};
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
- * Copyright 2020 Toradex
+ * Copyright 2020-2021 Toradex
*/
#include "imx8mm-u-boot.dtsi"
/ {
+ binman: binman {
+ multiple-images;
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+
wdt-reboot {
compatible = "wdt-reboot";
- wdt = <&wdog1>;
u-boot,dm-spl;
+ wdt = <&wdog1>;
};
};
+&{/soc@0/bus@30800000/i2c@30a20000/pmic} {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic/regulators} {
+ u-boot,dm-spl;
+};
+
&gpio1 {
u-boot,dm-spl;
};
u-boot,dm-spl;
};
-&{/soc@0/bus@30800000/i2c@30a20000/pmic} {
- u-boot,dm-spl;
-};
-
-&{/soc@0/bus@30800000/i2c@30a20000/pmic/regulators} {
+&pinctrl_wdog {
u-boot,dm-spl;
};
&wdog1 {
u-boot,dm-spl;
};
+
+&binman {
+ u-boot-spl-ddr {
+ filename = "u-boot-spl-ddr.bin";
+ pad-byte = <0xff>;
+ align-size = <4>;
+ align = <4>;
+
+ u-boot-spl {
+ align-end = <4>;
+ };
+
+ blob_1: blob-ext@1 {
+ filename = "lpddr4_pmu_train_1d_imem.bin";
+ size = <0x8000>;
+ };
+
+ blob_2: blob-ext@2 {
+ filename = "lpddr4_pmu_train_1d_dmem.bin";
+ size = <0x4000>;
+ };
+
+ blob_3: blob-ext@3 {
+ filename = "lpddr4_pmu_train_2d_imem.bin";
+ size = <0x8000>;
+ };
+
+ blob_4: blob-ext@4 {
+ filename = "lpddr4_pmu_train_2d_dmem.bin";
+ size = <0x4000>;
+ };
+ };
+
+ spl {
+ filename = "spl.bin";
+
+ mkimage {
+ args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000";
+
+ blob {
+ filename = "u-boot-spl-ddr.bin";
+ };
+ };
+ };
+
+ itb {
+ filename = "u-boot.itb";
+
+ fit {
+ description = "Configuration to load ATF before U-Boot";
+ #address-cells = <1>;
+ fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
+
+ images {
+ uboot {
+ description = "U-Boot (64-bit)";
+ type = "standalone";
+ arch = "arm64";
+ compression = "none";
+ load = <CONFIG_SYS_TEXT_BASE>;
+
+ uboot_blob: blob-ext {
+ filename = "u-boot-nodtb.bin";
+ };
+ };
+
+ atf {
+ description = "ARM Trusted Firmware";
+ type = "firmware";
+ arch = "arm64";
+ compression = "none";
+ load = <0x920000>;
+ entry = <0x920000>;
+
+ atf_blob: blob-ext {
+ filename = "bl31.bin";
+ };
+ };
+
+ fdt {
+ description = "NAME";
+ type = "flat_dt";
+ compression = "none";
+
+ uboot_fdt_blob: blob-ext {
+ filename = "u-boot.dtb";
+ };
+ };
+ };
+
+ configurations {
+ default = "conf";
+
+ conf {
+ description = "NAME";
+ firmware = "uboot";
+ loadables = "atf";
+ fdt = "fdt";
+ };
+ };
+ };
+ };
+
+ imx-boot {
+ filename = "flash.bin";
+ pad-byte = <0x00>;
+
+ spl: blob-ext@1 {
+ offset = <0x0>;
+ filename = "spl.bin";
+ };
+
+ uboot: blob-ext@2 {
+ offset = <0x5fc00>;
+ filename = "u-boot.itb";
+ };
+ };
+};
&fec1 {
fsl,magic-packet;
phy-handle = <ðphy0>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
phy-supply = <®_ethphy>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_fec1>;
};
};
+&gpio5 {
+ ctrl_sleep_moci {
+ gpio-hog;
+ /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
+ gpios = <1 GPIO_ACTIVE_HIGH>;
+ line-name = "CTRL_SLEEP_MOCI#";
+ output-high;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
+ };
+};
+
/* On-module I2C */
&i2c1 {
clock-frequency = <400000>;
>;
};
+ pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1c4 /* SODIMM 256 */
+ >;
+ };
+
pinctrl_dsi_bkl_en: dsi_bkl_en {
fsl,pins = <
MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x1c4 /* SODIMM 21 */
u-boot,dm-spl;
};
+&eqos {
+ compatible = "fsl,imx-eqos";
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ assigned-clock-rates;
+};
+
+ðphy0 {
+ reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <15000>;
+ reset-post-delay-us = <100000>;
+};
+
&fec {
phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
phy-reset-duration = <15>;
status = "okay";
};
+&eqos {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eqos>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy0>;
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ eee-broken-1000t;
+ };
+ };
+};
+
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
};
&iomuxc {
+ pinctrl_eqos: eqosgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
+ MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
+ MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
+ MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
+ MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
+ MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
+ MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
+ MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
+ MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
+ MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
+ MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
+ MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
+ MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
+ MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
+ MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x19
+ >;
+ };
+
pinctrl_fec: fecgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
&clk {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ assigned-clock-rates;
};
&osc_32k {
};
};
- flash {
+ spl {
+ filename = "spl.bin";
+
mkimage {
args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x920000";
};
};
};
+
+ imx-boot {
+ filename = "flash.bin";
+ pad-byte = <0x00>;
+
+ spl: blob-ext@1 {
+ filename = "spl.bin";
+ offset = <0x0>;
+ };
+
+ uboot: blob-ext@2 {
+ filename = "u-boot.itb";
+ offset = <0x58000>;
+ };
+ };
};
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "dspi";
clocks = <&platform_clk 1>;
- num-cs = <6>;
+ spi-num-chipselects = <6>;
big-endian;
status = "disabled";
};
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "dspi";
clocks = <&platform_clk 1>;
- num-cs = <6>;
+ spi-num-chipselects = <6>;
big-endian;
status = "disabled";
};
sata: sata@3200000 {
compatible = "fsl,ls1021a-ahci";
reg = <0x3200000 0x10000 0x20220520 0x4>;
- reg-names = "sata-base", "ecc-addr";
+ reg-names = "ahci", "sata-ecc";
interrupts = <0 101 4>;
status = "disabled";
};
#include "imx8mm-u-boot.dtsi"
/ {
+ binman: binman {
+ multiple-images;
+ };
+
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
u-boot,dm-spl;
};
+&pinctrl_wdog {
+ u-boot,dm-spl;
+};
+
&gpio1 {
u-boot,dm-spl;
};
&wdog1 {
u-boot,dm-spl;
};
+
+&binman {
+ u-boot-spl-ddr {
+ filename = "u-boot-spl-ddr.bin";
+ pad-byte = <0xff>;
+ align-size = <4>;
+ align = <4>;
+
+ u-boot-spl {
+ align-end = <4>;
+ };
+
+ blob_1: blob-ext@1 {
+ filename = "lpddr4_pmu_train_1d_imem.bin";
+ size = <0x8000>;
+ };
+
+ blob_2: blob-ext@2 {
+ filename = "lpddr4_pmu_train_1d_dmem.bin";
+ size = <0x4000>;
+ };
+
+ blob_3: blob-ext@3 {
+ filename = "lpddr4_pmu_train_2d_imem.bin";
+ size = <0x8000>;
+ };
+
+ blob_4: blob-ext@4 {
+ filename = "lpddr4_pmu_train_2d_dmem.bin";
+ size = <0x4000>;
+ };
+ };
+
+ spl {
+ filename = "spl.bin";
+
+ mkimage {
+ args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000";
+
+ blob {
+ filename = "u-boot-spl-ddr.bin";
+ };
+ };
+ };
+
+ itb {
+ filename = "u-boot.itb";
+
+ fit {
+ description = "Configuration to load ATF before U-Boot";
+ #address-cells = <1>;
+ fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
+
+ images {
+ uboot {
+ description = "U-Boot (64-bit)";
+ type = "standalone";
+ arch = "arm64";
+ compression = "none";
+ load = <CONFIG_SYS_TEXT_BASE>;
+
+ uboot_blob: blob-ext {
+ filename = "u-boot-nodtb.bin";
+ };
+ };
+
+ atf {
+ description = "ARM Trusted Firmware";
+ type = "firmware";
+ arch = "arm64";
+ compression = "none";
+ load = <0x920000>;
+ entry = <0x920000>;
+
+ atf_blob: blob-ext {
+ filename = "bl31.bin";
+ };
+ };
+
+ fdt {
+ description = "NAME";
+ type = "flat_dt";
+ compression = "none";
+
+ uboot_fdt_blob: blob-ext {
+ filename = "u-boot.dtb";
+ };
+ };
+ };
+
+ configurations {
+ default = "conf";
+
+ conf {
+ description = "NAME";
+ firmware = "uboot";
+ loadables = "atf";
+ fdt = "fdt";
+ };
+ };
+ };
+ };
+
+ imx-boot {
+ filename = "flash.bin";
+ pad-byte = <0x00>;
+
+ spl: blob-ext@1 {
+ filename = "spl.bin";
+ offset = <0x0>;
+ };
+
+ uboot: blob-ext@2 {
+ filename = "u-boot.itb";
+ offset = <0x57c00>;
+ };
+ };
+};
compatible = "phytec,imx8mm-phycore-som", "fsl,imx8mm";
chosen {
- stdout-patch = &uart3;
+ stdout-path = &uart3;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
};
};
+/* SPI nor flash */
+&flexspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexspi0>;
+ status = "okay";
+
+ flash0: norflash@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <80000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ };
+};
+
/* i2c eeprom */
&i2c1 {
clock-frequency = <400000>;
>;
};
+ pinctrl_flexspi0: flexspi0grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
+ MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
+ MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
+ MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
+ MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
+ MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
+ >;
+ };
+
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm SDM845 chip device tree source
+ *
+ * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
+ *
+ */
+
+/dts-v1/;
+
+#include "skeleton64.dtsi"
+
+/ {
+ soc: soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0xffffffff>;
+ compatible = "simple-bus";
+
+ gcc: clock-controller@100000 {
+ u-boot,dm-pre-reloc;
+ compatible = "qcom,gcc-sdm845";
+ reg = <0x100000 0x1f0000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ gpio_north: gpio_north@3900000 {
+ u-boot,dm-pre-reloc;
+ #gpio-cells = <2>;
+ compatible = "qcom,sdm845-pinctrl";
+ reg = <0x3900000 0x400000>;
+ gpio-count = <150>;
+ gpio-controller;
+ gpio-ranges = <&gpio_north 0 0 150>;
+ gpio-bank-name = "soc_north.";
+ };
+
+ tlmm_north: pinctrl_north@3900000 {
+ u-boot,dm-pre-reloc;
+ compatible = "qcom,tlmm-sdm845";
+ reg = <0x3900000 0x400000>;
+ gpio-count = <150>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&tlmm_north 0 0 150>;
+
+ /* DEBUG UART */
+ qup_uart9: qup-uart9-default {
+ pinmux {
+ pins = "GPIO_4", "GPIO_5";
+ function = "qup9";
+ };
+ };
+ };
+
+ debug_uart: serial@a84000 {
+ compatible = "qcom,msm-geni-uart";
+ reg = <0xa84000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk";
+ clocks = <&gcc 0x58>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart9>;
+ qcom,wrapper-core = <0x8a>;
+ status = "disabled";
+ };
+
+ spmi@c440000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0xc440000 0x1100>,
+ <0xc600000 0x2000000>,
+ <0xe600000 0x100000>;
+ reg-names = "cnfg", "core", "obsrvr";
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+
+ qcom,revid@100 {
+ compatible = "qcom,qpnp-revid";
+ reg = <0x100 0x100>;
+ };
+
+ pmic0: pm8998@0 {
+ compatible = "qcom,spmi-pmic";
+ reg = <0x0 0x1>;
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+
+ pm8998_pon: pm8998_pon@800 {
+ compatible = "qcom,pm8998-pwrkey";
+ reg = <0x800 0x100>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-bank-name = "pm8998_key.";
+ };
+
+ pm8998_gpios: pm8998_gpios@c000 {
+ compatible = "qcom,pm8998-gpio";
+ reg = <0xc000 0x1a00>;
+ gpio-controller;
+ gpio-count = <21>;
+ #gpio-cells = <2>;
+ gpio-bank-name = "pm8998.";
+ };
+ };
+
+ pmic1: pm8998@1 {
+ compatible = "qcom,spmi-pmic";
+ reg = <0x1 0x0>;
+ #address-cells = <0x2>;
+ #size-cells = <0x0>;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot addition to handle Samsung S9 SM-G9600 (starqltechn) pins
+ *
+ * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
+ *
+ */
+
+/
+{
+ soc {
+ u-boot,dm-pre-reloc;
+ gcc {
+ clock-controller@100000 {
+ u-boot,dm-pre-reloc;
+ };
+ serial@0xa84000 {
+ u-boot,dm-pre-reloc;
+ };
+ gpio_north@3900000 {
+ u-boot,dm-pre-reloc;
+ };
+ pinctrl@3900000 {
+ u-boot,dm-pre-reloc;
+ };
+ };
+ };
+};
+
+&pm8998_pon {
+ key_vol_down {
+ gpios = <&pm8998_pon 1 0>;
+ label = "key_vol_down";
+ };
+ key_power {
+ gpios = <&pm8998_pon 0 0>;
+ label = "key_power";
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Samsung S9 SM-G9600 (starqltechn) board device tree source
+ *
+ * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
+ *
+ */
+
+/dts-v1/;
+
+#include "sdm845.dtsi"
+
+/ {
+ model = "Samsung S9 (SM-G9600)";
+ compatible = "qcom,sdm845-mtp", "qcom,sdm845", "qcom,mtp";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen {
+ stdout-path = "serial0:921600n8";
+ };
+
+ aliases {
+ serial0 = &debug_uart;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x80000000 0 0xfe1bffff>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ soc: soc {
+ serial@0xa84000 {
+ status = "ok";
+ };
+
+ pinctrl@3900000 {
+ muic_i2c: muic_i2c {
+ pins = "GPIO_33", "GPIO_34";
+ drive-strength = <0x2>;
+ function = "gpio";
+ bias-disable;
+ };
+ };
+ };
+};
+
+#include "starqltechn-uboot.dtsi"
pinctrl1 = &pinctrl_z;
};
+ binman: binman {
+ multiple-images;
+ };
+
clocks {
u-boot,dm-pre-reloc;
};
resets = <&rcc UART8_R>;
};
+#if defined(CONFIG_STM32MP15x_STM32IMAGE)
+&binman {
+ u-boot-stm32 {
+ filename = "u-boot.stm32";
+ mkimage {
+ args = "-T stm32image -a 0xC0100000 -e 0xC0100000";
+ u-boot {
+ };
+ };
+ };
+};
+#endif
+
+#if defined(CONFIG_SPL)
+&binman {
+ spl-stm32 {
+ filename = "u-boot-spl.stm32";
+ mkimage {
+ args = "-T stm32image -a 0x2FFC2500 -e 0x2FFC2500";
+ u-boot-spl {
+ };
+ };
+ };
+};
+#endif
&m4_rproc {
memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
<&vdev0vring1>, <&vdev0buffer>;
- mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
- mbox-names = "vq0", "vq1", "shutdown";
+ mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
+ mbox-names = "vq0", "vq1", "shutdown", "detach";
interrupt-parent = <&exti>;
interrupts = <68 1>;
status = "okay";
};
};
-&gpiof {
- snor-nwp {
- gpio-hog;
- gpios = <7 0>;
- output-high;
- line-name = "spi-nor-nwp";
- };
-};
-
&i2c4 {
u-boot,dm-pre-reloc;
};
u-boot,dm-spl;
};
-&gpiof {
- snor-nwp {
- gpio-hog;
- gpios = <7 0>;
- output-high;
- line-name = "spi-nor-nwp";
- };
-};
-
&i2c4 {
u-boot,dm-pre-reloc;
};
cs42l51_tx_endpoint: endpoint@0 {
reg = <0>;
remote-endpoint = <&sai2a_endpoint>;
- frame-master;
- bitclock-master;
+ frame-master = <&cs42l51_tx_endpoint>;
+ bitclock-master = <&cs42l51_tx_endpoint>;
};
cs42l51_rx_endpoint: endpoint@1 {
reg = <1>;
remote-endpoint = <&sai2b_endpoint>;
- frame-master;
- bitclock-master;
+ frame-master = <&cs42l51_rx_endpoint>;
+ bitclock-master = <&cs42l51_rx_endpoint>;
};
};
};
&m4_rproc {
memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
<&vdev0vring1>, <&vdev0buffer>;
- mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
- mbox-names = "vq0", "vq1", "shutdown";
+ mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
+ mbox-names = "vq0", "vq1", "shutdown", "detach";
interrupt-parent = <&exti>;
interrupts = <68 1>;
status = "okay";
reg = <0x030090a0 0x20>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>;
- status = "disabled";
};
pio: pinctrl@300b000 {
/ {
aliases {
mmc0 = &mmc0;
+#if CONFIG_MMC_SUNXI_EXTRA_SLOT == 2
mmc1 = &mmc2;
+#endif
};
binman: binman {
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Apple Mac mini (M1, 2020)
+ *
+ * target-type: J274
+ *
+ * Copyright The Asahi Linux Contributors
+ */
+
+/dts-v1/;
+
+#include "t8103.dtsi"
+
+/ {
+ compatible = "apple,j274", "apple,t8103", "apple,arm-platform";
+ model = "Apple Mac mini (M1, 2020)";
+
+ aliases {
+ serial0 = &serial0;
+ ethernet0 = ð0;
+ wifi0 = &wifi0;
+ };
+
+ chosen {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ stdout-path = "serial0";
+
+ framebuffer0: framebuffer@0 {
+ compatible = "apple,simple-framebuffer", "simple-framebuffer";
+ reg = <0 0 0 0>; /* To be filled by loader */
+ /* Format properties will be added by loader */
+ status = "disabled";
+ };
+ };
+
+ memory@800000000 {
+ device_type = "memory";
+ reg = <0x8 0 0x2 0>; /* To be filled by loader */
+ };
+};
+
+&serial0 {
+ status = "okay";
+};
+
+&pcie0_dart_0 {
+ status = "okay";
+};
+
+&pcie0_dart_1 {
+ status = "okay";
+};
+
+&pcie0_dart_2 {
+ status = "okay";
+};
+
+&pcie0 {
+ status = "okay";
+
+ pci0: pci@0,0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ pwren-gpios = <&smc 13 0>;
+ reset-gpios = <&pinctrl_ap 152 0>;
+ max-link-speed = <2>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+
+ pci1: pci@1,0 {
+ device_type = "pci";
+ reg = <0x800 0x0 0x0 0x0 0x0>;
+ reset-gpios = <&pinctrl_ap 153 0>;
+ max-link-speed = <2>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+
+ pci2: pci@2,0 {
+ device_type = "pci";
+ reg = <0x1000 0x0 0x0 0x0 0x0>;
+ reset-gpios = <&pinctrl_ap 33 0>;
+ max-link-speed = <1>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+};
+
+&pci0 {
+ wifi0: network@0,0 {
+ reg = <0x10000 0x0 0x0 0x0 0x0>;
+ local-mac-address = [00 00 00 00 00 00];
+ };
+};
+
+&pci2 {
+ eth0: ethernet@0,0 {
+ reg = <0x30000 0x0 0x0 0x0 0x0>;
+ local-mac-address = [00 00 00 00 00 00];
+ };
+};
+
+&dwc3_0_dart_0 {
+ status = "okay";
+};
+
+&dwc3_0_dart_1 {
+ status = "okay";
+};
+
+&dwc3_0 {
+ status = "okay";
+};
+
+&dwc3_1_dart_0 {
+ status = "okay";
+};
+
+&dwc3_1_dart_1 {
+ status = "okay";
+};
+
+&dwc3_1 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Apple Macbook Pro (M1, 2020)
+ *
+ * target-type: J293
+ *
+ * Copyright The Asahi Linux Contributors
+ */
+
+/dts-v1/;
+
+#include "t8103.dtsi"
+
+/ {
+ compatible = "apple,j293", "apple,t8103", "apple,arm-platform";
+ model = "Apple Macbook Pro (M1, 2020)";
+
+ aliases {
+ serial0 = &serial0;
+ wifi0 = &wifi0;
+ };
+
+ chosen {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ stdout-path = "serial0";
+
+ framebuffer0: framebuffer@0 {
+ compatible = "apple,simple-framebuffer", "simple-framebuffer";
+ reg = <0 0 0 0>; /* To be filled by loader */
+ /* Format properties will be added by loader */
+ status = "disabled";
+ };
+ };
+
+ memory@800000000 {
+ device_type = "memory";
+ reg = <0x8 0 0x2 0>; /* To be filled by loader */
+ };
+};
+
+&serial0 {
+ status = "okay";
+};
+
+&pcie0_dart_0 {
+ status = "okay";
+};
+
+&pcie0 {
+ status = "okay";
+
+ pci0: pci@0,0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ pwren-gpios = <&smc 13 0>;
+ reset-gpios = <&pinctrl_ap 152 0>;
+ max-link-speed = <2>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+};
+
+&pci0 {
+ wifi0: network@0,0 {
+ reg = <0x10000 0x0 0x0 0x0 0x0>;
+ local-mac-address = [00 00 00 00 00 00];
+ };
+};
+
+&dwc3_0_dart_0 {
+ status = "okay";
+};
+
+&dwc3_0_dart_1 {
+ status = "okay";
+};
+
+&dwc3_0 {
+ status = "okay";
+};
+
+&dwc3_1_dart_0 {
+ status = "okay";
+};
+
+&dwc3_1_dart_1 {
+ status = "okay";
+};
+
+&dwc3_1 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Apple T8103 "M1" SoC
+ *
+ * Other names: H13G, "Tonga"
+ *
+ * Copyright The Asahi Linux Contributors
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/apple-aic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/apple.h>
+#include <dt-bindings/spmi/spmi.h>
+
+/ {
+ compatible = "apple,t8103", "apple,arm-platform";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "apple,icestorm";
+ device_type = "cpu";
+ reg = <0x0 0x0>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0>; /* To be filled by loader */
+ };
+
+ cpu1: cpu@1 {
+ compatible = "apple,icestorm";
+ device_type = "cpu";
+ reg = <0x0 0x1>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0>; /* To be filled by loader */
+ };
+
+ cpu2: cpu@2 {
+ compatible = "apple,icestorm";
+ device_type = "cpu";
+ reg = <0x0 0x2>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0>; /* To be filled by loader */
+ };
+
+ cpu3: cpu@3 {
+ compatible = "apple,icestorm";
+ device_type = "cpu";
+ reg = <0x0 0x3>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0>; /* To be filled by loader */
+ };
+
+ cpu4: cpu@10100 {
+ compatible = "apple,firestorm";
+ device_type = "cpu";
+ reg = <0x0 0x10100>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0>; /* To be filled by loader */
+ };
+
+ cpu5: cpu@10101 {
+ compatible = "apple,firestorm";
+ device_type = "cpu";
+ reg = <0x0 0x10101>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0>; /* To be filled by loader */
+ };
+
+ cpu6: cpu@10102 {
+ compatible = "apple,firestorm";
+ device_type = "cpu";
+ reg = <0x0 0x10102>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0>; /* To be filled by loader */
+ };
+
+ cpu7: cpu@10103 {
+ compatible = "apple,firestorm";
+ device_type = "cpu";
+ reg = <0x0 0x10103>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0>; /* To be filled by loader */
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&aic>;
+ interrupt-names = "hyp-phys", "hyp-virt", "phys", "virt";
+ interrupts = <AIC_FIQ AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_FIQ AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ clkref: clock-ref {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "clkref";
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ranges;
+ dma-ranges;
+ dma-coherent;
+ nonposted-mmio;
+
+ serial0: serial@235200000 {
+ compatible = "apple,s5l-uart";
+ reg = <0x2 0x35200000 0x0 0x1000>;
+ reg-io-width = <4>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 605 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clkref>, <&clkref>, <&clkref>;
+ clock-names = "uart", "clk_uart_baud0", "clk_uart_baud1";
+ power-domains = <&ps_uart0>;
+ status = "disabled";
+ };
+
+ serial2: serial@235208000 {
+ compatible = "apple,s5l-uart";
+ reg = <0x2 0x35208000 0x0 0x1000>;
+ reg-io-width = <4>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 607 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clkref>, <&clkref>, <&clkref>;
+ clock-names = "uart", "clk_uart_baud0", "clk_uart_baud1";
+ power-domains = <&ps_uart2>;
+ status = "disabled";
+ };
+
+ aic: interrupt-controller@23b100000 {
+ compatible = "apple,t8103-aic", "apple,aic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x2 0x3b100000 0x0 0x8000>;
+ };
+
+ pmgr: power-controller@23b700000 {
+ compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <0x2 0x3b700000 0x0 0x14000>;
+
+ ps_pcie_ref: power-controller@1a0 {
+ compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x1a0>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ apple,domain-name = "pcie_ref";
+ };
+
+ ps_imx: power-controller@1b8 {
+ compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x1b8>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ apple,domain-name = "imx";
+ apple,always-on;
+ };
+
+ ps_sio: power-controller@1c0 {
+ compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x1c0>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ apple,domain-name = "sio";
+ };
+
+ ps_uart_p: power-controller@220 {
+ compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x220>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ power-domains = <&ps_sio>;
+ apple,domain-name = "uart_p";
+ };
+
+ ps_uart0: power-controller@270 {
+ compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x270>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ power-domains = <&ps_uart_p>;
+ apple,domain-name = "uart0";
+ };
+
+ ps_uart1: power-controller@278 {
+ compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x278>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ apple,domain-name = "uart1";
+ power-domains = <&ps_uart_p>;
+ };
+
+ ps_uart2: power-controller@280 {
+ compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x280>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ apple,domain-name = "uart2";
+ power-domains = <&ps_uart_p>;
+ };
+
+ ps_uart3: power-controller@288 {
+ compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x288>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ apple,domain-name = "uart3";
+ power-domains = <&ps_uart_p>;
+ };
+
+ ps_apcie: power-controller@348 {
+ compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x348>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ apple,domain-name = "apcie";
+ power-domains = <&ps_imx>;
+ };
+
+ ps_apcie_gp: power-controller@3e8 {
+ compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x3e8>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ apple,domain-name = "apcie_gp";
+ power-domains = <&ps_apcie>;
+ };
+
+ ps_ans2: power-controller@3f0 {
+ compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x3f0>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ apple,domain-name = "ans2";
+ power-domains = <&ps_apcie_st>;
+ };
+
+ ps_apcie_st: power-controller@418 {
+ compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x418>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ apple,domain-name = "apcie_st";
+ power-domains = <&ps_apcie>;
+ };
+ };
+
+ pinctrl_ap: pinctrl@23c100000 {
+ compatible = "apple,t8103-pinctrl", "apple,pinctrl";
+ reg = <0x2 0x3c100000 0x0 0x100000>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_ap 0 0 212>;
+
+ interrupt-controller;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 190 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 191 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 192 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 193 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 194 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 195 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 196 IRQ_TYPE_LEVEL_HIGH>;
+
+ i2c0_pins: i2c0_pins {
+ pinmux = <APPLE_PINMUX(188, 1)>,
+ <APPLE_PINMUX(192, 1)>;
+ };
+
+ pcie_pins: pcie-pins {
+ pinmux = <APPLE_PINMUX(150, 1)>,
+ <APPLE_PINMUX(151, 1)>,
+ <APPLE_PINMUX(32, 1)>;
+ };
+ };
+
+ pinctrl_aop: pinctrl@24a820000 {
+ compatible = "apple,t8103-pinctrl", "apple,pinctrl";
+ reg = <0x2 0x4a820000 0x0 0x4000>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_aop 0 0 42>;
+
+ interrupt-controller;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 268 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 269 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 270 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 271 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 272 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 273 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 274 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pinctrl_nub: pinctrl@23d1f0000 {
+ compatible = "apple,t8103-pinctrl", "apple,pinctrl";
+ reg = <0x2 0x3d1f0000 0x0 0x4000>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_nub 0 0 23>;
+
+ interrupt-controller;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 330 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 331 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 332 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 333 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 334 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 335 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 336 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pinctrl_smc: pinctrl@23e820000 {
+ compatible = "apple,t8103-pinctrl", "apple,pinctrl";
+ reg = <0x2 0x3e820000 0x0 0x4000>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_smc 0 0 16>;
+
+ interrupt-controller;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 391 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 392 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 393 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 394 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 395 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 396 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 397 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ i2c0: i2c@20a110000 {
+ compatible = "apple,i2c-v0";
+ reg = <0x2 0x35010000 0x0 0x4000>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 627 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clkref>;
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+
+ hpm0: hpm@38 {
+ compatible = "ti,tps6598x";
+ reg = <0x38>;
+ };
+
+ hpm1: hpm@3f {
+ compatible = "ti,tps6598x";
+ reg = <0x3f>;
+ };
+ };
+
+ ans_mbox: mbox@277400000 {
+ compatible = "apple,iop-mailbox-m1";
+ reg = <0x2 0x77400000 0x0 0x20000>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 583 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 586 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&ps_ans2>;
+ #mbox-cells = <1>;
+ endpoints = <32>;
+ };
+
+ ans@27bcc0000 {
+ compatible = "apple,nvme-m1";
+ reg = <0x2 0x7bcc0000 0x0 0x40000>,
+ <0x2 0x7bc50000 0x0 0x4000>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 590 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&ps_apcie_st>;
+ mboxes = <&ans_mbox 32>;
+ };
+
+ pcie0_dart_0: iommu@681008000 {
+ compatible = "apple,t8103-dart", "apple,dart-m1";
+ reg = <0x6 0x81008000 0x0 0x4000>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 696 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ pcie0_dart_1: iommu@682008000 {
+ compatible = "apple,t8103-dart", "apple,dart-m1";
+ reg = <0x6 0x82008000 0x0 0x4000>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 699 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ pcie0_dart_2: iommu@683008000 {
+ compatible = "apple,t8103-dart", "apple,dart-m1";
+ reg = <0x6 0x83008000 0x0 0x4000>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 702 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ smc_mbox: mbox@23e400000 {
+ compatible = "apple,iop-mailbox-m1";
+ reg = <0x2 0x3e400000 0x0 0x20000>;
+ #mbox-cells = <1>;
+ endpoints = <32>;
+ };
+
+ smc: smc@23e050000 {
+ compatible = "apple,smc-m1";
+ reg = <0x2 0x3e050000 0x0 0x4000>;
+ mboxes = <&smc_mbox 32>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-13 = <0x00800000>;
+ };
+
+ pcie0: pcie@690000000 {
+ compatible = "apple,t8103-pcie", "apple,pcie";
+
+ reg = <0x6 0x90000000 0x0 0x1000000>,
+ <0x6 0x80000000 0x0 0x4000>,
+ <0x6 0x81000000 0x0 0x8000>,
+ <0x6 0x82000000 0x0 0x8000>,
+ <0x6 0x83000000 0x0 0x8000>;
+ reg-names = "config", "rc", "port0", "port1", "port2";
+
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 695 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 698 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 701 IRQ_TYPE_LEVEL_HIGH>;
+
+ msi-controller;
+ msi-parent = <&pcie0>;
+ msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>;
+
+ iommu-map = <0x100 &pcie0_dart_0 1 1>,
+ <0x200 &pcie0_dart_1 1 1>,
+ <0x300 &pcie0_dart_2 1 1>;
+ iommu-map-mask = <0xff00>;
+
+ bus-range = <0 3>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000
+ 0x0 0x20000000>,
+ <0x02000000 0x0 0xc0000000 0x6 0xc0000000
+ 0x0 0x40000000>;
+
+ power-domains = <&ps_apcie>, <&ps_apcie_gp>, <&ps_pcie_ref>;
+ pinctrl-0 = <&pcie_pins>;
+ pinctrl-names = "default";
+
+ device_type = "pci";
+ status = "disabled";
+ };
+
+ dwc3_0_dart_0: iommu@382f00000 {
+ compatible = "apple,t8103-dart";
+ reg = <0x3 0x82f00000 0x0 0x4000>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 781 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ dwc3_0_dart_1: iommu@382f80000 {
+ compatible = "apple,t8103-dart";
+ reg = <0x3 0x82f80000 0x0 0x4000>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 781 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ dwc3_0: usb@382280000{
+ compatible = "snps,dwc3";
+ reg = <0x3 0x82280000 0x0 0x100000>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 777 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
+ iommus = <&dwc3_0_dart_0 0>, <&dwc3_0_dart_1 1>;
+ status = "disabled";
+ };
+
+ dwc3_1_dart_0: iommu@502f00000 {
+ compatible = "apple,t8103-dart";
+ reg = <0x5 0x02f00000 0x0 0x4000>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 861 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ dwc3_1_dart_1: iommu@502f80000 {
+ compatible = "apple,t8103-dart";
+ reg = <0x5 0x02f80000 0x0 0x4000>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 861 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ dwc3_1: usb@502280000{
+ compatible = "snps,dwc3";
+ reg = <0x5 0x02280000 0x0 0x100000>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 857 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
+ iommus = <&dwc3_1_dart_0 0>, <&dwc3_1_dart_1 1>;
+ status = "disabled";
+ };
+
+ reboot@23d2b0000 {
+ compatible = "apple,reboot-v0";
+ reg = <0x2 0x3d2b0000 0x0 0x4000>;
+ };
+
+ spi@23510c000 {
+ compatible = "apple,t8103-spi", "apple,spi";
+ reg = <0x2 0x3510c000 0x0 0x4000>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 617 IRQ_TYPE_LEVEL_HIGH>;
+ cs-gpios = <&pinctrl_ap 49 GPIO_ACTIVE_HIGH>;
+ };
+
+ spmi@23d0d8000 {
+ compatible = "apple,t8103-spmi", "apple,spmi";
+ reg = <0x2 0x3d0d9300 0x0 0x100>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 343 IRQ_TYPE_LEVEL_HIGH>;
+
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ pmu@f {
+ compatible = "apple,sera-pmu";
+ reg = <0xf SPMI_USID>;
+ };
+ };
+ };
+};
compatible = "simple-bus";
ranges;
- aips0: aips-bus@40000000 {
+ aips0: bus@40000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
#size-cells = <0>;
compatible = "fsl,vf610-dspi";
reg = <0x4002c000 0x1000>;
- num-cs = <5>;
+ spi-num-chipselects = <5>;
status = "disabled";
};
#size-cells = <0>;
compatible = "fsl,vf610-dspi";
reg = <0x4002d000 0x1000>;
- num-cs = <5>;
+ spi-num-chipselects = <5>;
status = "disabled";
};
};
};
- aips1: aips-bus@40080000 {
+ aips1: bus@40080000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
#define CONFIG_SYS_NS16550_CLK 100000000
#define CONFIG_SYS_NS16550_CLK_DIV 54
-#define CONFIG_SERIAL_MULTI
#define CONFIG_SYS_NS16550_COM3 0x18023000
/* Ethernet */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Heungjun Kim <riverful.kim@samsung.com>
+ */
+
+#ifndef __ASM_ARCH_UART_H_
+#define __ASM_ARCH_UART_H_
+
+#ifndef __ASSEMBLY__
+/* baudrate rest value */
+union br_rest {
+ unsigned short slot; /* udivslot */
+ unsigned char value; /* ufracval */
+};
+
+struct s5p_uart {
+ unsigned int ulcon;
+ unsigned int ucon;
+ unsigned int ufcon;
+ unsigned int umcon;
+ unsigned int utrstat;
+ unsigned int uerstat;
+ unsigned int ufstat;
+ unsigned int umstat;
+ unsigned int utxh;
+ unsigned int urxh;
+ unsigned int ubrdiv;
+ union br_rest rest;
+ unsigned char res3[0x3fd0];
+};
+
+static inline int s5p_uart_divslot(void)
+{
+ return 0;
+}
+
+#endif /* __ASSEMBLY__ */
+
+#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2011
- * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
- *
- * (C) Copyright 2015
- * Kamil Lulko, <kamil.lulko@gmail.com>
- */
-
-#ifndef _STM32_GPIO_H_
-#define _STM32_GPIO_H_
-
-#include <asm/arch-stm32/gpio.h>
-
-#endif /* _STM32_GPIO_H_ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
- * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
- */
-
-#ifndef _STM32_GPIO_H_
-#define _STM32_GPIO_H_
-
-#include <asm/arch-stm32/gpio.h>
-
-#endif /* _STM32_GPIO_H_ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
- * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
- */
-
-#ifndef _STM32_GPIO_H_
-#define _STM32_GPIO_H_
-
-#include <asm/arch-stm32/gpio.h>
-
-#endif /* _STM32_GPIO_H_ */
#define GPT_FREE_RUNNING 0xFFFF
/* Timer, HZ specific defines */
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_HZ_CLOCK ((27 * 1000 * 1000) / GPT_PRESCALER_128)
#endif
#define GIC_REDISTRIBUTOR_OFFSET 0x20000
#ifdef CONFIG_GIC_V3_ITS
-int gic_lpi_tables_init(void);
+int gic_lpi_tables_init(u64 base, u32 max_redist);
#else
-int gic_lpi_tables_init(void)
+int gic_lpi_tables_init(u64 base, u32 max_redist)
{
return 0;
}
#define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \
MUX_MODE_SHIFT)
#ifdef CONFIG_IMX8M
-#define PAD_CTL_DSE0 (0x0 << 0)
-#define PAD_CTL_DSE1 (0x1 << 0)
-#define PAD_CTL_DSE2 (0x2 << 0)
-#define PAD_CTL_DSE3 (0x3 << 0)
-#define PAD_CTL_DSE4 (0x4 << 0)
-#define PAD_CTL_DSE5 (0x5 << 0)
-#define PAD_CTL_DSE6 (0x6 << 0)
-#define PAD_CTL_DSE7 (0x7 << 0)
-
#define PAD_CTL_FSEL0 (0x0 << 3)
#define PAD_CTL_FSEL1 (0x1 << 3)
#define PAD_CTL_FSEL2 (0x2 << 3)
#define PAD_CTL_PUE (0x1 << 6)
#define PAD_CTL_HYS (0x1 << 7)
#if defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
+#define PAD_CTL_DSE1 (0x0 << 1)
+#define PAD_CTL_DSE2 (0x2 << 1)
+#define PAD_CTL_DSE4 (0x1 << 1)
+#define PAD_CTL_DSE6 (0x3 << 1)
#define PAD_CTL_PE (0x1 << 8)
#else
+#define PAD_CTL_DSE0 (0x0 << 0)
+#define PAD_CTL_DSE1 (0x1 << 0)
+#define PAD_CTL_DSE2 (0x2 << 0)
+#define PAD_CTL_DSE3 (0x3 << 0)
+#define PAD_CTL_DSE4 (0x4 << 0)
+#define PAD_CTL_DSE5 (0x5 << 0)
+#define PAD_CTL_DSE6 (0x6 << 0)
+#define PAD_CTL_DSE7 (0x7 << 0)
#define PAD_CTL_LVTTL (0x1 << 8)
#endif
#include <common.h>
#include <cpu_func.h>
#include <dm.h>
-#include <regmap.h>
-#include <syscon.h>
#include <asm/gic.h>
#include <asm/gic-v3.h>
#include <asm/io.h>
#define LPI_PROPBASE_SZ ALIGN(BIT(LPI_NRBITS), SZ_64K)
#define LPI_PENDBASE_SZ ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
-/* Number of GIC re-distributors */
-#define MAX_GIC_REDISTRIBUTORS 8
-
/*
* gic_v3_its_priv - gic details
*
* @gicd_base: gicd base address
* @gicr_base: gicr base address
- * @lpi_base: gic lpi base address
- * @num_redist: number of gic re-distributors
*/
struct gic_v3_its_priv {
ulong gicd_base;
ulong gicr_base;
- ulong lpi_base;
- u32 num_redist;
};
static int gic_v3_its_get_gic_addr(struct gic_v3_its_priv *priv)
return 0;
}
-static int gic_v3_its_get_gic_lpi_addr(struct gic_v3_its_priv *priv)
-{
- struct regmap *regmap;
- struct udevice *dev;
- int ret;
-
- ret = uclass_get_device_by_driver(UCLASS_SYSCON,
- DM_DRIVER_GET(gic_lpi_syscon), &dev);
- if (ret) {
- pr_err("%s: failed to get %s syscon device\n", __func__,
- DM_DRIVER_GET(gic_lpi_syscon)->name);
- return ret;
- }
-
- regmap = syscon_get_regmap(dev);
- if (!regmap) {
- pr_err("%s: failed to regmap for %s syscon device\n", __func__,
- DM_DRIVER_GET(gic_lpi_syscon)->name);
- return -ENODEV;
- }
- priv->lpi_base = regmap->ranges[0].start;
-
- priv->num_redist = dev_read_u32_default(dev, "max-gic-redistributors",
- MAX_GIC_REDISTRIBUTORS);
-
- return 0;
-}
-
/*
* Program the GIC LPI configuration tables for all
* the re-distributors and enable the LPI table
+ * base: Configuration table address
+ * num_redist: number of redistributors
*/
-int gic_lpi_tables_init(void)
+int gic_lpi_tables_init(u64 base, u32 num_redist)
{
struct gic_v3_its_priv priv;
u32 gicd_typer;
int i;
u64 redist_lpi_base;
u64 pend_base;
- ulong pend_tab_total_sz;
+ ulong pend_tab_total_sz = num_redist * LPI_PENDBASE_SZ;
void *pend_tab_va;
if (gic_v3_its_get_gic_addr(&priv))
return -EINVAL;
- if (gic_v3_its_get_gic_lpi_addr(&priv))
- return -EINVAL;
-
gicd_typer = readl((uintptr_t)(priv.gicd_base + GICD_TYPER));
/* GIC support for Locality specific peripheral interrupts (LPI's) */
if (!(gicd_typer & GICD_TYPER_LPIS)) {
* Once the LPI table is enabled, can not program the
* LPI configuration tables again, unless the GIC is reset.
*/
- for (i = 0; i < priv.num_redist; i++) {
+ for (i = 0; i < num_redist; i++) {
u32 offset = i * GIC_REDISTRIBUTOR_OFFSET;
if ((readl((uintptr_t)(priv.gicr_base + offset))) &
ITS_MAX_LPI_NRBITS);
/* Set PropBase */
- val = (priv.lpi_base |
+ val = (base |
GICR_PROPBASER_INNERSHAREABLE |
GICR_PROPBASER_RAWAWB |
((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
}
}
- redist_lpi_base = priv.lpi_base + LPI_PROPBASE_SZ;
- pend_tab_total_sz = priv.num_redist * LPI_PENDBASE_SZ;
+ redist_lpi_base = base + LPI_PROPBASE_SZ;
pend_tab_va = map_physmem(redist_lpi_base, pend_tab_total_sz,
MAP_NOCACHE);
memset(pend_tab_va, 0, pend_tab_total_sz);
unmap_physmem(pend_tab_va, MAP_NOCACHE);
pend_base = priv.gicr_base + GICR_PENDBASER;
- for (i = 0; i < priv.num_redist; i++) {
+ for (i = 0; i < num_redist; i++) {
u32 offset = i * GIC_REDISTRIBUTOR_OFFSET;
val = ((redist_lpi_base + (i * LPI_PENDBASE_SZ)) |
.id = UCLASS_IRQ,
.of_match = gic_v3_its_ids,
};
-
-static const struct udevice_id gic_lpi_syscon_ids[] = {
- { .compatible = "gic-lpi-base" },
- {}
-};
-
-U_BOOT_DRIVER(gic_lpi_syscon) = {
- .name = "gic-lpi-base",
- .id = UCLASS_SYSCON,
- .of_match = gic_lpi_syscon_ids,
-};
* This function jumps to an image with argument. Normally an FDT or ATAGS
* image.
*/
-#ifdef CONFIG_SPL_OS_BOOT
+#if CONFIG_IS_ENABLED(OS_BOOT)
#ifdef CONFIG_ARM64
void __noreturn jump_to_image_linux(struct spl_image_info *spl_image)
{
}
#endif /* CONFIG_ARM64 */
#endif
+
+#if CONFIG_IS_ENABLED(OPTEE_IMAGE)
+void __noreturn jump_to_image_optee(struct spl_image_info *spl_image)
+{
+ /* flush and turn off caches before jumping to OPTEE */
+ cleanup_before_linux();
+
+ spl_optee_entry(NULL, NULL, spl_image->fdt_addr,
+ (void *)spl_image->entry_point);
+}
+#endif
--- /dev/null
+if ARCH_APPLE
+
+config SYS_TEXT_BASE
+ default 0x00000000
+
+config SYS_CONFIG_NAME
+ default "apple"
+
+config SYS_SOC
+ default "m1"
+
+config SYS_MALLOC_LEN
+ default 0x4000000
+
+config SYS_MALLOC_F_LEN
+ default 0x4000
+
+endif
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += board.o
+obj-y += lowlevel_init.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Mark Kettenis <kettenis@openbsd.org>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <efi_loader.h>
+
+#include <asm/armv8/mmu.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/system.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct mm_region apple_mem_map[] = {
+ {
+ /* I/O */
+ .virt = 0x200000000,
+ .phys = 0x200000000,
+ .size = 8UL * SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x500000000,
+ .phys = 0x500000000,
+ .size = 2UL * SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x680000000,
+ .phys = 0x680000000,
+ .size = SZ_512M,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* PCIE */
+ .virt = 0x6a0000000,
+ .phys = 0x6a0000000,
+ .size = SZ_512M,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
+ PTE_BLOCK_INNER_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* PCIE */
+ .virt = 0x6c0000000,
+ .phys = 0x6c0000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
+ PTE_BLOCK_INNER_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* RAM */
+ .virt = 0x800000000,
+ .phys = 0x800000000,
+ .size = 8UL * SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ /* Empty entry for framebuffer */
+ 0,
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = apple_mem_map;
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ ofnode node;
+ int index, ret;
+ fdt_addr_t base;
+ fdt_size_t size;
+
+ ret = fdtdec_setup_mem_size_base();
+ if (ret)
+ return ret;
+
+ /* Update RAM mapping */
+ index = ARRAY_SIZE(apple_mem_map) - 3;
+ apple_mem_map[index].virt = gd->ram_base;
+ apple_mem_map[index].phys = gd->ram_base;
+ apple_mem_map[index].size = gd->ram_size;
+
+ node = ofnode_path("/chosen/framebuffer");
+ if (!ofnode_valid(node))
+ return 0;
+
+ base = ofnode_get_addr_size(node, "reg", &size);
+ if (base == FDT_ADDR_T_NONE)
+ return 0;
+
+ /* Add framebuffer mapping */
+ index = ARRAY_SIZE(apple_mem_map) - 2;
+ apple_mem_map[index].virt = base;
+ apple_mem_map[index].phys = base;
+ apple_mem_map[index].size = size;
+ apple_mem_map[index].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
+ PTE_BLOCK_INNER_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN;
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
+
+#define APPLE_WDT_BASE 0x23d2b0000ULL
+
+#define APPLE_WDT_SYS_CTL_ENABLE BIT(2)
+
+typedef struct apple_wdt {
+ u32 reserved0[3];
+ u32 chip_ctl;
+ u32 sys_tmr;
+ u32 sys_cmp;
+ u32 reserved1;
+ u32 sys_ctl;
+} apple_wdt_t;
+
+void reset_cpu(void)
+{
+ apple_wdt_t *wdt = (apple_wdt_t *)APPLE_WDT_BASE;
+
+ writel(0, &wdt->sys_cmp);
+ writel(APPLE_WDT_SYS_CTL_ENABLE, &wdt->sys_ctl);
+
+ while(1)
+ wfi();
+}
+
+extern long fw_dtb_pointer;
+
+void *board_fdt_blob_setup(int *err)
+{
+ /* Return DTB pointer passed by m1n1 */
+ *err = 0;
+ return (void *)fw_dtb_pointer;
+}
+
+ulong board_get_usable_ram_top(ulong total_size)
+{
+ /*
+ * Top part of RAM is used by firmware for things like the
+ * framebuffer. This gives us plenty of room to play with.
+ */
+ return 0x980000000;
+}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2021 Mark Kettenis <kettenis@openbsd.org>
+ */
+
+.align 8
+.global fw_dtb_pointer
+fw_dtb_pointer:
+ .quad 0
+
+.global save_boot_params
+save_boot_params:
+ /* Stash DTB pointer passed by m1n1 */
+ adr x1, fw_dtb_pointer
+ str x0, [x1]
+
+ b save_boot_params_ret
select PINCTRL_EXYNOS7420
select SUPPORT_SPL
+config TARGET_A5Y17LTE
+ bool "Samsung SM-A520F board"
+ select ARM64
+ select CLK_EXYNOS
+ select OF_CONTROL
+ select PINCTRL
+ select PINCTRL_EXYNOS78x0
+ select SUPPORT_SPL
+
+config TARGET_A7Y17LTE
+ bool "Samsung SM-A520F board"
+ select ARM64
+ select CLK_EXYNOS
+ select OF_CONTROL
+ select PINCTRL
+ select PINCTRL_EXYNOS78x0
+ select SUPPORT_SPL
+
+config TARGET_A3Y17LTE
+ bool "Samsung SM-A520F board"
+ select ARM64
+ select CLK_EXYNOS
+ select OF_CONTROL
+ select PINCTRL
+ select PINCTRL_EXYNOS7880
+ select SUPPORT_SPL
+
endchoice
endif
source "board/samsung/smdk5250/Kconfig"
source "board/samsung/smdk5420/Kconfig"
source "board/samsung/espresso7420/Kconfig"
+source "board/samsung/axy17lte/Kconfig"
config SPL_LDSCRIPT
default "board/samsung/common/exynos-uboot-spl.lds" if ARCH_EXYNOS5 || ARCH_EXYNOS4
#include <common.h>
#include <asm/armv8/mmu.h>
-#ifdef CONFIG_EXYNOS7420
+#if CONFIG_IS_ENABLED(EXYNOS7420)
+
static struct mm_region exynos7420_mem_map[] = {
{
.virt = 0x10000000UL,
};
struct mm_region *mem_map = exynos7420_mem_map;
+
+#elif CONFIG_IS_ENABLED(EXYNOS7870)
+
+static struct mm_region exynos7870_mem_map[] = {
+ {
+ .virt = 0x10000000UL,
+ .phys = 0x10000000UL,
+ .size = 0x10000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+ },
+ {
+ .virt = 0x40000000UL,
+ .phys = 0x40000000UL,
+ .size = 0x3E400000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE,
+ },
+ {
+ .virt = 0x80000000UL,
+ .phys = 0x80000000UL,
+ .size = 0x40000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE,
+ },
+
+ {
+ /* List terminator */
+ },
+};
+
+struct mm_region *mem_map = exynos7870_mem_map;
+
+#elif CONFIG_IS_ENABLED(EXYNOS7880)
+
+static struct mm_region exynos7880_mem_map[] = {
+ {
+ .virt = 0x10000000UL,
+ .phys = 0x10000000UL,
+ .size = 0x10000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+ },
+ {
+ .virt = 0x40000000UL,
+ .phys = 0x40000000UL,
+ .size = 0x3E400000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE,
+ },
+ {
+ .virt = 0x80000000UL,
+ .phys = 0x80000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE,
+ },
+
+ {
+ /* List terminator */
+ },
+};
+
+struct mm_region *mem_map = exynos7880_mem_map;
#endif
config IMX_HAB
bool "Support i.MX HAB features"
- depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5 || ARCH_IMX8M
+ depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5 || ARCH_IMX8M || ARCH_MX7ULP
select FSL_CAAM if HAS_CAAM
imply CMD_DEKBLOB if HAS_CAAM
help
endif
obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o
obj-$(CONFIG_FEC_MXC) += mac.o
+obj-$(CONFIG_DWC_ETH_QOS) += mac.o
obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
obj-$(CONFIG_IMX_HAB) += hab.o
obj-y += cpu.o
DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o u-boot-dtb.cfgout $(srctree)/$(IMX_CONFIG); if [ -f u-boot-dtb.cfgout ]; then $(CNTR_DEPFILES) u-boot-dtb.cfgout; echo $$?; fi)
else ifeq ($(CONFIG_ARCH_IMX8M), y)
IMAGE_TYPE := imx8mimage
-IMX8M_DEPFILES := $(srctree)/tools/imx8m_image.sh
-DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o spl/u-boot-spl.cfgout $(srctree)/$(IMX_CONFIG);if [ -f spl/u-boot-spl.cfgout ]; then $(IMX8M_DEPFILES) spl/u-boot-spl.cfgout 0; echo $$?; fi)
+DEPFILE_EXISTS := 0
else
IMAGE_TYPE := imximage
DEPFILE_EXISTS := 0
ifdef CONFIG_ARM64
ifeq ($(CONFIG_ARCH_IMX8M), y)
-SPL:
+
+SPL: spl/u-boot-spl.bin spl/u-boot-spl.cfgout FORCE
MKIMAGEFLAGS_flash.bin = -n spl/u-boot-spl.cfgout \
-T $(IMAGE_TYPE) -e $(CONFIG_SPL_TEXT_BASE)
flash.bin: MKIMAGEOUTPUT = flash.log
+spl/u-boot-spl.cfgout: $(IMX_CONFIG) FORCE
+ $(Q)mkdir -p $(dir $@)
+ $(call if_changed_dep,cpp_cfg)
+
spl/u-boot-spl-ddr.bin: spl/u-boot-spl.bin spl/u-boot-spl.cfgout FORCE
-ifeq ($(DEPFILE_EXISTS),0)
- $(IMX8M_DEPFILES) spl/u-boot-spl.cfgout 1
-endif
flash.bin: spl/u-boot-spl-ddr.bin u-boot.itb FORCE
$(call if_changed,mkimage)
default "imx8m"
choice
- prompt "NXP i.MX8M board select"
+ prompt "NXP i.MX8M board select"
optional
config TARGET_IMX8MQ_CM
- bool "Ronetix iMX8MQ-CM SoM"
+ bool "Ronetix iMX8MQ-CM SoM"
select BINMAN
- select IMX8MQ
- select IMX8M_LPDDR4
+ select IMX8MQ
+ select IMX8M_LPDDR4
config TARGET_IMX8MQ_EVK
bool "imx8mq_evk"
select SUPPORT_SPL
select IMX8M_LPDDR4
+config TARGET_KONTRON_MX8MM
+ bool "Kontron Electronics N80xx"
+ select BINMAN
+ select IMX8MM
+ select SUPPORT_SPL
+ select IMX8M_LPDDR4
+
config TARGET_IMX8MN_EVK
bool "imx8mn LPDDR4 EVK board"
select BINMAN
select IMX8M_LPDDR4
config TARGET_VERDIN_IMX8MM
- bool "Support Toradex Verdin iMX8M Mini module"
- select IMX8MM
- select SUPPORT_SPL
- select IMX8M_LPDDR4
+ bool "Support Toradex Verdin iMX8M Mini module"
+ select BINMAN
+ select IMX8MM
+ select SUPPORT_SPL
+ select IMX8M_LPDDR4
config TARGET_IMX8MM_BEACON
bool "imx8mm Beacon Embedded devkit"
config TARGET_PHYCORE_IMX8MM
bool "PHYTEC PHYCORE i.MX8MM"
+ select BINMAN
select IMX8MM
- select SUPPORT_SPL
+ select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_PHYCORE_IMX8MP
bool "PHYTEC PHYCORE i.MX8MP"
select BINMAN
select IMX8MP
- select SUPPORT_SPL
+ select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_IMX8MM_CL_IOT_GATE
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
+
+config TARGET_IMX8MM_CL_IOT_GATE_OPTEE
+ bool "CompuLab iot-gate-imx8 with optee support"
+ select BINMAN
+ select IMX8MM
+ select SUPPORT_SPL
+ select IMX8M_LPDDR4
endchoice
source "board/beacon/imx8mm/Kconfig"
source "board/freescale/imx8mp_evk/Kconfig"
source "board/gateworks/venice/Kconfig"
source "board/google/imx8mq_phanbell/Kconfig"
+source "board/kontron/sl-mx8mm/Kconfig"
source "board/phytec/phycore_imx8mm/Kconfig"
source "board/phytec/phycore_imx8mp/Kconfig"
source "board/ronetix/imx8mq-cm/Kconfig"
ulong board_get_usable_ram_top(ulong total_size)
{
+ ulong top_addr = PHYS_SDRAM + gd->ram_size;
+
/*
* Some IPs have their accessible address space restricted by
* the interconnect. Let's make sure U-Boot only ever uses the
* space below the 4G address boundary (which is 3GiB big),
* even when the effective available memory is bigger.
*/
- if (PHYS_SDRAM + gd->ram_size > 0x80000000)
- return 0x80000000;
+ if (top_addr > 0x80000000)
+ top_addr = 0x80000000;
+
+ /*
+ * rom_pointer[0] stores the TEE memory start address.
+ * rom_pointer[1] stores the size TEE uses.
+ * We need to reserve the memory region for TEE.
+ */
+ if (rom_pointer[0] && rom_pointer[1] && top_addr > rom_pointer[0])
+ top_addr = rom_pointer[0];
- return PHYS_SDRAM + gd->ram_size;
+ return top_addr;
}
static u32 get_cpu_variant_type(u32 type)
offset = is_mx6() ? MAC_FUSE_MX6_OFFSET : MAC_FUSE_MX7_OFFSET;
fuse = (struct imx_mac_fuse *)(ulong)(OCOTP_BASE_ADDR + offset);
- has_second_mac = is_mx7() || is_mx6sx() || is_mx6ul() || is_mx6ull();
+ has_second_mac = is_mx7() || is_mx6sx() || is_mx6ul() || is_mx6ull() || is_imx8mp();
if (has_second_mac && dev_id == 1) {
u32 value = readl(&fuse->mac_addr2);
+++ /dev/null
-#!/bin/sh
-# SPDX-License-Identifier: GPL-2.0+
-#
-# script to generate FIT image source for i.MX8MQ boards with
-# ARM Trusted Firmware and multiple device trees (given on the command line)
-#
-# usage: $0 <dt_name> [<dt_name> [<dt_name] ...]
-
-[ -z "$BL31" ] && BL31="bl31.bin"
-[ -z "$TEE_LOAD_ADDR" ] && TEE_LOAD_ADDR="0xfe000000"
-[ -z "$ATF_LOAD_ADDR" ] && ATF_LOAD_ADDR="0x00910000"
-[ -z "$BL33_LOAD_ADDR" ] && BL33_LOAD_ADDR="0x40200000"
-
-if [ ! -f $BL31 ]; then
- echo "ERROR: BL31 file $BL31 NOT found" >&2
- exit 0
-else
- echo "$BL31 size: " >&2
- stat -c %s $BL31 >&2
-fi
-
-BL32="tee.bin"
-
-if [ ! -f $BL32 ]; then
- BL32=/dev/null
-else
- echo "Building with TEE support, make sure your $BL31 is compiled with spd. If you do not want tee, please delete $BL31" >&2
- echo "$BL32 size: " >&2
- stat -c %s $BL32 >&2
-fi
-
-BL33="u-boot-nodtb.bin"
-
-if [ ! -f $BL33 ]; then
- echo "ERROR: $BL33 file NOT found" >&2
- exit 0
-else
- echo "u-boot-nodtb.bin size: " >&2
- stat -c %s u-boot-nodtb.bin >&2
-fi
-
-for dtname in $*
-do
- echo "$dtname size: " >&2
- stat -c %s $dtname >&2
-done
-
-
-cat << __HEADER_EOF
-/dts-v1/;
-
-/ {
- description = "Configuration to load ATF before U-Boot";
-
- images {
- uboot@1 {
- description = "U-Boot (64-bit)";
- os = "u-boot";
- data = /incbin/("$BL33");
- type = "standalone";
- arch = "arm64";
- compression = "none";
- load = <$BL33_LOAD_ADDR>;
- };
-__HEADER_EOF
-
-cnt=1
-for dtname in $*
-do
- cat << __FDT_IMAGE_EOF
- fdt@$cnt {
- description = "$(basename $dtname .dtb)";
- data = /incbin/("$dtname");
- type = "flat_dt";
- compression = "none";
- };
-__FDT_IMAGE_EOF
-cnt=$((cnt+1))
-done
-
-cat << __HEADER_EOF
- atf@1 {
- description = "ARM Trusted Firmware";
- os = "arm-trusted-firmware";
- data = /incbin/("$BL31");
- type = "firmware";
- arch = "arm64";
- compression = "none";
- load = <$ATF_LOAD_ADDR>;
- entry = <$ATF_LOAD_ADDR>;
- };
-__HEADER_EOF
-
-if [ -f $BL32 ]; then
-cat << __HEADER_EOF
- tee@1 {
- description = "TEE firmware";
- data = /incbin/("$BL32");
- type = "firmware";
- arch = "arm64";
- compression = "none";
- load = <$TEE_LOAD_ADDR>;
- entry = <$TEE_LOAD_ADDR>;
- };
-__HEADER_EOF
-fi
-
-cat << __CONF_HEADER_EOF
- };
- configurations {
- default = "config@1";
-
-__CONF_HEADER_EOF
-
-cnt=1
-for dtname in $*
-do
-if [ -f $BL32 ]; then
-cat << __CONF_SECTION_EOF
- config@$cnt {
- description = "$(basename $dtname .dtb)";
- firmware = "uboot@1";
- loadables = "atf@1", "tee@1";
- fdt = "fdt@$cnt";
- };
-__CONF_SECTION_EOF
-else
-cat << __CONF_SECTION1_EOF
- config@$cnt {
- description = "$(basename $dtname .dtb)";
- firmware = "uboot@1";
- loadables = "atf@1";
- fdt = "fdt@$cnt";
- };
-__CONF_SECTION1_EOF
-fi
-cnt=$((cnt+1))
-done
-
-cat << __ITS_EOF
- };
-};
-__ITS_EOF
imply CMD_SATA
imply CMD_SPL
+config TARGET_KONTRON_MX6UL
+ bool "Kontron Electronics SL/BL i.MX6UL/ULL (N63xx/N64xx)"
+ depends on MX6UL
+ select BINMAN
+ select DM
+ select DM_THERMAL
+ select SUPPORT_SPL
+ imply CMD_DM
+
config TARGET_KOSAGI_NOVENA
bool "Kosagi Novena"
select BOARD_LATE_INIT
source "board/phytec/pcm058/Kconfig"
source "board/phytec/pcl063/Kconfig"
source "board/gateworks/gw_ventana/Kconfig"
+source "board/kontron/sl-mx6ul/Kconfig"
source "board/kosagi/novena/Kconfig"
source "board/softing/vining_2000/Kconfig"
source "board/liebherr/display5/Kconfig"
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/hab.h>
+#include <asm/setup.h>
#include <linux/bitops.h>
#define PMC0_BASE_ADDR 0x410a1000
static void disable_wdog(u32 wdog_base)
{
- writel(UNLOCK_WORD0, (wdog_base + 0x04));
- writel(UNLOCK_WORD1, (wdog_base + 0x04));
- writel(0x0, (wdog_base + 0x0C)); /* Set WIN to 0 */
- writel(0x400, (wdog_base + 0x08)); /* Set timeout to default 0x400 */
- writel(0x120, (wdog_base + 0x00)); /* Disable it and set update */
-
- writel(REFRESH_WORD0, (wdog_base + 0x04)); /* Refresh the CNT */
- writel(REFRESH_WORD1, (wdog_base + 0x04));
+ u32 val_cs = readl(wdog_base + 0x00);
+
+ if (!(val_cs & 0x80))
+ return;
+
+ dmb();
+ __raw_writel(REFRESH_WORD0, (wdog_base + 0x04)); /* Refresh the CNT */
+ __raw_writel(REFRESH_WORD1, (wdog_base + 0x04));
+ dmb();
+
+ if (!(val_cs & 800)) {
+ dmb();
+ __raw_writel(UNLOCK_WORD0, (wdog_base + 0x04));
+ __raw_writel(UNLOCK_WORD1, (wdog_base + 0x04));
+ dmb();
+
+ while (!(readl(wdog_base + 0x00) & 0x800));
+ }
+ dmb();
+ __raw_writel(0x0, wdog_base + 0x0C); /* Set WIN to 0 */
+ __raw_writel(0x400, wdog_base + 0x08); /* Set timeout to default 0x400 */
+ __raw_writel(0x120, wdog_base + 0x00); /* Disable it and set update */
+ dmb();
+
+ while (!(readl(wdog_base + 0x00) & 0x400));
}
void init_wdog(void)
return boot_dev;
}
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+/*
+ * OCOTP_CFG (SJC CHALLENGE, Unique ID)
+ * i.MX 7ULP Applications Processor Reference Manual, Rev. 0, 09/2020
+ *
+ * OCOTP_CFG0 offset 0x4B0: 15:0 -> 15:0 bits of Unique ID
+ * OCOTP_CFG1 offset 0x4C0: 15:0 -> 31:16 bits of Unique ID
+ * OCOTP_CFG2 offset 0x4D0: 15:0 -> 47:32 bits of Unique ID
+ * OCOTP_CFG3 offset 0x4E0: 15:0 -> 63:48 bits of Unique ID
+ */
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[1];
+ struct fuse_bank1_regs *fuse =
+ (struct fuse_bank1_regs *)bank->fuse_regs;
+
+ serialnr->low = (fuse->cfg0 & 0xFFFF) + ((fuse->cfg1 & 0xFFFF) << 16);
+ serialnr->high = (fuse->cfg2 & 0xFFFF) + ((fuse->cfg3 & 0xFFFF) << 16);
+}
+#endif /* CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG */
}
#endif
+void *board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len)
+{
+ int align_len = ARCH_DMA_MINALIGN - 1;
+
+ /* Some devices like SDP, NOR, NAND, SPI are using bl_len =1, so their fit address
+ * is different with SD/MMC, this cause mismatch with signed address. Thus, adjust
+ * the bl_len to align with SD/MMC.
+ */
+ if (bl_len < 512)
+ bl_len = 512;
+
+ return (void *)((CONFIG_SYS_TEXT_BASE - fit_size - bl_len -
+ align_len) & ~align_len);
+}
#endif
#if defined(CONFIG_MX6) && defined(CONFIG_SPL_OS_BOOT)
return 0;
}
#endif
+
+/*
+ * read the address where the IVT header must sit
+ * from IVT image header, loaded from SPL into
+ * an malloced buffer and copy the IVT header
+ * to this address
+ */
+void *spl_load_simple_fit_fix_load(const void *fit)
+{
+ struct ivt *ivt;
+ unsigned long new;
+ unsigned long offset;
+ unsigned long size;
+ u8 *tmp = (u8 *)fit;
+
+ offset = ALIGN(fdt_totalsize(fit), 0x1000);
+ size = ALIGN(fdt_totalsize(fit), 4);
+ size = board_spl_fit_size_align(size);
+ tmp += offset;
+ ivt = (struct ivt *)tmp;
+ if (ivt->hdr.magic != IVT_HEADER_MAGIC) {
+ debug("no IVT header found\n");
+ return (void *)fit;
+ }
+ debug("%s: ivt: %p offset: %lx size: %lx\n", __func__, ivt, offset, size);
+ debug("%s: ivt self: %x\n", __func__, ivt->self);
+ new = ivt->self;
+ new -= offset;
+ debug("%s: new %lx\n", __func__, new);
+ memcpy((void *)new, fit, size);
+
+ return (void *)new;
+}
return regs.regs[0];
}
+ssize_t meson_sm_write_efuse(uintptr_t offset, void *buffer, size_t size)
+{
+ struct pt_regs regs;
+
+ meson_init_shmem();
+
+ memcpy(shmem_input, buffer, size);
+
+ regs.regs[0] = FN_EFUSE_WRITE;
+ regs.regs[1] = offset;
+ regs.regs[2] = size;
+
+ smc_call(®s);
+
+ if (regs.regs[0] == 0)
+ return -1;
+
+ return 0;
+}
+
#define SM_CHIP_ID_LENGTH 119
#define SM_CHIP_ID_OFFSET 4
#define SM_CHIP_ID_SIZE 12
return CMD_RET_SUCCESS;
}
+static int do_efuse_read(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ ulong address, offset, size;
+ int ret;
+
+ if (argc < 4)
+ return CMD_RET_USAGE;
+
+ offset = simple_strtoul(argv[1], NULL, 0);
+ size = simple_strtoul(argv[2], NULL, 0);
+
+ address = simple_strtoul(argv[3], NULL, 0);
+
+ ret = meson_sm_read_efuse(offset, (void *)address, size);
+ if (ret)
+ return CMD_RET_FAILURE;
+
+ return CMD_RET_SUCCESS;
+}
+
+static int do_efuse_write(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ ulong address, offset, size;
+ int ret;
+
+ if (argc < 4)
+ return CMD_RET_USAGE;
+
+ offset = simple_strtoul(argv[1], NULL, 0);
+ size = simple_strtoul(argv[2], NULL, 0);
+
+ address = simple_strtoul(argv[3], NULL, 0);
+
+ ret = meson_sm_write_efuse(offset, (void *)address, size);
+ if (ret)
+ return CMD_RET_FAILURE;
+
+ return CMD_RET_SUCCESS;
+}
+
static struct cmd_tbl cmd_sm_sub[] = {
U_BOOT_CMD_MKENT(serial, 2, 1, do_sm_serial, "", ""),
U_BOOT_CMD_MKENT(reboot_reason, 1, 1, do_sm_reboot_reason, "", ""),
+ U_BOOT_CMD_MKENT(efuseread, 4, 1, do_efuse_read, "", ""),
+ U_BOOT_CMD_MKENT(efusewrite, 4, 0, do_efuse_write, "", ""),
};
static int do_sm(struct cmd_tbl *cmdtp, int flag, int argc,
sm, 5, 0, do_sm,
"Secure Monitor Control",
"serial <address> - read chip unique id to memory address\n"
- "sm reboot_reason [name] - get reboot reason and store to to environment"
+ "sm reboot_reason [name] - get reboot reason and store to to environment\n"
+ "sm efuseread <offset> <size> <address> - read efuse to memory address\n"
+ "sm efusewrite <offset> <size> <address> - write into efuse from memory address"
);
select SPL_DM if SPL
select SPL_DM_SEQ_ALIAS if SPL
select SPL_OF_CONTROL if SPL
- select SPL_SKIP_LOWLEVEL_INIT
+ select SPL_SKIP_LOWLEVEL_INIT if SPL
select SPL_SIMPLE_BUS if SPL
select SUPPORT_SPL
select TRANSLATION_OFFSET
select DM_I2C
select I2C_MUX
select I2C_MUX_PCA954x
+ select SPL_DRIVERS_MISC
select SPL_I2C_MUX
+ select SPL_SYS_MALLOC_SIMPLE
select SYS_I2C_MVTWSI
select ATSHA204A
#@BOOT_FROM
# Binary Header (bin_hdr) with DDR3 training code
-BINARY spl/u-boot-spl.bin 0000005b 00000068
+BINARY spl/u-boot-spl.bin
#include <config.h>
#include <linux/linkage.h>
+/*
+ * BootROM loads the header part of kwbimage into L2 cache. BIN header usually
+ * contains U-Boot SPL, optionally it can also contain additional arguments.
+ * The number of these arguments is in r0, pointer to the argument array in r1.
+ * BootROM expects executable BIN header code to return to address stored in lr.
+ * Other registers (r2 - r12) must be preserved. We save all registers to
+ * CONFIG_SPL_BOOTROM_SAVE address. BIN header arguments (passed via r0 and r1)
+ * are currently not used by U-Boot SPL binary.
+ */
ENTRY(save_boot_params)
stmfd sp!, {r0 - r12, lr} /* @ save registers on stack */
ldr r12, =CONFIG_SPL_BOOTROM_SAVE
#define IBR_HDR_UART_ID 0x69
#define IBR_HDR_SDIO_ID 0xAE
-/* Structure of the main header, version 1 (Armada 370/38x/XP) */
+/* Structure of the main header, version 1 (Armada 370/XP/375/38x/39x) */
struct kwbimage_main_hdr_v1 {
uint8_t blockid; /* 0x0 */
uint8_t flags; /* 0x1 */
- uint16_t reserved2; /* 0x2-0x3 */
+ uint16_t nandpagesize; /* 0x2-0x3 */
uint32_t blocksize; /* 0x4-0x7 */
uint8_t version; /* 0x8 */
uint8_t headersz_msb; /* 0x9 */
return BOOT_DEVICE_MMC1;
#endif
#ifdef CONFIG_SPL_SATA
- case BOOT_FROM_SATA:
- return BOOT_FROM_SATA;
+ case BOOT_DEVICE_SATA:
+ return BOOT_DEVICE_SATA;
#endif
#ifdef CONFIG_SPL_SPI_FLASH_SUPPORT
case BOOT_DEVICE_SPI:
prompt "Renesas ARM64 SoCs board select"
optional
-config TARGET_BEACON_RZG2H
- bool "Beacon EmbeddedWorks RZ/G2H Dev Kit"
- select R8A774E1
- select RZ_G2
- select PINCTRL_PFC_R8A774E1
-
config TARGET_BEACON_RZG2M
- bool "Beacon EmbeddedWorks RZ/G2M Dev Kit"
+ bool "Beacon EmbeddedWorks RZ/G2 Dev Kit"
select R8A774A1
- select RZ_G2
- select PINCTRL_PFC_R8A774A1
-
-config TARGET_BEACON_RZG2N
- bool "Beacon EmbeddedWorks RZ/G2N Dev Kit"
select R8A774B1
+ select R8A774E1
select RZ_G2
+ select PINCTRL_PFC_R8A774A1
select PINCTRL_PFC_R8A774B1
+ select PINCTRL_PFC_R8A774E1
+ imply MULTI_DTB_FIT
+ imply MULTI_DTB_FIT_USER_DEFINED_AREA
+ imply CLK_VERSACLOCK
+ imply CLK_CCF
config TARGET_CONDOR
bool "Condor board"
source "board/silinux/ek874/Kconfig"
config MULTI_DTB_FIT_UNCOMPRESS_SZ
+ default 0x80000 if TARGET_BEACON_RZG2M
default 0x80000 if TARGET_HIHOPE_RZG2
default 0x80000 if TARGET_SALVATOR_X
default 0x80000 if TARGET_ULCB
config MULTI_DTB_FIT_USER_DEF_ADDR
+ default 0x49000000 if TARGET_BEACON_RZG2M
default 0x49000000 if TARGET_HIHOPE_RZG2
default 0x49000000 if TARGET_SALVATOR_X
default 0x49000000 if TARGET_ULCB
config SPL_SYS_MALLOC_F_LEN
default 0x2000
+config SDM845
+ bool "Qualcomm Snapdragon 845 SoC"
+ default n
+ select LINUX_KERNEL_IMAGE_HEADER
+
+config LNX_KRNL_IMG_TEXT_OFFSET_BASE
+ default 0x80000000
+
choice
prompt "Snapdragon board select"
- 3GiB RAM
- 32GiB UFS drive
+config TARGET_STARQLTECHN
+ bool "Samsung S9 SM-G9600(starqltechn)"
+ help
+ Support for Samsung S9 SM-G9600(starqltechn) board.
+ Features:
+ - Qualcomm Snapdragon SDM845 SoC
+ - 4GiB RAM
+ - 64GiB UFS drive
+ select MISC_INIT_R
+ select SDM845
+ select DM_ETH if NET
+
endchoice
source "board/qualcomm/dragonboard410c/Kconfig"
source "board/qualcomm/dragonboard820c/Kconfig"
+source "board/samsung/starqltechn/Kconfig"
endif
#
# (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+obj-$(CONFIG_SDM845) += clock-sdm845.o
+obj-$(CONFIG_SDM845) += sysmap-sdm845.o
+obj-$(CONFIG_SDM845) += init_sdm845.o
obj-$(CONFIG_TARGET_DRAGONBOARD820C) += clock-apq8096.o
obj-$(CONFIG_TARGET_DRAGONBOARD820C) += sysmap-apq8096.o
obj-$(CONFIG_TARGET_DRAGONBOARD410C) += clock-apq8016.o
obj-y += pinctrl-snapdragon.o
obj-y += pinctrl-apq8016.o
obj-y += pinctrl-apq8096.o
+obj-$(CONFIG_SDM845) += pinctrl-sdm845.o
--- /dev/null
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Clock drivers for Qualcomm SDM845
+ *
+ * (C) Copyright 2017 Jorge Ramirez Ortiz <jorge.ramirez-ortiz@linaro.org>
+ * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
+ *
+ * Based on Little Kernel driver, simplified
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include "clock-snapdragon.h"
+
+#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
+
+struct freq_tbl {
+ uint freq;
+ uint src;
+ u8 pre_div;
+ u16 m;
+ u16 n;
+};
+
+static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
+ F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625),
+ F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625),
+ F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
+ F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625),
+ F(32000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75),
+ F(48000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25),
+ F(64000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75),
+ F(80000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15),
+ F(96000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25),
+ F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0),
+ F(102400000, CFG_CLK_SRC_GPLL0_EVEN, 1, 128, 375),
+ F(112000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 28, 75),
+ F(117964800, CFG_CLK_SRC_GPLL0_EVEN, 1, 6144, 15625),
+ F(120000000, CFG_CLK_SRC_GPLL0_EVEN, 2.5, 0, 0),
+ F(128000000, CFG_CLK_SRC_GPLL0, 1, 16, 75),
+ { }
+};
+
+static const struct bcr_regs uart2_regs = {
+ .cfg_rcgr = SE9_UART_APPS_CFG_RCGR,
+ .cmd_rcgr = SE9_UART_APPS_CMD_RCGR,
+ .M = SE9_UART_APPS_M,
+ .N = SE9_UART_APPS_N,
+ .D = SE9_UART_APPS_D,
+};
+
+const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate)
+{
+ if (!f)
+ return NULL;
+
+ if (!f->freq)
+ return f;
+
+ for (; f->freq; f++)
+ if (rate <= f->freq)
+ return f;
+
+ /* Default to our fastest rate */
+ return f - 1;
+}
+
+static int clk_init_uart(struct msm_clk_priv *priv, uint rate)
+{
+ const struct freq_tbl *freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s0_clk_src, rate);
+
+ clk_rcg_set_rate_mnd(priv->base, &uart2_regs,
+ freq->pre_div, freq->m, freq->n, freq->src);
+
+ return 0;
+}
+
+ulong msm_set_rate(struct clk *clk, ulong rate)
+{
+ struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+
+ switch (clk->id) {
+ case 0x58: /*UART2*/
+ return clk_init_uart(priv, rate);
+ default:
+ return 0;
+ }
+}
{ .compatible = "qcom,gcc-apq8016" },
{ .compatible = "qcom,gcc-msm8996" },
{ .compatible = "qcom,gcc-apq8096" },
+ { .compatible = "qcom,gcc-sdm845" },
{ }
};
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Qualcomm APQ8016, APQ8096
+ * Qualcomm APQ8016, APQ8096, SDM845
*
* (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
*/
#define CFG_CLK_SRC_CXO (0 << 8)
#define CFG_CLK_SRC_GPLL0 (1 << 8)
+#define CFG_CLK_SRC_GPLL0_EVEN (6 << 8)
#define CFG_CLK_SRC_MASK (7 << 8)
struct pll_vote_clk {
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Qualcomm SDM845 sysmap
+ *
+ * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
+ */
+#ifndef _MACH_SYSMAP_SDM845_H
+#define _MACH_SYSMAP_SDM845_H
+
+#define TLMM_BASE_ADDR (0x1010000)
+
+/* Strength (sdc1) */
+#define SDC1_HDRV_PULL_CTL_REG (TLMM_BASE_ADDR + 0x0012D000)
+
+/* Clocks: (from CLK_CTL_BASE) */
+#define GPLL0_STATUS (0x0000)
+#define APCS_GPLL_ENA_VOTE (0x52000)
+#define APCS_CLOCK_BRANCH_ENA_VOTE (0x52004)
+
+#define SDCC2_BCR (0x14000) /* block reset */
+#define SDCC2_APPS_CBCR (0x14004) /* branch control */
+#define SDCC2_AHB_CBCR (0x14008)
+#define SDCC2_CMD_RCGR (0x1400c)
+#define SDCC2_CFG_RCGR (0x14010)
+#define SDCC2_M (0x14014)
+#define SDCC2_N (0x14018)
+#define SDCC2_D (0x1401C)
+
+#define RCG2_CFG_REG 0x4
+#define M_REG 0x8
+#define N_REG 0xc
+#define D_REG 0x10
+
+#define SE9_AHB_CBCR (0x25004)
+#define SE9_UART_APPS_CBCR (0x29004)
+#define SE9_UART_APPS_CMD_RCGR (0x18148)
+#define SE9_UART_APPS_CFG_RCGR (0x1814C)
+#define SE9_UART_APPS_M (0x18150)
+#define SE9_UART_APPS_N (0x18154)
+#define SE9_UART_APPS_D (0x18158)
+
+#endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Common init part for boards based on SDM845
+ *
+ * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
+ */
+
+#include <init.h>
+#include <env.h>
+#include <common.h>
+#include <asm/system.h>
+#include <asm/gpio.h>
+#include <dm.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
+
+void reset_cpu(void)
+{
+ psci_system_reset();
+}
+
+__weak int board_init(void)
+{
+ return 0;
+}
+
+/* Check for vol- and power buttons */
+__weak int misc_init_r(void)
+{
+ struct udevice *pon;
+ struct gpio_desc resin;
+ int node, ret;
+
+ ret = uclass_get_device_by_name(UCLASS_GPIO, "pm8998_pon@800", &pon);
+ if (ret < 0) {
+ printf("Failed to find PMIC pon node. Check device tree\n");
+ return 0;
+ }
+
+ node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(pon),
+ "key_vol_down");
+ if (node < 0) {
+ printf("Failed to find key_vol_down node. Check device tree\n");
+ return 0;
+ }
+ if (gpio_request_by_name_nodev(offset_to_ofnode(node), "gpios", 0,
+ &resin, 0)) {
+ printf("Failed to request key_vol_down button.\n");
+ return 0;
+ }
+ if (dm_gpio_get_value(&resin)) {
+ env_set("key_vol_down", "1");
+ printf("Volume down button pressed\n");
+ } else {
+ env_set("key_vol_down", "0");
+ }
+
+ node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(pon),
+ "key_power");
+ if (node < 0) {
+ printf("Failed to find key_power node. Check device tree\n");
+ return 0;
+ }
+ if (gpio_request_by_name_nodev(offset_to_ofnode(node), "gpios", 0,
+ &resin, 0)) {
+ printf("Failed to request key_power button.\n");
+ return 0;
+ }
+ if (dm_gpio_get_value(&resin)) {
+ env_set("key_power", "1");
+ printf("Power button pressed\n");
+ } else {
+ env_set("key_power", "0");
+ }
+
+ return 0;
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm SDM845 pinctrl
+ *
+ * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
+ *
+ */
+
+#include "pinctrl-snapdragon.h"
+#include <common.h>
+
+#define MAX_PIN_NAME_LEN 32
+static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
+
+static const struct pinctrl_function msm_pinctrl_functions[] = {
+ {"qup9", 1},
+ {"gpio", 0},
+};
+
+static const char *sdm845_get_function_name(struct udevice *dev,
+ unsigned int selector)
+{
+ return msm_pinctrl_functions[selector].name;
+}
+
+static const char *sdm845_get_pin_name(struct udevice *dev,
+ unsigned int selector)
+{
+ snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
+ return pin_name;
+}
+
+static unsigned int sdm845_get_function_mux(unsigned int selector)
+{
+ return msm_pinctrl_functions[selector].val;
+}
+
+struct msm_pinctrl_data sdm845_data = {
+ .pin_count = 150,
+ .functions_count = ARRAY_SIZE(msm_pinctrl_functions),
+ .get_function_name = sdm845_get_function_name,
+ .get_function_mux = sdm845_get_function_mux,
+ .get_pin_name = sdm845_get_pin_name,
+};
static const struct udevice_id msm_pinctrl_ids[] = {
{ .compatible = "qcom,tlmm-apq8016", .data = (ulong)&apq8016_data },
{ .compatible = "qcom,tlmm-apq8096", .data = (ulong)&apq8096_data },
+#ifdef CONFIG_SDM845
+ { .compatible = "qcom,tlmm-sdm845", .data = (ulong)&sdm845_data },
+#endif
{ }
};
extern struct msm_pinctrl_data apq8016_data;
extern struct msm_pinctrl_data apq8096_data;
+extern struct msm_pinctrl_data sdm845_data;
#endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm SDM845 memory map
+ *
+ * (C) Copyright 2021 Dzmitry Sankouski <dsankousk@gmail.com>
+ */
+
+#include <common.h>
+#include <asm/armv8/mmu.h>
+
+static struct mm_region sdm845_mem_map[] = {
+ {
+ .virt = 0x0UL, /* Peripheral block */
+ .phys = 0x0UL, /* Peripheral block */
+ .size = 0x10000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ .virt = 0x80000000UL, /* DDR */
+ .phys = 0x80000000UL, /* DDR */
+ .size = 0x200000000UL, /* 8GiB - maximum allowed memory */
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = sdm845_mem_map;
config STM32MP15x
bool "Support STMicroelectronics STM32MP15x Soc"
- select ARCH_SUPPORT_PSCI if !TFABOOT
- select ARM_SMCCC if TFABOOT
+ select ARCH_SUPPORT_PSCI
+ select BINMAN
select CPU_V7A
- select CPU_V7_HAS_NONSEC if !TFABOOT
+ select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select OF_BOARD_SETUP
select PINCTRL_STM32
select STM32_SERIAL
select SYS_ARCH_TIMER
imply CMD_NVEDIT_INFO
- imply SYSRESET_PSCI if TFABOOT
- imply SYSRESET_SYSCON if !TFABOOT
help
support of STMicroelectronics SOC STM32MP15x family
STM32MP157, STM32MP153 or STM32MP151
config DDR_CACHEABLE_SIZE
hex "Size of the DDR marked cacheable in pre-reloc stage"
- default 0x10000000 if TFABOOT
default 0x40000000
help
Define the size of the DDR marked as cacheable in U-Boot
* Use the saved FDT address provided by TF-A at boot time (NT_FW_CONFIG =
* Non Trusted Firmware configuration file) when the pointer is valid
*/
-void *board_fdt_blob_setup(void)
+void *board_fdt_blob_setup(int *err)
{
log_debug("%s: nt_fw_dtb=%lx\n", __func__, nt_fw_dtb);
+ *err = 0;
/* use external device tree only if address is valid */
if (nt_fw_dtb >= STM32_DDR_BASE) {
if (fdt_magic(nt_fw_dtb) == FDT_MAGIC)
u32 tmp_data = 0;
int ret;
- if (IS_ENABLED(CONFIG_TFABOOT))
+ if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD))
return stm32_smc(STM32_SMC_BSEC,
STM32_SMC_READ_OTP,
otp, 0, val);
{
struct stm32mp_bsec_plat *plat;
- if (IS_ENABLED(CONFIG_TFABOOT))
+ if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD))
return stm32_smc(STM32_SMC_BSEC,
STM32_SMC_READ_SHADOW,
otp, 0, val);
{
struct stm32mp_bsec_plat *plat;
- if (IS_ENABLED(CONFIG_TFABOOT))
+ if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD))
return stm32_smc_exec(STM32_SMC_BSEC,
STM32_SMC_PROG_OTP,
otp, val);
{
struct stm32mp_bsec_plat *plat;
- if (IS_ENABLED(CONFIG_TFABOOT))
+ if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD))
return stm32_smc_exec(STM32_SMC_BSEC,
STM32_SMC_WRITE_SHADOW,
otp, val);
static int stm32mp_bsec_write_lock(struct udevice *dev, u32 val, u32 otp)
{
- if (!IS_ENABLED(CONFIG_TFABOOT))
+ if (!IS_ENABLED(CONFIG_ARM_SMCCC) || IS_ENABLED(CONFIG_SPL_BUILD))
return -ENOTSUPP;
if (val == 1)
/*
* update unlocked shadow for OTP cleared by the rom code
- * only executed in U-Boot proper when TF-A is not used
+ * only executed in SPL, it is done in TF-A for TFABOOT
*/
-
- if (!IS_ENABLED(CONFIG_TFABOOT) && !IS_ENABLED(CONFIG_SPL_BUILD)) {
+ if (IS_ENABLED(CONFIG_SPL_BUILD)) {
plat = dev_get_plat(dev);
for (otp = 57; otp <= BSEC_OTP_MAX_VALUE; otp++)
-
config CMD_STM32PROG
bool "command stm32prog for STM32CudeProgrammer"
select DFU
help
activate the command "stm32prog serial" for STM32MP soc family
with the tools STM32CubeProgrammer using U-Boot serial device
- and UART protocol.
\ No newline at end of file
+ and UART protocol.
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
-#
-# Copyright (C) 2018, STMicroelectronics - All Rights Reserved
-#
-
-ifndef CONFIG_SPL
-INPUTS-$(CONFIG_STM32MP15x_STM32IMAGE) += u-boot.stm32
-else
-ifdef CONFIG_SPL_BUILD
-INPUTS-y += u-boot-spl.stm32
-endif
-endif
-
-MKIMAGEFLAGS_u-boot.stm32 = -T stm32image -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE)
-
-u-boot.stm32: MKIMAGEOUTPUT = u-boot.stm32.log
-
-u-boot.stm32: u-boot.bin FORCE
- $(call if_changed,mkimage)
-
-MKIMAGEFLAGS_u-boot-spl.stm32 = -T stm32image -a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE)
-
-spl/u-boot-spl.stm32: MKIMAGEOUTPUT = spl/u-boot-spl.stm32.log
-
-spl/u-boot-spl.stm32: spl/u-boot-spl.bin FORCE
- $(call if_changed,mkimage)
-
-u-boot-spl.stm32 : spl/u-boot-spl.stm32
- $(call if_changed,copy)
struct lmb lmb;
-#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
-#ifndef CONFIG_TFABOOT
static void security_init(void)
{
/* Disable the backup domain write protection */
writel(BIT(0), RCC_MP_AHB5ENSETR);
writel(0x0, GPIOZ_SECCFGR);
}
-#endif /* CONFIG_TFABOOT */
/*
* Debug init
* done in TF-A for TRUSTED boot and
* DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE
*/
- if (!IS_ENABLED(CONFIG_TFABOOT) && bsec_dbgswenable()) {
+ if (bsec_dbgswenable()) {
setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2);
}
void spl_board_init(void)
{
+ struct udevice *dev;
+ int ret;
+
dbgmcu_init();
+
+ /* force probe of BSEC driver to shadow the upper OTP */
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(stm32mp_bsec), &dev);
+ if (ret)
+ log_warning("BSEC probe failed: %d\n", ret);
}
-#endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
-#if !defined(CONFIG_TFABOOT) && \
- (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
/* get bootmode from ROM code boot context: saved in TAMP register */
static void update_bootmode(void)
{
TAMP_BOOT_MODE_MASK,
boot_mode << TAMP_BOOT_MODE_SHIFT);
}
-#endif
u32 get_bootmode(void)
{
/* early armv7 timer init: needed for polling */
timer_init();
-#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
-#ifndef CONFIG_TFABOOT
- security_init();
- update_bootmode();
-#endif
- /* Reset Coprocessor state unless it wakes up from Standby power mode */
- if (!(readl(PWR_MCUCR) & PWR_MCUCR_SBF)) {
- writel(TAMP_COPRO_STATE_OFF, TAMP_COPRO_STATE);
- writel(0, TAMP_COPRO_RSC_TBL_ADDRESS);
+ if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+ security_init();
+ update_bootmode();
+ }
+/* reset copro state in SPL, when used, or in U-Boot */
+ if (!IS_ENABLED(CONFIG_SPL) || IS_ENABLED(CONFIG_SPL_BUILD)) {
+ /* Reset Coprocessor state unless it wakes up from Standby power mode */
+ if (!(readl(PWR_MCUCR) & PWR_MCUCR_SBF)) {
+ writel(TAMP_COPRO_STATE_OFF, TAMP_COPRO_STATE);
+ writel(0, TAMP_COPRO_RSC_TBL_ADDRESS);
+ }
}
-#endif
boot_mode = get_bootmode();
if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) &&
(boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART)
gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
-#if defined(CONFIG_DEBUG_UART) && \
- !defined(CONFIG_TFABOOT) && \
- (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
- else
+ else if (IS_ENABLED(CONFIG_DEBUG_UART) && IS_ENABLED(CONFIG_SPL_BUILD))
debug_uart_init();
-#endif
return 0;
}
soc_type[type], soc_pkg[pkg], soc_rev[rev]);
}
-#if defined(CONFIG_DISPLAY_CPUINFO)
+/* used when CONFIG_DISPLAY_CPUINFO is activated */
int print_cpuinfo(void)
{
char name[SOC_NAME_SIZE];
return 0;
}
-#endif /* CONFIG_DISPLAY_CPUINFO */
static void setup_boot_mode(void)
{
*/
__weak int setup_mac_address(void)
{
-#if defined(CONFIG_NET)
int ret;
int i;
u32 otp[2];
uchar enetaddr[6];
struct udevice *dev;
+ if (!IS_ENABLED(CONFIG_NET))
+ return 0;
+
/* MAC already in environment */
if (eth_env_get_enetaddr("ethaddr", enetaddr))
return 0;
ret = eth_env_set_enetaddr("ethaddr", enetaddr);
if (ret)
log_err("Failed to set mac address %pM from OTP: %d\n", enetaddr, ret);
-#endif
return 0;
}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2016
- * Vikas Manocha, <vikas.manocha@st.com>
- */
-
-#ifndef _STM32_GPIO_H_
-#define _STM32_GPIO_H_
-#include <asm/gpio.h>
-
-enum stm32_gpio_mode {
- STM32_GPIO_MODE_IN = 0,
- STM32_GPIO_MODE_OUT,
- STM32_GPIO_MODE_AF,
- STM32_GPIO_MODE_AN
-};
-
-enum stm32_gpio_otype {
- STM32_GPIO_OTYPE_PP = 0,
- STM32_GPIO_OTYPE_OD
-};
-
-enum stm32_gpio_speed {
- STM32_GPIO_SPEED_2M = 0,
- STM32_GPIO_SPEED_25M,
- STM32_GPIO_SPEED_50M,
- STM32_GPIO_SPEED_100M
-};
-
-enum stm32_gpio_pupd {
- STM32_GPIO_PUPD_NO = 0,
- STM32_GPIO_PUPD_UP,
- STM32_GPIO_PUPD_DOWN
-};
-
-enum stm32_gpio_af {
- STM32_GPIO_AF0 = 0,
- STM32_GPIO_AF1,
- STM32_GPIO_AF2,
- STM32_GPIO_AF3,
- STM32_GPIO_AF4,
- STM32_GPIO_AF5,
- STM32_GPIO_AF6,
- STM32_GPIO_AF7,
- STM32_GPIO_AF8,
- STM32_GPIO_AF9,
- STM32_GPIO_AF10,
- STM32_GPIO_AF11,
- STM32_GPIO_AF12,
- STM32_GPIO_AF13,
- STM32_GPIO_AF14,
- STM32_GPIO_AF15
-};
-
-struct stm32_gpio_dsc {
- u8 port;
- u8 pin;
-};
-
-struct stm32_gpio_ctl {
- enum stm32_gpio_mode mode;
- enum stm32_gpio_otype otype;
- enum stm32_gpio_speed speed;
- enum stm32_gpio_pupd pupd;
- enum stm32_gpio_af af;
-};
-
-struct stm32_gpio_regs {
- u32 moder; /* GPIO port mode */
- u32 otyper; /* GPIO port output type */
- u32 ospeedr; /* GPIO port output speed */
- u32 pupdr; /* GPIO port pull-up/pull-down */
- u32 idr; /* GPIO port input data */
- u32 odr; /* GPIO port output data */
- u32 bsrr; /* GPIO port bit set/reset */
- u32 lckr; /* GPIO port configuration lock */
- u32 afr[2]; /* GPIO alternate function */
-};
-
-struct stm32_gpio_priv {
- struct stm32_gpio_regs *regs;
- unsigned int gpio_range;
-};
-
-int stm32_offset_to_index(struct udevice *dev, unsigned int offset);
-
-#endif /* _STM32_GPIO_H_ */
}
#endif
+#if !CONFIG_IS_ENABLED(SYSRESET)
void reset_cpu(void)
{
#if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40)
while (1) { }
#endif
}
+#endif
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
void enable_caches(void)
#include <image.h>
#include <log.h>
#include <spl.h>
+#include <asm/arch/spl.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <linux/bitops.h>
int ret = 0;
struct image_header *header;
header = (struct image_header *)(CONFIG_SYS_TEXT_BASE);
+ int load_offset = readl(SPL_ADDR + 0x10);
+
+ load_offset = max(load_offset, CONFIG_SYS_SPI_U_BOOT_OFFS);
spi0_init();
- spi0_read_data((void *)header, CONFIG_SYS_SPI_U_BOOT_OFFS, 0x40);
+ spi0_read_data((void *)header, load_offset, 0x40);
if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
image_get_magic(header) == FDT_MAGIC) {
load.bl_len = 1;
load.read = spi_load_read;
ret = spl_load_simple_fit(spl_image, &load,
- CONFIG_SYS_SPI_U_BOOT_OFFS, header);
+ load_offset, header);
} else {
ret = spl_parse_image_header(spl_image, header);
if (ret)
return ret;
spi0_read_data((void *)spl_image->load_addr,
- CONFIG_SYS_SPI_U_BOOT_OFFS, spl_image->size);
+ load_offset, spl_image->size);
}
spi0_deinit();
# (C) Copyright 2000-2010
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-PLATFORM_CPPFLAGS += -mstring -mcpu=860 -msoft-float
+PLATFORM_CPPFLAGS += -mcpu=860 -msoft-float
* read/writes. We define __arch_*[bl] here, and leave __arch_*w
* to the architecture specific code.
*/
-#define __arch_getb(a) (*(unsigned char *)(a))
-#define __arch_getw(a) (*(unsigned short *)(a))
-#define __arch_getl(a) (*(unsigned int *)(a))
-#define __arch_getq(a) (*(unsigned long long *)(a))
+#define __arch_getb(a) (*(volatile unsigned char *)(a))
+#define __arch_getw(a) (*(volatile unsigned short *)(a))
+#define __arch_getl(a) (*(volatile unsigned int *)(a))
+#define __arch_getq(a) (*(volatile unsigned long long *)(a))
-#define __arch_putb(v, a) (*(unsigned char *)(a) = (v))
-#define __arch_putw(v, a) (*(unsigned short *)(a) = (v))
-#define __arch_putl(v, a) (*(unsigned int *)(a) = (v))
-#define __arch_putq(v, a) (*(unsigned long long *)(a) = (v))
+#define __arch_putb(v, a) (*(volatile unsigned char *)(a) = (v))
+#define __arch_putw(v, a) (*(volatile unsigned short *)(a) = (v))
+#define __arch_putl(v, a) (*(volatile unsigned int *)(a) = (v))
+#define __arch_putq(v, a) (*(volatile unsigned long long *)(a) = (v))
#define __raw_writeb(v, a) __arch_putb(v, a)
#define __raw_writew(v, a) __arch_putw(v, a)
#define __raw_readl(a) __arch_getl(a)
#define __raw_readq(a) __arch_getq(a)
+/* adding for cadence_qspi_apb.c */
+#define memcpy_fromio(a, c, l) memcpy((a), (c), (l))
+#define memcpy_toio(c, a, l) memcpy((c), (a), (l))
+
#define dmb() mb()
#define __iormb() rmb()
#define __iowmb() wmb()
void sbi_set_timer(uint64_t stime_value);
long sbi_get_spec_version(void);
int sbi_get_impl_id(void);
+int sbi_get_impl_version(long *version);
int sbi_probe_extension(int ext);
void sbi_srst_reset(unsigned long type, unsigned long reason);
}
/**
+ * sbi_get_impl_version() - get SBI implementation version
+ *
+ * @version: pointer to receive version
+ * Return: 0 on success, -ENOTSUPP otherwise
+ */
+int sbi_get_impl_version(long *version)
+{
+ struct sbiret ret;
+
+ ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_IMP_VERSION,
+ 0, 0, 0, 0, 0, 0);
+ if (ret.error)
+ return -ENOTSUPP;
+ if (version)
+ *version = ret.value;
+ return 0;
+}
+
+/**
* sbi_probe_extension() - Check if an SBI extension ID is supported or not.
* @extid: The extension ID to be probed.
*
menu "Sandbox architecture"
depends on SANDBOX
+config ARCH_MAP_SYSMEM
+ def_bool y
+
config SYS_ARCH
default "sandbox"
# Copyright (c) 2011 The Chromium OS Authors.
PLATFORM_CPPFLAGS += -D__SANDBOX__ -U_FORTIFY_SOURCE
-PLATFORM_CPPFLAGS += -DCONFIG_ARCH_MAP_SYSMEM
PLATFORM_CPPFLAGS += -fPIC
PLATFORM_LIBS += -lrt
SDL_CONFIG ?= sdl2-config
{
}
-int sandbox_read_fdt_from_file(void)
+void *board_fdt_blob_setup(int *ret)
{
struct sandbox_state *state = state_get_current();
const char *fname = state->fdt_fname;
- void *blob;
+ void *blob = NULL;
loff_t size;
int err;
int fd;
blob = map_sysmem(CONFIG_SYS_FDT_LOAD_ADDR, 0);
+ *ret = 0;
if (!state->fdt_fname) {
err = fdt_create_empty_tree(blob, 256);
if (!err)
goto done;
printf("Unable to create empty FDT: %s\n", fdt_strerror(err));
- return -EINVAL;
+ *ret = -EINVAL;
+ goto fail;
}
err = os_get_filesize(fname, &size);
if (err < 0) {
- printf("Failed to file FDT file '%s'\n", fname);
- return err;
+ printf("Failed to find FDT file '%s'\n", fname);
+ *ret = err;
+ goto fail;
}
fd = os_open(fname, OS_O_RDONLY);
if (fd < 0) {
printf("Failed to open FDT file '%s'\n", fname);
- return -EACCES;
+ *ret = -EACCES;
+ goto fail;
}
+
if (os_read(fd, blob, size) != size) {
os_close(fd);
- return -EIO;
+ printf("Failed to read FDT file '%s'\n", fname);
+ *ret = -EIO;
+ goto fail;
}
os_close(fd);
done:
- gd->fdt_blob = blob;
-
- return 0;
+ return blob;
+fail:
+ return NULL;
}
ulong timer_get_boot_us(void)
vss-microvolts = <0>;
};
+ iommu: iommu@0 {
+ compatible = "sandbox,iommu";
+ #iommu-cells = <0>;
+ };
+
irq: irq {
compatible = "sandbox,irq";
interrupt-controller;
usb_1: usb@1 {
compatible = "sandbox,usb";
+ iommus = <&iommu>;
hub {
compatible = "usb-hub";
usb,device-class = <9>;
void sandbox_set_enable_pci_map(int enable);
/**
- * sandbox_read_fdt_from_file() - Read a device tree from a file
- *
- * Read a device tree file from a host file and set it up for use as the
- * control FDT.
- */
-int sandbox_read_fdt_from_file(void);
-
-/**
* sandbox_reset() - reset sandbox
*
* This functions implements the cold reboot of the sandbox. It relaunches the
# (C) Copyright 2002-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-obj-y += interrupts.o sections.o
+obj-y += fdt_fixup.o interrupts.o sections.o
obj-$(CONFIG_PCI) += pci_io.o
obj-$(CONFIG_CMD_BOOTM) += bootm.o
obj-$(CONFIG_CMD_BOOTZ) += bootm.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+
+#define LOG_CATEGORY LOGC_ARCH
+
+#include <common.h>
+#include <fdt_support.h>
+#include <log.h>
+
+#if defined(__riscv)
+int arch_fixup_fdt(void *blob)
+{
+ int ret;
+
+ ret = fdt_find_or_add_subnode(blob, 0, "chosen");;
+ if (ret < 0)
+ goto err;
+ ret = fdt_setprop_u32(blob, ret, "boot-hartid", 1);
+ if (ret < 0)
+ goto err;
+ return 0;
+err:
+ log_err("Setting /chosen/boot-hartid failed: %s\n", fdt_strerror(ret));
+ return ret;
+}
+#endif
LDFLAGS_EFI_PAYLOAD := -Bsymbolic -Bsymbolic-functions -shared --no-undefined -s
OBJCOPYFLAGS_EFI := -j .text -j .sdata -j .data -j .dynamic -j .dynsym \
- -j .rel -j .rela -j .reloc
+ -j .rel -j .rela -j .reloc --strip-all
# Compiler flags to be added when building UEFI applications
CFLAGS_EFI := -fpic -fshort-wchar
ifeq ($(CONFIG_EFI_APP),y)
PLATFORM_CPPFLAGS += $(CFLAGS_EFI)
-LDFLAGS_FINAL += -znocombreloc -shared -s
+LDFLAGS_FINAL += -znocombreloc -shared
LDSCRIPT := $(LDSCRIPT_EFI)
else
return 0;
}
-#if CONFIG_IS_ENABLED(BOOTSTAGE)
+#if CONFIG_IS_ENABLED(SHOW_BOOT_PROGRESS)
void show_boot_progress(int val)
{
outb(val, POST_PORT);
}
efi_info->efi_memdesc_size = map->desc_size;
efi_info->efi_memdesc_version = map->version;
- efi_info->efi_memmap = (u32)(map->desc);
+ efi_info->efi_memmap = (ulong)(map->desc);
efi_info->efi_memmap_size = size - sizeof(struct efi_entry_memmap);
#ifdef CONFIG_EFI_STUB_64BIT
efi_info->efi_systab_hi = table->sys_table >> 32;
- efi_info->efi_memmap_hi = (u64)(u32)(map->desc) >> 32;
+ efi_info->efi_memmap_hi = (u64)(ulong)map->desc >> 32;
signature = EFI64_LOADER_SIGNATURE;
#else
signature = EFI32_LOADER_SIGNATURE;
#endif
memcpy(&efi_info->efi_loader_signature, signature, 4);
}
+
+void efi_show_bdinfo(void)
+{
+ struct efi_entry_systable *table = NULL;
+ int size, ret;
+
+ ret = efi_info_get(EFIET_SYS_TABLE, (void **)&table, &size);
+ bdinfo_print_num_l("efi_table", (ulong)table);
+}
obj-y += lpc.o
obj-y += lpss.o
obj-$(CONFIG_$(SPL_)INTEL_GENERIC_WIFI) += generic_wifi.o
-ifndef CONFIG_TARGET_EFI_APP
+ifndef CONFIG_EFI_APP
obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += microcode.o
ifndef CONFIG_$(SPL_)X86_64
obj-y += microcode.o
.npins = (e) - (s) + 1, \
}
-/* Now we only support I2C family of pins */
+/* Now we only support SD/SDIO and I2C families of pins */
static struct mrfld_family mrfld_families[] = {
+ MRFLD_FAMILY(3, 37, 56),
MRFLD_FAMILY(7, 101, 114),
};
debug("scu: v: 0x%x p: 0x%x bits: %d, mask: %d bufcfg: 0x%p\n",
v, (u32)bufcfg, bits, mask, bufcfg);
- ret = scu_ipc_raw_command(IPCMSG_INDIRECT_WRITE, 0, &v, 4,
- NULL, 0, (u32)bufcfg, 0);
+ return scu_ipc_raw_command(IPCMSG_INDIRECT_WRITE, 0, &v, 4, NULL, 0, (u32)bufcfg, 0);
+}
+
+static int mrfld_pinconfig(unsigned int pin, u32 mask, u32 bits)
+{
+ struct mrfld_pinctrl *pinctrl;
+ struct udevice *dev;
+ void __iomem *bufcfg;
+ u32 v, value;
+ int ret;
+
+ ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev);
if (ret)
- pr_err("Failed to set mode via SCU for pin %u (%d)\n",
- pin, ret);
+ return ret;
- return ret;
+ pinctrl = dev_get_priv(dev);
+
+ bufcfg = mrfld_get_bufcfg(pinctrl, pin);
+ if (!bufcfg)
+ return -EINVAL;
+
+ value = readl(bufcfg);
+ v = (value & ~mask) | (bits & mask);
+ writel(v, bufcfg);
+
+ debug("v: 0x%x p: 0x%x bits: %d, mask: %d bufcfg: 0x%p\n",
+ v, (u32)bufcfg, bits, mask, bufcfg);
+
+ return 0;
}
static int mrfld_pinctrl_cfg_pin(ofnode pin_node)
u32 mask;
int ret;
- /* For now we only support just protected Family of pins */
- is_protected = ofnode_read_bool(pin_node, "protected");
- if (!is_protected)
- return -ENOTSUPP;
-
pad_offset = ofnode_read_s32_default(pin_node, "pad-offset", -1);
if (pad_offset == -1)
return -EINVAL;
if (mode & ~mask)
return -ENOTSUPP;
- ret = mrfld_pinconfig_protected(pad_offset, mask, mode);
+ is_protected = ofnode_read_bool(pin_node, "protected");
+ if (is_protected)
+ ret = mrfld_pinconfig_protected(pad_offset, mask, mode);
+ else
+ ret = mrfld_pinconfig(pad_offset, mask, mode);
+ if (ret)
+ pr_err("Failed to set mode for pin %u (%d)\n", pad_offset, ret);
return ret;
}
/DISCARD/ : { *(.u_boot_list_2_cmd_*) }
#endif
+#ifdef CONFIG_SYS_TEXT_BASE
. = CONFIG_SYS_TEXT_BASE; /* Location of bootcode in flash */
+#endif
__text_start = .;
.text.start : { *(.text.start); }
#
obj-y += cpu.o interrupts.o setjmp.o
+
+ifndef CONFIG_EFI
+obj-y += misc.o
+endif
#include <cpu_func.h>
#include <debug_uart.h>
#include <init.h>
-
-/*
- * Global declaration of gd.
- *
- * As we write to it before relocation we have to make sure it is not put into
- * a .bss section which may overlap a .rela section. Initialization forces it
- * into a .data section which cannot overlap any .rela section.
- */
-struct global_data *global_data_ptr = (struct global_data *)~0;
-
-void arch_setup_gd(gd_t *new_gd)
-{
- global_data_ptr = new_gd;
-}
+#include <asm/global_data.h>
int cpu_has_64bit(void)
{
return 0;
}
-int misc_init_r(void)
-{
- return 0;
-}
-
-#ifndef CONFIG_SYS_COREBOOT
-int checkcpu(void)
-{
- return 0;
-}
-
-int print_cpuinfo(void)
-{
- return 0;
-}
-#endif
-
int x86_cpu_reinit_f(void)
{
return 0;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <common.h>
+#include <init.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Global declaration of gd.
+ *
+ * As we write to it before relocation we have to make sure it is not put into
+ * a .bss section which may overlap a .rela section. Initialization forces it
+ * into a .data section which cannot overlap any .rela section.
+ */
+struct global_data *global_data_ptr = (struct global_data *)~0;
+
+void arch_setup_gd(gd_t *new_gd)
+{
+ global_data_ptr = new_gd;
+}
+
+int misc_init_r(void)
+{
+ return 0;
+}
+
+#ifndef CONFIG_SYS_COREBOOT
+int checkcpu(void)
+{
+ return 0;
+}
+
+int print_cpuinfo(void)
+{
+ return 0;
+}
+#endif
* Refer to EDS-Vol2-22.3
* [14:8] steps of delay for HS400, each 125ps
* [6:0] steps of delay for SDR104/HS200, each 125ps
+ */
/*
* EMMC TX DATA Delay 2
sdcard: mmc@ff3fa000 {
compatible = "intel,sdhci-tangier";
reg = <0xff3fa000 0x1000>;
+ /*
+ * In the disconnected state of the SD Card Detection pin
+ * the read value is always the same and inverted to what
+ * we are expecting in the code.
+ */
+ cd-inverted;
};
pmu: power@ff00b000 {
reg = <0xff0c0000 0x8000>;
/*
+ * Disconnect SD card detection pin, so it won't affect
+ * the reality on two different PCB designs where it's
+ * using the opposite signaling: Edison/Arduino uses
+ * Active Low, while SparkFun went with Active High.
+ */
+ sd_cd@0 {
+ pad-offset = <37>;
+ mode-func = <3>;
+ };
+
+ /*
* Initial configuration came from the firmware.
* Which quite likely has been used in the phones, where I2C #8,
* that is not part of Atom peripheral, is in use.
compatible = "efi,reset";
u-boot,dm-pre-reloc;
};
+ efi-fb {
+ compatible = "efi-fb";
+ };
+
};
}
})
- Method (_STA)
- {
- Return (STA_VISIBLE)
- }
+ Name (_STA, STA_VISIBLE)
}
Device (SDHC)
})
Name (PSTS, Zero)
- Method (_STA)
- {
- Return (STA_VISIBLE)
- }
+ Name (_STA, STA_VISIBLE)
Method (_PS3, 0, NotSerialized)
{
GPIO
})
- Method (_STA)
- {
- Return (STA_VISIBLE)
- }
+ Name (_STA, STA_VISIBLE)
Method (_RMV, 0, NotSerialized)
{
Device (BRC2)
{
Name (_ADR, 0x02)
- Method (_STA, 0, NotSerialized)
- {
- Return (STA_VISIBLE)
- }
+
+ Name (_STA, STA_VISIBLE)
Method (_RMV, 0, NotSerialized)
{
}
})
- Method (_STA, 0, NotSerialized)
- {
- Return (STA_VISIBLE)
- }
+ Name (_STA, STA_VISIBLE)
}
Device (I2C1)
{
Name (_ADR, 0x00080000)
- Method (_STA, 0, NotSerialized)
- {
- Return (STA_VISIBLE)
- }
+ Name (_STA, STA_VISIBLE)
Name (SSCN, Package ()
{
{
Name (_ADR, 0x00090001)
- Method (_STA, 0, NotSerialized)
- {
- Return (STA_VISIBLE)
- }
+ Name (_STA, STA_VISIBLE)
Name (SSCN, Package ()
{
{
Name (_ADR, 0x000c0000)
- Method (_STA)
- {
- Return (STA_VISIBLE)
- }
+ Name (_STA, STA_VISIBLE)
Name (AVBL, Zero)
Method (_REG, 2, NotSerialized)
^IPC1.PMIC
})
- Method (_STA, 0, NotSerialized)
- {
- Return (STA_VISIBLE)
- }
+ Name (_STA, STA_VISIBLE)
Device (RHUB)
{
{
Name (_ADR, 0x00170000)
- Method (_STA, 0, NotSerialized)
- {
- Return (STA_VISIBLE)
- }
+ Name (_STA, STA_VISIBLE)
}
Device (HSU0)
{
Name (_ADR, 0x00040001)
- Method (_STA, 0, NotSerialized)
- {
- Return (STA_VISIBLE)
- }
+ Name (_STA, STA_VISIBLE)
Device (BTH0)
{
HSU0
})
- Method (_STA, 0, NotSerialized)
- {
- Return (STA_VISIBLE)
- }
+ Name (_STA, STA_VISIBLE)
Name (RBUF, ResourceTemplate()
{
{
Name (_ADR, 0x00130000)
- Method (_STA, 0, NotSerialized)
- {
- Return (STA_VISIBLE)
- }
+ Name (_STA, STA_VISIBLE)
Device (PMIC)
{
IPC1
})
- Method (_STA, 0, NotSerialized)
- {
- Return (STA_VISIBLE)
- }
+ Name (_STA, STA_VISIBLE)
Name (RBUF, ResourceTemplate()
{
Name (_ADR, 0x00150000)
Name (_UID, Zero)
- Method (_STA, 0, NotSerialized)
- {
- Return (STA_VISIBLE)
- }
+ Name (_STA, STA_VISIBLE)
Name (RBUF, ResourceTemplate ()
{
Return (RBUF)
}
- Method (_STA, 0, NotSerialized)
- {
- Return (STA_VISIBLE)
- }
+ Name (_STA, STA_VISIBLE)
}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright Google LLC
+ */
+
+#ifndef _ASM_EFI_H_
+#define _ASM_EFI_H_
+
+struct efi_info;
+struct screen_info;
+
+/**
+ * setup_video() - Set up the screen info in the x86 setup
+ *
+ * This is needed so Linux can use the display (when U-Boot is an EFI payload)
+ *
+ * @efi_info: Pointer to place to put the screen info in the x86 setup base
+ */
+void setup_video(struct screen_info *screen_info);
+
+/**
+ * setup_efi_info() - Set up the EFI info needed by Linux to boot
+ *
+ * This writes a suitable signature, table pointers, memory-map pointer, etc.
+ * These are needed for Linux to boot from U-Boot (when U-Boot is an EFI
+ * payload).
+ *
+ * @efi_info: Pointer to place to put the EFI info in the x86 setup base
+ */
+void setup_efi_info(struct efi_info *efi_info);
+
+/**
+ * efi_show_bdinfo() - Show information about EFI for the 'bdinfo' command
+ *
+ * This looks up the EFI table pointer and shows related info
+ */
+void efi_show_bdinfo(void);
+
+#endif
/* i8254.h Intel 8254 PIT registers */
#ifndef _ASMI386_I8254_H_
-#define _ASMI386_I8954_H_
+#define _ASMI386_I8254_H_
#define PIT_T0 0x00 /* PIT channel 0 count/status */
#define PIT_T1 0x01 /* PIT channel 1 count/status */
*/
void i8254_disable_beep(void);
-#endif /* _ASMI386_I8954_H_ */
+#endif /* _ASMI386_I8254_H_ */
*/
void zimage_dump(struct boot_params *base_ptr);
-void setup_video(struct screen_info *screen_info);
-void setup_efi_info(struct efi_info *efi_info);
-
#endif
# (C) Copyright 2002-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+obj-y += bdinfo.o
ifndef CONFIG_X86_64
ifndef CONFIG_TPL_BUILD
obj-y += bios.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * x86-specific information for the 'bd' command
+ *
+ * Copyright 2021 Google LLC
+ */
+
+#include <common.h>
+#include <efi.h>
+#include <init.h>
+#include <asm/efi.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void arch_print_bdinfo(void)
+{
+ bdinfo_print_num_l("prev table", gd->arch.table);
+
+ if (IS_ENABLED(CONFIG_EFI_STUB))
+ efi_show_bdinfo();
+}
#include <asm/byteorder.h>
#include <asm/bootm.h>
#include <asm/bootparam.h>
+#include <asm/efi.h>
#include <asm/global_data.h>
#ifdef CONFIG_SYS_COREBOOT
#include <asm/arch/timestamp.h>
return 0;
}
-void *board_fdt_blob_setup(void)
+void *board_fdt_blob_setup(int *err)
{
-#if CONFIG_IS_ENABLED(OF_BOARD)
+ *err = 0;
+#if defined(CONFIG_OF_BOARD)
return (void *)(ulong)gd->arch.firmware_fdt_addr;
-#elif CONFIG_IS_ENABLED(OF_SEPARATE)
+#elif defined(CONFIG_OF_SEPARATE)
return (void *)CONFIG_SYS_FDT_BASE;
#else
+ *err = -EINVAL;
return NULL;
#endif
}
int misc_init_r(void)
{
- int ret;
- u8 mac1[6], mac2[6];
+ u8 mac[2][6];
+ int i, ret;
- ret = mbox_sp_get_board_info(NULL, mac1, mac2, NULL, NULL);
+ ret = mbox_sp_get_board_info(NULL, mac[0], mac[1], NULL, NULL);
if (ret < 0) {
printf("Cannot read data from OTP!\n");
return 0;
}
- if (is_valid_ethaddr(mac1) && !env_get("ethaddr"))
- eth_env_set_enetaddr("ethaddr", mac1);
+ for (i = 0; i < 2; ++i) {
+ u8 oldmac[6];
- if (is_valid_ethaddr(mac2) && !env_get("eth1addr"))
- eth_env_set_enetaddr("eth1addr", mac2);
+ if (is_valid_ethaddr(mac[i]) &&
+ !eth_env_get_enetaddr_by_index("eth", i, oldmac))
+ eth_env_set_enetaddr_by_index("eth", i, mac[i]);
+ }
return 0;
}
}
}
-static void mox_print_info(void)
+int show_board_info(void)
{
- int ret, board_version, ram_size;
- u64 serial_number;
+ int i, ret, board_version, ram_size, is_sd;
const char *pub_key;
+ const u8 *topology;
+ u64 serial_number;
+
+ printf("Model: CZ.NIC Turris Mox Board\n");
ret = mbox_sp_get_board_info(&serial_number, NULL, NULL, &board_version,
&ram_size);
- if (ret < 0)
- return;
-
- printf("Turris Mox:\n");
- printf(" Board version: %i\n", board_version);
- printf(" RAM size: %i MiB\n", ram_size);
- printf(" Serial Number: %016llX\n", serial_number);
+ if (ret < 0) {
+ printf(" Cannot read board info: %i\n", ret);
+ } else {
+ printf(" Board version: %i\n", board_version);
+ printf(" RAM size: %i MiB\n", ram_size);
+ printf(" Serial Number: %016llX\n", serial_number);
+ }
pub_key = mox_sp_get_ecdsa_public_key();
if (pub_key)
printf(" ECDSA Public Key: %s\n", pub_key);
else
- printf("Cannot read ECDSA Public Key\n");
-}
-
-int last_stage_init(void)
-{
- int ret, i;
- const u8 *topology;
- int is_sd;
- struct mii_dev *bus;
- struct gpio_desc reset_gpio = {};
-
- mox_print_info();
+ printf(" Cannot read ECDSA Public Key\n");
ret = mox_get_topology(&topology, &module_count, &is_sd);
- if (ret) {
+ if (ret)
printf("Cannot read module topology!\n");
- return 0;
- }
printf(" SD/eMMC version: %s\n", is_sd ? "SD" : "eMMC");
}
}
- /* now check if modules are connected in supported mode */
-
+ /* check if modules are connected in supported mode */
for (i = 0; i < module_count; ++i) {
switch (topology[i]) {
case MOX_MODULE_SFP:
}
}
- /* now configure modules */
+ if (module_count)
+ printf("\n");
+
+ return 0;
+}
+
+int last_stage_init(void)
+{
+ struct gpio_desc reset_gpio = {};
+ /* configure modules */
if (get_reset_gpio(&reset_gpio) < 0)
- return 0;
+ goto handle_reset_btn;
if (peridot > 0) {
if (configure_peridots(&reset_gpio) < 0) {
mdelay(50);
}
+ /*
+ * check if the addresses are set by reading Scratch & Misc register
+ * 0x70 of Peridot (and potentially Topaz) modules
+ */
if (peridot || topaz) {
- /*
- * now check if the addresses are set by reading Scratch & Misc
- * register 0x70 of Peridot (and potentially Topaz) modules
- */
+ struct mii_dev *bus;
bus = miiphy_get_dev_by_name("neta@30000");
if (!bus) {
printf("Cannot get MDIO bus device!\n");
} else {
+ int i;
+
for (i = 0; i < peridot; ++i)
check_switch_address(bus, 0x10 + i);
}
}
- printf("\n");
-
+handle_reset_btn:
handle_reset_button();
return 0;
return dev;
}
-int checkboard(void)
+int show_board_info(void)
{
u32 version_num, serial_num;
int err = 1;
}
out:
- printf("Turris Omnia:\n");
+ printf("Model: Turris Omnia\n");
printf(" RAM size: %i MiB\n", omnia_get_ram_size_gb() * 1024);
if (err)
printf(" Serial Number: unknown\n");
}
}
+static void set_mac_if_invalid(int i, u8 *mac)
+{
+ u8 oldmac[6];
+
+ if (is_valid_ethaddr(mac) &&
+ !eth_env_get_enetaddr_by_index("eth", i, oldmac))
+ eth_env_set_enetaddr_by_index("eth", i, mac);
+}
+
int misc_init_r(void)
{
int err;
mac[4] = mac1[2];
mac[5] = mac1[3];
- if (is_valid_ethaddr(mac))
- eth_env_set_enetaddr("eth1addr", mac);
-
+ set_mac_if_invalid(1, mac);
increment_mac(mac);
-
- if (is_valid_ethaddr(mac))
- eth_env_set_enetaddr("eth2addr", mac);
-
+ set_mac_if_invalid(2, mac);
increment_mac(mac);
-
- if (is_valid_ethaddr(mac))
- eth_env_set_enetaddr("ethaddr", mac);
+ set_mac_if_invalid(0, mac);
out:
return 0;
mtd_probe_devices();
- list_for_each_entry(slave, &mtd->partitions, node) {
+ list_for_each_entry_reverse(slave, &mtd->partitions, node) {
char name[32];
int part;
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
- char *ptr = (char *)&default_environment[0];
+ char *ptr = &default_environment[0];
struct udevice *dev;
struct mmc *mmc_dev;
bool ddr4, emmc;
*
* @return FDT base address received from ATF in x1 register
*/
-void *board_fdt_blob_setup(void)
+void *board_fdt_blob_setup(int *err)
{
+ *err = 0;
return (void *)fdt_base_addr;
}
*
* @return FDT base address received from ATF in x1 register
*/
-void *board_fdt_blob_setup(void)
+void *board_fdt_blob_setup(int *err)
{
+ *err = 0;
return (void *)fdt_base_addr;
}
uboot_entry_t entry;
ulong addr;
void *fdt;
+ int err;
if (argc < 2)
return CMD_RET_USAGE;
addr = hextoul(argv[1], NULL);
- fdt = board_fdt_blob_setup();
+ fdt = board_fdt_blob_setup(&err);
entry = (uboot_entry_t)addr;
flush_cache((ulong)addr, 1 << 20); /* 1MiB should be enough */
dcache_disable();
--- /dev/null
+JetHome JetHub
+M: Vyacheslav Bocharov <adeep@lexina.in>
+S: Maintained
+L: u-boot-amlogic@groups.io
+F: board/amlogic/jethub-j100/
+F: configs/jethub_j100_defconfig
+F: doc/board/amlogic/jethub-j100.rst
+F: include/configs/jethub.h
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2021 Vyacheslav Bocharov
+# Author: Vyacheslav Bocharov <adeep@lexina.in>
+
+obj-y := jethub-j100.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 Vyacheslav Bocharov
+ * Author: Vyacheslav Bocharov <adeep@lexina.in>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <init.h>
+#include <net.h>
+#include <asm/io.h>
+#include <asm/arch/axg.h>
+#include <asm/arch/sm.h>
+#include <asm/arch/eth.h>
+#include <asm/arch/mem.h>
+#include <u-boot/crc.h>
+
+int misc_init_r(void)
+{
+ u8 mac_addr[ARP_HLEN];
+ char serial[SM_SERIAL_SIZE];
+ u32 sid;
+
+ if (!meson_sm_get_serial(serial, SM_SERIAL_SIZE)) {
+ sid = crc32(0, (unsigned char *)serial, SM_SERIAL_SIZE);
+ /* Ensure the NIC specific bytes of the mac are not all 0 */
+ if ((sid & 0xffff) == 0)
+ sid |= 0x800000;
+
+ /* OUI registered MAC address */
+ mac_addr[0] = 0x10;
+ mac_addr[1] = 0x27;
+ mac_addr[2] = 0xBE;
+ mac_addr[3] = (sid >> 16) & 0xff;
+ mac_addr[4] = (sid >> 8) & 0xff;
+ mac_addr[5] = (sid >> 0) & 0xff;
+
+ eth_env_set_enetaddr("ethaddr", mac_addr);
+ }
+
+ return 0;
+}
L: u-boot-amlogic@groups.io
F: board/amlogic/jethub-j80/
F: configs/jethub_j80_defconfig
-F: configs/jethub_j100_defconfig
F: doc/board/amlogic/jethub-j80.rst
-F: doc/board/amlogic/jethub-j100.rst
+F: include/configs/jethub.h
return ~0;
}
-void *board_fdt_blob_setup(void)
+void *board_fdt_blob_setup(int *err)
{
phys_addr_t fdt_rom_addr = find_dtb_in_nor_flash(CONFIG_JUNO_DTB_PART);
- if (fdt_rom_addr == ~0UL)
+ *err = 0;
+ if (fdt_rom_addr == ~0UL) {
+ *err = -ENXIO;
return NULL;
+ }
return (void *)fdt_rom_addr;
}
-if TARGET_BEACON_RZG2H || TARGET_BEACON_RZG2M || TARGET_BEACON_RZG2N
+if TARGET_BEACON_RZG2M
config SYS_SOC
default "rmobile"
S: Maintained
F: board/beacon/beacon-rzg2m/
F: include/configs/beacon-rzg2m.h
-F: configs/r8a774a1_beacon_defconfig
-F: configs/r8a774b1_beacon_defconfig
-F: configs/r8a774e1_beacon_defconfig
+F: configs/rzg2_beacon_defconfig
DECLARE_GLOBAL_DATA_PTR;
-void s_init(void)
-{
-}
-
-/* Kconfig forces this on, so just return 0 */
-int board_early_init_f(void)
-{
- return 0;
-}
-
int board_init(void)
{
/* address of boot parameters */
{
writel(RST_CODE, RST_CA57RESCNT);
}
+
+#if IS_ENABLED(CONFIG_MULTI_DTB_FIT)
+int board_fit_config_name_match(const char *name)
+{
+ if (!strcmp(rzg_get_cpu_name(), "R8A774A1") && !strcmp(name, "r8a774a1-beacon-rzg2m-kit"))
+ return 0;
+
+ if (!strcmp(rzg_get_cpu_name(), "R8A774B1") && !strcmp(name, "r8a774b1-beacon-rzg2n-kit"))
+ return 0;
+
+ if (!strcmp(rzg_get_cpu_name(), "R8A774E1") && !strcmp(name, "r8a774e1-beacon-rzg2h-kit"))
+ return 0;
+
+ return -1;
+}
+#endif
{
u32 chimp_hs = CHIMP_HANDSHAKE_WAIT_TIMEOUT;
- gic_lpi_tables_init();
+ /* FIXME: Need to call gic_lpi_tables_init correctly now */
+ printf("%s: failed to init gic-lpi-tables\n", __func__);
/*
* Check for chimp handshake status.
return 0;
}
-void *board_fdt_blob_setup(void)
+void *board_fdt_blob_setup(int *err)
{
+ *err = 0;
/* Stored the DTB address there during our init */
return (void *)prior_stage_fdt_address;
}
-if TARGET_IMX8MM_CL_IOT_GATE
+if TARGET_IMX8MM_CL_IOT_GATE || TARGET_IMX8MM_CL_IOT_GATE_OPTEE
config SYS_BOARD
default "imx8mm-cl-iot-gate"
F: board/compulab/imx8mm-cl-iot-gate/
F: include/configs/imx8mm-cl-iot-gate.h
F: configs/imx8mm-cl-iot-gate_defconfig
+F: configs/imx8mm-cl-iot-gate-optee_defconfig
#include <common.h>
#include <env.h>
+#include <hang.h>
#include <init.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
+#include "ddr/ddr.h"
+
DECLARE_GLOBAL_DATA_PTR;
+int board_phys_sdram_size(phys_size_t *size)
+{
+ struct lpddr4_tcm_desc *lpddr4_tcm_desc =
+ (struct lpddr4_tcm_desc *)TCM_DATA_CFG;
+
+ switch (lpddr4_tcm_desc->size) {
+ case 4096:
+ case 2048:
+ case 1024:
+ *size = (1L << 20) * lpddr4_tcm_desc->size;
+ break;
+ default:
+ printf("%s: DRAM size %uM is not supported\n",
+ __func__,
+ lpddr4_tcm_desc->size);
+ hang();
+ break;
+ };
+
+ return 0;
+}
+
static int setup_fec(void)
{
if (IS_ENABLED(CONFIG_FEC_MXC)) {
default "dhelectronics"
config SYS_CONFIG_NAME
- default "dh_stm32mp1"
+ default "stm32mp15_dh_dhsom"
config ENV_SECT_SIZE
default 0x10000 if ENV_IS_IN_SPI_FLASH
F: board/dhelectronics/dh_stm32mp1/
F: configs/stm32mp15_dhcom_basic_defconfig
F: configs/stm32mp15_dhcor_basic_defconfig
-F: include/configs/stm32mp1.h
+F: include/configs/stm32mp15_dh_dhsom.h
obj-y += ../../st/common/stpmic1.o board.o
-obj-$(CONFIG_SYS_MTDPARTS_RUNTIME) += ../../st/common/stm32mp_mtdparts.o
obj-$(CONFIG_SET_DFU_ALT_INFO) += ../../st/common/stm32mp_dfu.o
{
gd->ram_size = imx_ddr_size();
+#ifdef CONFIG_OPTEE_TZDRAM_SIZE
+ gd->ram_size -= CONFIG_OPTEE_TZDRAM_SIZE;
+#endif
+
return 0;
}
prompt "Mainboard model"
optional
-config TARGET_EFI_APP
- bool "efi application"
+config TARGET_EFI_APP32
+ bool "32-bit efi application"
+ select EFI_APP
help
This target is used for running U-Boot on top of EFI. In
this case EFI does the early initialisation, and U-Boot
takes over once the RAM, video and CPU are fully running.
U-Boot is loaded as an application from EFI.
+config TARGET_EFI_APP64
+ bool "64-bit efi application"
+ select EFI_APP
+ select X86_64
+ help
+ This target is used for running U-Boot on top of EFI in 64-bit mode.
+ In this case EFI does the early initialisation, and U-Boot
+ takes over once the RAM, video and CPU are fully running.
+ U-Boot is loaded as an application from EFI.
+
config TARGET_EFI_PAYLOAD
bool "efi payload"
help
-if TARGET_EFI_APP
+if EFI_APP
config SYS_BOARD
default "efi-x86_app"
config SYS_CONFIG_NAME
default "efi-x86_app"
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ imply VIDEO_EFI
+
endif
-EFI-X86_APP BOARD
+EFI-X86_APP32 BOARD
M: Simon Glass <sjg@chromium.org>
S: Maintained
F: board/efi/efi-x86_app/
F: include/configs/efi-x86_app.h
-F: configs/efi-x86_app_defconfig
+F: configs/efi-x86_app32_defconfig
+
+EFI-X86_APP64 BOARD
+M: Simon Glass <sjg@chromium.org>
+S: Maintained
+F: board/efi/efi-x86_app/
+F: include/configs/efi-x86_app.h
+F: configs/efi-x86_app64_defconfig
return 0;
}
-void *board_fdt_blob_setup(void)
+void *board_fdt_blob_setup(int *err)
{
+ *err = 0;
/* QEMU loads a generated DTB for us at the start of RAM. */
return (void *)CONFIG_SYS_SDRAM_BASE;
}
*
* @return virtual address of FDT received from QEMU in r3 register
*/
-void *board_fdt_blob_setup(void)
+void *board_fdt_blob_setup(int *err)
{
+ *err = 0;
return get_fdt_virt();
}
}
#endif
-void *board_fdt_blob_setup(void)
+void *board_fdt_blob_setup(int *err)
{
+ *err = 0;
/* Stored the DTB address there during our init */
return (void *)(ulong)gd->arch.firmware_fdt_addr;
}
default "engicam"
config SYS_CONFIG_NAME
- default "stm32mp1"
+ default "stm32mp15_common"
endif
return ret;
ret = algo->hash_init(algo, &ctx);
- if (ret) {
- if (ctx)
- free(ctx);
+ if (ret)
return ret;
- }
-
/* Update hash for ESBC key */
#ifdef CONFIG_KEY_REVOCATION
if (check_srk(img)) {
img->img_key, img->key_len, 1);
if (ret)
return ret;
-
/* Copy hash at destination buffer */
ret = algo->hash_finish(algo, ctx, hash_val, algo->digest_size);
if (ret) {
- if (ctx)
- free(ctx);
+ free(ctx);
return ret;
}
-
for (i = 0; i < SHA256_BYTES; i++)
img->img_key_hash[i] = hash_val[i];
ret = algo->hash_init(algo, &ctx);
/* Copy hash at destination buffer */
- if (ret) {
- free(ctx);
+ if (ret)
return ret;
- }
/* Update hash for CSF Header */
ret = algo->hash_update(algo, ctx,
(u8 *)&img->hdr, sizeof(struct fsl_secboot_img_hdr), 0);
- if (ret) {
- free(ctx);
+ if (ret)
return ret;
- }
/* Update the hash with that of srk table if srk flag is 1
* If IE Table is selected, key is not added in the hash
key_hash = 1;
}
#endif
- if (ret) {
- free(ctx);
+ if (ret)
return ret;
- }
if (!key_hash) {
free(ctx);
return ERROR_KEY_TABLE_NOT_FOUND;
}
-
/* Update hash for actual Image */
ret = algo->hash_update(algo, ctx,
(u8 *)(*(img->img_addr_ptr)), img->img_size, 1);
- if (ret) {
- free(ctx);
+ if (ret)
return ret;
- }
/* Copy hash at destination buffer */
ret = algo->hash_finish(algo, ctx, hash_val, algo->digest_size);
#define __ASSEMBLY__
BOOT_FROM sd
-LOADER mkimage.flash.mkimage 0x7E1000
+LOADER u-boot-spl-ddr.bin 0x7E1000
setbits_le32(&gpr->gpr[1], BIT(22));
}
-#define EQOS_RST_PAD IMX_GPIO_NR(4, 22)
-static iomux_v3_cfg_t const eqos_rst_pads[] = {
- MX8MP_PAD_SAI2_RXC__GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static void setup_iomux_eqos(void)
-{
- imx_iomux_v3_setup_multiple_pads(eqos_rst_pads,
- ARRAY_SIZE(eqos_rst_pads));
-
- gpio_request(EQOS_RST_PAD, "eqos_rst");
- gpio_direction_output(EQOS_RST_PAD, 0);
- mdelay(15);
- gpio_direction_output(EQOS_RST_PAD, 1);
- mdelay(100);
-}
-
static int setup_eqos(void)
{
struct iomuxc_gpr_base_regs *gpr =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
- setup_iomux_eqos();
-
/* set INTF as RGMII, enable RGMII TXC clock */
clrsetbits_le32(&gpr->gpr[1],
IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
if (CONFIG_IS_ENABLED(FEC_MXC)) {
setup_fec();
+ }
- if (CONFIG_IS_ENABLED(DWC_ETH_QOS))
- ret = setup_eqos();
+ if (CONFIG_IS_ENABLED(DWC_ETH_QOS)) {
+ ret = setup_eqos();
}
return ret;
ROM_VERSION v2
BOOT_FROM sd
-LOADER mkimage.flash.mkimage 0x920000
+LOADER u-boot-spl-ddr.bin 0x920000
if (current_el() == 3)
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
-#ifdef CONFIG_ENV_IS_NOWHERE
- gd->env_addr = (ulong)&default_environment[0];
-#endif
-
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif
erratum_a010315();
#endif
-#ifdef CONFIG_ENV_IS_NOWHERE
- gd->env_addr = (ulong)&default_environment[0];
-#endif
-
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif
erratum_a010315();
#endif
-#ifdef CONFIG_ENV_IS_NOWHERE
- gd->env_addr = (ulong)&default_environment[0];
-#endif
-
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif
int board_init(void)
{
-#ifdef CONFIG_ENV_IS_NOWHERE
- gd->env_addr = (ulong)&default_environment[0];
-#endif
-
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
board_retimer_init();
-#ifdef CONFIG_ENV_IS_NOWHERE
- gd->env_addr = (ulong)&default_environment[0];
-#endif
-
#if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
/* invert AQR105 IRQ pins polarity */
out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
FSL_QIXIS_BRDCFG9_QSPI);
#endif
-#ifdef CONFIG_ENV_IS_NOWHERE
- gd->env_addr = (ulong)&default_environment[0];
-#endif
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT
init_final_memctl_regs();
-#ifdef CONFIG_ENV_IS_NOWHERE
- gd->env_addr = (ulong)&default_environment[0];
-#endif
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
#ifdef CONFIG_FSL_QIXIS
#if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
#endif
-#ifdef CONFIG_ENV_IS_NOWHERE
- gd->env_addr = (ulong)&default_environment[0];
-#endif
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
u64 mc_memory_base = 0;
u64 mc_memory_size = 0;
u16 total_memory_banks;
+ int err;
#if CONFIG_IS_ENABLED(TARGET_LX2160ARDB)
u8 board_rev;
#endif
+ err = fdt_increase_size(blob, 512);
+ if (err) {
+ printf("%s fdt_increase_size: err=%s\n", __func__,
+ fdt_strerror(err));
+ return err;
+ }
+
ft_cpu_setup(blob, bd);
fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include <common.h>
/* optimize cpo for erratum A-009942 */
popts->cpo_sample = 0x59;
#else
+ popts->cpo_sample = 0x54;
popts->half_strength_driver_enable = 0;
#endif
/*
struct ventana_board_info ventana_info;
static int board_type;
-#ifdef CONFIG_USB_EHCI_MX6
-/* toggle USB_HUB_RST# for boards that have it; it is not defined in dt */
-int board_ehci_hcd_init(int port)
-{
- int gpio;
-
- /* USB HUB is always on P1 */
- if (port == 0)
- return 0;
-
- /* Reset USB HUB */
- switch (board_type) {
- case GW53xx:
- case GW552x:
- case GW5906:
- gpio = (IMX_GPIO_NR(1, 9));
- break;
- case GW54proto:
- case GW54xx:
- gpio = (IMX_GPIO_NR(1, 16));
- break;
- default:
- return 0;
- }
-
- /* request and toggle hub rst */
- gpio_request(gpio, "usb_hub_rst#");
- gpio_direction_output(gpio, 0);
- mdelay(2);
- gpio_set_value(gpio, 1);
-
- return 0;
-}
-#endif /* CONFIG_USB_EHCI_MX6 */
-
/* configure eth0 PHY board-specific LED behavior */
int board_phy_config(struct phy_device *phydev)
{
imx_enable_hdmi_phy();
}
-static int detect_i2c(struct display_info_t const *dev)
+static int detect_lvds(struct display_info_t const *dev)
{
+ /* only the following boards support LVDS connectors */
+ switch (board_type) {
+ case GW52xx:
+ case GW53xx:
+ case GW54xx:
+ case GW560x:
+ case GW5905:
+ case GW5909:
+ break;
+ default:
+ return 0;
+ }
+
return i2c_set_bus_num(dev->bus) == 0 &&
i2c_probe(dev->addr) == 0;
}
static void enable_lvds(struct display_info_t const *dev)
{
- struct iomuxc *iomux = (struct iomuxc *)
- IOMUXC_BASE_ADDR;
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
u32 reg = readl(&iomux->gpr[2]);
reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
writel(reg, &iomux->gpr[2]);
- /* Enable Backlight */
- gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio");
- gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
+ /* Configure GPIO */
+ switch (board_type) {
+ case GW52xx:
+ case GW53xx:
+ case GW54xx:
+ if (!strncmp(dev->mode.name, "Hannstar", 8)) {
+ SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
+ gpio_request(IMX_GPIO_NR(1, 10), "cabc");
+ gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
+ } else if (!strncmp(dev->mode.name, "DLC", 3)) {
+ SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
+ gpio_request(IMX_GPIO_NR(1, 10), "touch_rst#");
+ gpio_direction_output(IMX_GPIO_NR(1, 10), 1);
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Configure backlight */
gpio_request(IMX_GPIO_NR(1, 18), "bklt_en");
SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
.bus = 2,
.addr = 0x4,
.pixfmt = IPU_PIX_FMT_LVDS666,
- .detect = detect_i2c,
+ .detect = detect_lvds,
.enable = enable_lvds,
.mode = {
.name = "Hannstar-XGA",
/* DLC700JMG-T-4 */
.bus = 2,
.addr = 0x38,
- .detect = NULL,
+ .detect = detect_lvds,
.enable = enable_lvds,
.pixfmt = IPU_PIX_FMT_LVDS666,
.mode = {
.vmode = FB_VMODE_NONINTERLACED
} }, {
/* DLC0700XDP21LF-C-1 */
- .bus = 0,
- .addr = 0,
- .detect = NULL,
+ .bus = 2,
+ .addr = 0x38,
+ .detect = detect_lvds,
.enable = enable_lvds,
.pixfmt = IPU_PIX_FMT_LVDS666,
.mode = {
/* DLC800FIG-T-3 */
.bus = 2,
.addr = 0x14,
- .detect = NULL,
+ .detect = detect_lvds,
.enable = enable_lvds,
.pixfmt = IPU_PIX_FMT_LVDS666,
.mode = {
} }, {
.bus = 2,
.addr = 0x5d,
- .detect = detect_i2c,
+ .detect = detect_lvds,
.enable = enable_lvds,
.pixfmt = IPU_PIX_FMT_LVDS666,
.mode = {
| (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
writel(reg, &iomux->gpr[3]);
-
- /* LVDS Backlight GPIO on LVDS connector - output low */
- SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
- gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
}
#endif /* CONFIG_VIDEO_IPUV3 */
#endif
/*
+ * remove reset gpio control as we configure the PHY registers
+ * for internal delay, LED config, and clock config in the bootloader
+ */
+ i = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-fec");
+ if (i)
+ fdt_delprop(blob, i, "phy-reset-gpios");
+
+ /*
* Peripheral Config:
* remove nodes by alias path if EEPROM config tells us the
* peripheral is not loaded on the board.
printf("%d\n", buf[0] | buf[1] << 8 | buf[2] << 16 | buf[3] << 24);
}
+ /* Display hwmon */
+ gsc_hwmon();
+
return 0;
}
led_default_state();
/* Set board serial/model */
- env_set_ulong("serial#", gsc_get_serial());
+ if (!env_get("serial#"))
+ env_set_ulong("serial#", gsc_get_serial());
env_set("model", gsc_get_model());
/* Set fdt_file vars */
int ft_board_setup(void *blob, struct bd_info *bd)
{
+ int off;
+
/* set board model dt prop */
fdt_setprop_string(blob, 0, "board", gsc_get_model());
+ /* update temp thresholds */
+ off = fdt_path_offset(blob, "/thermal-zones/cpu-thermal/trips");
+ if (off >= 0) {
+ int minc, maxc, prop;
+
+ get_cpu_temp_grade(&minc, &maxc);
+ fdt_for_each_subnode(prop, blob, off) {
+ const char *type = fdt_getprop(blob, prop, "type", NULL);
+
+ if (type && (!strcmp("critical", type)))
+ fdt_setprop_u32(blob, prop, "temperature", maxc * 1000);
+ else if (type && (!strcmp("passive", type)))
+ fdt_setprop_u32(blob, prop, "temperature", (maxc - 10) * 1000);
+ }
+ }
+
return 0;
}
}
#endif
-void *board_fdt_blob_setup(void)
+void *board_fdt_blob_setup(int *err)
{
+ *err = 0;
/*
* The ECME management processor loads the DTB from NOR flash
* into DRAM (at 4KB), where it gets patched to contain the
--- /dev/null
+if TARGET_KONTRON_MX6UL
+
+config SYS_BOARD
+ string
+ default "sl-mx6ul"
+
+config SYS_VENDOR
+ string
+ default "kontron"
+
+config SYS_CONFIG_NAME
+ string
+ default "kontron-sl-mx6ul"
+
+endif
--- /dev/null
+Kontron SL/BL i.MX6UL/ULL Boards (N63xx/N64xx)
+M: Frieder Schrempf <frieder.schrempf@kontron.de>
+S: Maintained
+F: arch/arm/dts/imx6ul-kontron-n6*
+F: arch/arm/dts/imx6ull-kontron-n6*
+F: board/kontron/sl-mx6ul
+F: configs/kontron-sl-mx6ul_defconfig
+F: doc/board/kontron/sl-mx6ul.rst
+F: include/configs/kontron-sl-mx6ul.h
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# (C) Copyright 2018 Kontron Electronics GmbH
+
+ifdef CONFIG_SPL_BUILD
+obj-y := spl.o
+else
+obj-y := sl-mx6ul.o
+endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <fdt_support.h>
+#include <phy.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ gd->ram_size = imx_ddr_size();
+
+ return 0;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ /*
+ * Overwrite the memory size in the devicetree that is
+ * passed to the kernel with the actual size detected.
+ */
+ return fdt_fixup_memory(blob, PHYS_SDRAM, gd->ram_size);
+}
+
+static int setup_fec(void)
+{
+ struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ int ret;
+
+ /*
+ * Use 50M anatop loopback REF_CLK1 for ENET1,
+ * clear gpr1[13], set gpr1[17].
+ */
+ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
+ IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
+
+ /*
+ * Use 50M anatop loopback REF_CLK2 for ENET2,
+ * clear gpr1[14], set gpr1[18].
+ */
+ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
+ IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
+
+ ret = enable_fec_anatop_clock(0, ENET_50MHZ);
+ if (ret)
+ return ret;
+
+ ret = enable_fec_anatop_clock(1, ENET_50MHZ);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ enable_qspi_clk(0);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ setup_fec();
+
+ return 0;
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <fsl_esdhc_imx.h>
+#include <init.h>
+#include <linux/delay.h>
+#include <linux/sizes.h>
+#include <linux/errno.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+ BOARD_TYPE_KTN_N631X = 1,
+ BOARD_TYPE_KTN_N641X,
+ BOARD_TYPE_MAX
+};
+
+#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#include <spl.h>
+#include <asm/arch/mx6-ddr.h>
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+ MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+ /* CD */
+ MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(USDHC_CD_PAD_CTRL),
+};
+
+#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19)
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+ MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ /* RST */
+ MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+#define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10)
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+ {USDHC1_BASE_ADDR, 0, 4},
+ {USDHC2_BASE_ADDR, 0, 4},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC1_BASE_ADDR:
+ ret = !gpio_get_value(USDHC1_CD_GPIO);
+ break;
+ case USDHC2_BASE_ADDR:
+ // This SDHC interface does not use a CD pin
+ ret = 1;
+ break;
+ }
+
+ return ret;
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+ int i, ret;
+
+ /*
+ * According to the board_mmc_init() the following map is done:
+ * (U-boot device node) (Physical Port)
+ * mmc0 USDHC1
+ * mmc1 USDHC2
+ */
+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ switch (i) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+ gpio_direction_input(USDHC1_CD_GPIO);
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ break;
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ gpio_direction_output(USDHC2_PWR_GPIO, 0);
+ udelay(500);
+ gpio_direction_output(USDHC2_PWR_GPIO, 1);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n",
+ i + 1);
+ return -EINVAL;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ if (ret) {
+ printf("Warning: failed to initialize mmc dev %d\n", i);
+ return ret;
+ }
+ }
+ return 0;
+}
+
+iomux_v3_cfg_t const ecspi2_pads[] = {
+ MX6_PAD_CSI_DATA00__ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_CSI_DATA02__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_CSI_DATA03__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_CSI_DATA01__GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+int board_spi_cs_gpio(unsigned int bus, unsigned int cs)
+{
+ return (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS)
+ ? (IMX_GPIO_NR(4, 22)) : -1;
+}
+
+static void setup_spi(void)
+{
+ gpio_request(IMX_GPIO_NR(4, 22), "spi2_cs0");
+ gpio_direction_output(IMX_GPIO_NR(4, 22), 1);
+ imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads));
+
+ enable_spi_clk(true, 1);
+}
+
+static iomux_v3_cfg_t const uart4_pads[] = {
+ MX6_PAD_UART4_TX_DATA__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_UART4_RX_DATA__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
+}
+
+// DDR 256MB (Hynix H5TQ2G63DFR)
+static struct mx6_ddr3_cfg mem_256M_ddr = {
+ .mem_speed = 800,
+ .density = 2,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 14,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1350,
+ .trcmin = 4950,
+ .trasmin = 3600,
+};
+
+static struct mx6_mmdc_calibration mx6_mmcd_256M_calib = {
+ .p0_mpwldectrl0 = 0x00000000,
+ .p0_mpdgctrl0 = 0x01340134,
+ .p0_mprddlctl = 0x40405052,
+ .p0_mpwrdlctl = 0x40404E48,
+};
+
+// DDR 512MB (Hynix H5TQ4G63DFR)
+static struct mx6_ddr3_cfg mem_512M_ddr = {
+ .mem_speed = 800,
+ .density = 4,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 15,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1350,
+ .trcmin = 4950,
+ .trasmin = 3600,
+};
+
+static struct mx6_mmdc_calibration mx6_mmcd_512M_calib = {
+ .p0_mpwldectrl0 = 0x00000000,
+ .p0_mpdgctrl0 = 0X01440144,
+ .p0_mprddlctl = 0x40405454,
+ .p0_mpwrdlctl = 0x40404E4C,
+};
+
+// Common DDR parameters (256MB and 512MB)
+static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
+ .grp_addds = 0x00000028,
+ .grp_ddrmode_ctl = 0x00020000,
+ .grp_b0ds = 0x00000028,
+ .grp_ctlds = 0x00000028,
+ .grp_b1ds = 0x00000028,
+ .grp_ddrpke = 0x00000000,
+ .grp_ddrmode = 0x00020000,
+ .grp_ddr_type = 0x000c0000,
+};
+
+static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
+ .dram_dqm0 = 0x00000028,
+ .dram_dqm1 = 0x00000028,
+ .dram_ras = 0x00000028,
+ .dram_cas = 0x00000028,
+ .dram_odt0 = 0x00000028,
+ .dram_odt1 = 0x00000028,
+ .dram_sdba2 = 0x00000000,
+ .dram_sdclk_0 = 0x00000028,
+ .dram_sdqs0 = 0x00000028,
+ .dram_sdqs1 = 0x00000028,
+ .dram_reset = 0x00000028,
+};
+
+struct mx6_ddr_sysinfo ddr_sysinfo = {
+ .dsize = 0,
+ .cs_density = 20,
+ .ncs = 1,
+ .cs1_mirror = 0,
+ .rtt_wr = 2,
+ .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
+ .walat = 1, /* Write additional latency */
+ .ralat = 5, /* Read additional latency */
+ .mif3_mode = 3, /* Command prediction working mode */
+ .bi_on = 1, /* Bank interleaving enabled */
+ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
+ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
+ .ddr_type = DDR_TYPE_DDR3,
+ .refsel = 0, /* Refresh cycles at 64KHz */
+ .refr = 1, /* 2 refresh commands per refresh cycle */
+};
+
+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ writel(0xFFFFFFFF, &ccm->CCGR0);
+ writel(0xFFFFFFFF, &ccm->CCGR1);
+ writel(0xFFFFFFFF, &ccm->CCGR2);
+ writel(0xFFFFFFFF, &ccm->CCGR3);
+ writel(0xFFFFFFFF, &ccm->CCGR4);
+ writel(0xFFFFFFFF, &ccm->CCGR5);
+ writel(0xFFFFFFFF, &ccm->CCGR6);
+ writel(0xFFFFFFFF, &ccm->CCGR7);
+}
+
+static void spl_dram_init(void)
+{
+ unsigned int size;
+
+ // DDR RAM connection is always 16 bit wide. Init IOs.
+ mx6ul_dram_iocfg(16, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+
+ // Try to detect the 512MB RAM chip first.
+ mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_512M_calib, &mem_512M_ddr);
+
+ // Get the available RAM size
+ size = get_ram_size((void *)PHYS_SDRAM, SZ_512M);
+
+ gd->ram_size = size;
+
+ if (size == SZ_512M) {
+ // 512MB RAM was detected
+ return;
+ } else if (size == SZ_256M) {
+ // 256MB RAM was detected, use correct config and calibration
+ mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_256M_calib, &mem_256M_ddr);
+ } else {
+ printf("Invalid DDR RAM size detected: %x\n", size);
+ }
+}
+
+static int do_board_detect(void)
+{
+ if (is_mx6ul())
+ gd->board_type = BOARD_TYPE_KTN_N631X;
+ else if (is_mx6ull())
+ gd->board_type = BOARD_TYPE_KTN_N641X;
+
+ printf("Kontron SL i.MX6UL%s (N6%s1x) module, %lu MB RAM detected\n",
+ is_mx6ull() ? "L" : "", is_mx6ull() ? "4" : "3", gd->ram_size / SZ_1M);
+
+ return 0;
+}
+
+void board_init_f(ulong dummy)
+{
+ ccgr_init();
+
+ /* setup AIPS and disable watchdog */
+ arch_cpu_init();
+
+ /* iomux and setup of UART and SPI */
+ board_early_init_f();
+
+ /* setup GP timer */
+ timer_init();
+
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ /* Detect the board type */
+ do_board_detect();
+
+ /* load/boot image from boot device */
+ board_init_r(NULL, 0);
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+ u32 bootdev = spl_boot_device();
+
+ /*
+ * The default boot fuse settings use the SD card (MMC1) as primary
+ * boot device, but allow SPI NOR as a fallback boot device.
+ * We can't detect the fallback case and spl_boot_device() will return
+ * BOOT_DEVICE_MMC1 despite the actual boot device being SPI NOR.
+ * Therefore we try to load U-Boot proper vom SPI NOR after loading
+ * from MMC has failed.
+ */
+ spl_boot_list[0] = bootdev;
+
+ switch (bootdev) {
+ case BOOT_DEVICE_MMC1:
+ case BOOT_DEVICE_MMC2:
+ spl_boot_list[1] = BOOT_DEVICE_SPI;
+ break;
+ }
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+ setup_spi();
+
+ return 0;
+}
+
+int board_fit_config_name_match(const char *name)
+{
+ if (gd->board_type == BOARD_TYPE_KTN_N631X && is_mx6ul() &&
+ !strcmp(name, "imx6ul-kontron-n631x-s"))
+ return 0;
+
+ if (gd->board_type == BOARD_TYPE_KTN_N641X && is_mx6ull() &&
+ !strcmp(name, "imx6ull-kontron-n641x-s"))
+ return 0;
+
+ return -1;
+}
--- /dev/null
+if TARGET_KONTRON_MX8MM
+
+config SYS_BOARD
+ string
+ default "sl-mx8mm"
+
+config SYS_VENDOR
+ string
+ default "kontron"
+
+config SYS_CONFIG_NAME
+ string
+ default "kontron-sl-mx8mm"
+
+endif
--- /dev/null
+Kontron SL/BL i.MX8M Mini Boards (N801x)
+M: Frieder Schrempf <frieder.schrempf@kontron.de>
+S: Maintained
+F: arch/arm/dts/imx8mm-kontron-n801x-*
+F: board/kontron/sl-mx8mm
+F: configs/kontron-sl-mx8mm_defconfig
+F: doc/board/kontron/sl-mx8mm.rst
+F: include/configs/kontron-sl-mx8mm.h
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# (C) Copyright 2019 Kontron Electronics GmbH
+
+obj-y := sl-mx8mm.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
+endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Kontron Electronics GmbH
+ */
+
+#define __ASSEMBLY__
+
+BOOT_FROM sd
+LOADER u-boot-spl-ddr.bin 0x7E1000
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Kontron Electronics GmbH
+ */
+
+#include <linux/kernel.h>
+#include <common.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/lpddr4_define.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+ /** Initialize DDRC registers **/
+ {0x3d400304, 0x1},
+ {0x3d400030, 0x1},
+ {0x3d400000, 0xa3080020},
+ {0x3d400020, 0x223},
+ {0x3d400024, 0x3a980},
+ {0x3d400064, 0x5b0087},
+ {0x3d4000d0, 0xc00305ba},
+ {0x3d4000d4, 0x940000},
+ {0x3d4000dc, 0xd4002d},
+ {0x3d4000e0, 0x310000},
+ {0x3d4000e8, 0x66004d},
+ {0x3d4000ec, 0x16004d},
+ {0x3d400100, 0x191e1920},
+ {0x3d400104, 0x60630},
+ {0x3d40010c, 0xb0b000},
+ {0x3d400110, 0xe04080e},
+ {0x3d400114, 0x2040c0c},
+ {0x3d400118, 0x1010007},
+ {0x3d40011c, 0x401},
+ {0x3d400130, 0x20600},
+ {0x3d400134, 0xc100002},
+ {0x3d400138, 0xd8},
+ {0x3d400144, 0x96004b},
+ {0x3d400180, 0x2ee0017},
+ {0x3d400184, 0x2605b8e},
+ {0x3d400188, 0x0},
+ {0x3d400190, 0x497820a},
+ {0x3d400194, 0x80303},
+ {0x3d4001b4, 0x170a},
+ {0x3d4001a0, 0xe0400018},
+ {0x3d4001a4, 0xdf00e4},
+ {0x3d4001a8, 0x80000000},
+ {0x3d4001b0, 0x11},
+ {0x3d4001c0, 0x1},
+ {0x3d4001c4, 0x1},
+ {0x3d4000f4, 0xc99},
+ {0x3d400108, 0x70e1617},
+ {0x3d400200, 0x17},
+ {0x3d40020c, 0x0},
+ {0x3d400210, 0x1f1f},
+ {0x3d400204, 0x80808},
+ {0x3d400214, 0x7070707},
+ {0x3d400218, 0x7070707},
+ {0x3d400250, 0x29001701},
+ {0x3d400254, 0x2c},
+ {0x3d40025c, 0x4000030},
+ {0x3d400264, 0x900093e7},
+ {0x3d40026c, 0x2005574},
+ {0x3d400400, 0x111},
+ {0x3d400408, 0x72ff},
+ {0x3d400494, 0x2100e07},
+ {0x3d400498, 0x620096},
+ {0x3d40049c, 0x1100e07},
+ {0x3d4004a0, 0xc8012c},
+ {0x3d402020, 0x21},
+ {0x3d402024, 0x7d00},
+ {0x3d402050, 0x20d040},
+ {0x3d402064, 0xc001c},
+ {0x3d4020dc, 0x840000},
+ {0x3d4020e0, 0x310000},
+ {0x3d4020e8, 0x66004d},
+ {0x3d4020ec, 0x16004d},
+ {0x3d402100, 0xa040305},
+ {0x3d402104, 0x30407},
+ {0x3d402108, 0x203060b},
+ {0x3d40210c, 0x505000},
+ {0x3d402110, 0x2040202},
+ {0x3d402114, 0x2030202},
+ {0x3d402118, 0x1010004},
+ {0x3d40211c, 0x301},
+ {0x3d402130, 0x20300},
+ {0x3d402134, 0xa100002},
+ {0x3d402138, 0x1d},
+ {0x3d402144, 0x14000a},
+ {0x3d402180, 0x640004},
+ {0x3d402190, 0x3818200},
+ {0x3d402194, 0x80303},
+ {0x3d4021b4, 0x100},
+ {0x3d403020, 0x21},
+ {0x3d403024, 0x1f40},
+ {0x3d403050, 0x20d040},
+ {0x3d403064, 0x30007},
+ {0x3d4030dc, 0x840000},
+ {0x3d4030e0, 0x310000},
+ {0x3d4030e8, 0x66004d},
+ {0x3d4030ec, 0x16004d},
+ {0x3d403100, 0xa010102},
+ {0x3d403104, 0x30404},
+ {0x3d403108, 0x203060b},
+ {0x3d40310c, 0x505000},
+ {0x3d403110, 0x2040202},
+ {0x3d403114, 0x2030202},
+ {0x3d403118, 0x1010004},
+ {0x3d40311c, 0x301},
+ {0x3d403130, 0x20300},
+ {0x3d403134, 0xa100002},
+ {0x3d403138, 0x8},
+ {0x3d403144, 0x50003},
+ {0x3d403180, 0x190004},
+ {0x3d403190, 0x3818200},
+ {0x3d403194, 0x80303},
+ {0x3d4031b4, 0x100},
+ {0x3d400028, 0x0},
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ {0x100a0, 0x0},
+ {0x100a1, 0x1},
+ {0x100a2, 0x2},
+ {0x100a3, 0x3},
+ {0x100a4, 0x4},
+ {0x100a5, 0x5},
+ {0x100a6, 0x6},
+ {0x100a7, 0x7},
+ {0x110a0, 0x0},
+ {0x110a1, 0x1},
+ {0x110a2, 0x3},
+ {0x110a3, 0x4},
+ {0x110a4, 0x5},
+ {0x110a5, 0x2},
+ {0x110a6, 0x7},
+ {0x110a7, 0x6},
+ {0x120a0, 0x0},
+ {0x120a1, 0x1},
+ {0x120a2, 0x3},
+ {0x120a3, 0x2},
+ {0x120a4, 0x5},
+ {0x120a5, 0x4},
+ {0x120a6, 0x7},
+ {0x120a7, 0x6},
+ {0x130a0, 0x0},
+ {0x130a1, 0x1},
+ {0x130a2, 0x2},
+ {0x130a3, 0x3},
+ {0x130a4, 0x4},
+ {0x130a5, 0x5},
+ {0x130a6, 0x6},
+ {0x130a7, 0x7},
+ {0x1005f, 0x1ff},
+ {0x1015f, 0x1ff},
+ {0x1105f, 0x1ff},
+ {0x1115f, 0x1ff},
+ {0x1205f, 0x1ff},
+ {0x1215f, 0x1ff},
+ {0x1305f, 0x1ff},
+ {0x1315f, 0x1ff},
+ {0x11005f, 0x1ff},
+ {0x11015f, 0x1ff},
+ {0x11105f, 0x1ff},
+ {0x11115f, 0x1ff},
+ {0x11205f, 0x1ff},
+ {0x11215f, 0x1ff},
+ {0x11305f, 0x1ff},
+ {0x11315f, 0x1ff},
+ {0x21005f, 0x1ff},
+ {0x21015f, 0x1ff},
+ {0x21105f, 0x1ff},
+ {0x21115f, 0x1ff},
+ {0x21205f, 0x1ff},
+ {0x21215f, 0x1ff},
+ {0x21305f, 0x1ff},
+ {0x21315f, 0x1ff},
+ {0x55, 0x1ff},
+ {0x1055, 0x1ff},
+ {0x2055, 0x1ff},
+ {0x3055, 0x1ff},
+ {0x4055, 0x1ff},
+ {0x5055, 0x1ff},
+ {0x6055, 0x1ff},
+ {0x7055, 0x1ff},
+ {0x8055, 0x1ff},
+ {0x9055, 0x1ff},
+ {0x200c5, 0x19},
+ {0x1200c5, 0x7},
+ {0x2200c5, 0x7},
+ {0x2002e, 0x2},
+ {0x12002e, 0x2},
+ {0x22002e, 0x2},
+ {0x90204, 0x0},
+ {0x190204, 0x0},
+ {0x290204, 0x0},
+ {0x20024, 0x1ab},
+ {0x2003a, 0x0},
+ {0x120024, 0x1ab},
+ {0x2003a, 0x0},
+ {0x220024, 0x1ab},
+ {0x2003a, 0x0},
+ {0x20056, 0x3},
+ {0x120056, 0x3},
+ {0x220056, 0x3},
+ {0x1004d, 0xe00},
+ {0x1014d, 0xe00},
+ {0x1104d, 0xe00},
+ {0x1114d, 0xe00},
+ {0x1204d, 0xe00},
+ {0x1214d, 0xe00},
+ {0x1304d, 0xe00},
+ {0x1314d, 0xe00},
+ {0x11004d, 0xe00},
+ {0x11014d, 0xe00},
+ {0x11104d, 0xe00},
+ {0x11114d, 0xe00},
+ {0x11204d, 0xe00},
+ {0x11214d, 0xe00},
+ {0x11304d, 0xe00},
+ {0x11314d, 0xe00},
+ {0x21004d, 0xe00},
+ {0x21014d, 0xe00},
+ {0x21104d, 0xe00},
+ {0x21114d, 0xe00},
+ {0x21204d, 0xe00},
+ {0x21214d, 0xe00},
+ {0x21304d, 0xe00},
+ {0x21314d, 0xe00},
+ {0x10049, 0xeba},
+ {0x10149, 0xeba},
+ {0x11049, 0xeba},
+ {0x11149, 0xeba},
+ {0x12049, 0xeba},
+ {0x12149, 0xeba},
+ {0x13049, 0xeba},
+ {0x13149, 0xeba},
+ {0x110049, 0xeba},
+ {0x110149, 0xeba},
+ {0x111049, 0xeba},
+ {0x111149, 0xeba},
+ {0x112049, 0xeba},
+ {0x112149, 0xeba},
+ {0x113049, 0xeba},
+ {0x113149, 0xeba},
+ {0x210049, 0xeba},
+ {0x210149, 0xeba},
+ {0x211049, 0xeba},
+ {0x211149, 0xeba},
+ {0x212049, 0xeba},
+ {0x212149, 0xeba},
+ {0x213049, 0xeba},
+ {0x213149, 0xeba},
+ {0x43, 0x63},
+ {0x1043, 0x63},
+ {0x2043, 0x63},
+ {0x3043, 0x63},
+ {0x4043, 0x63},
+ {0x5043, 0x63},
+ {0x6043, 0x63},
+ {0x7043, 0x63},
+ {0x8043, 0x63},
+ {0x9043, 0x63},
+ {0x20018, 0x3},
+ {0x20075, 0x4},
+ {0x20050, 0x0},
+ {0x20008, 0x2ee},
+ {0x120008, 0x64},
+ {0x220008, 0x19},
+ {0x20088, 0x9},
+ {0x200b2, 0xdc},
+ {0x10043, 0x5a1},
+ {0x10143, 0x5a1},
+ {0x11043, 0x5a1},
+ {0x11143, 0x5a1},
+ {0x12043, 0x5a1},
+ {0x12143, 0x5a1},
+ {0x13043, 0x5a1},
+ {0x13143, 0x5a1},
+ {0x1200b2, 0xdc},
+ {0x110043, 0x5a1},
+ {0x110143, 0x5a1},
+ {0x111043, 0x5a1},
+ {0x111143, 0x5a1},
+ {0x112043, 0x5a1},
+ {0x112143, 0x5a1},
+ {0x113043, 0x5a1},
+ {0x113143, 0x5a1},
+ {0x2200b2, 0xdc},
+ {0x210043, 0x5a1},
+ {0x210143, 0x5a1},
+ {0x211043, 0x5a1},
+ {0x211143, 0x5a1},
+ {0x212043, 0x5a1},
+ {0x212143, 0x5a1},
+ {0x213043, 0x5a1},
+ {0x213143, 0x5a1},
+ {0x200fa, 0x1},
+ {0x1200fa, 0x1},
+ {0x2200fa, 0x1},
+ {0x20019, 0x1},
+ {0x120019, 0x1},
+ {0x220019, 0x1},
+ {0x200f0, 0x660},
+ {0x200f1, 0x0},
+ {0x200f2, 0x4444},
+ {0x200f3, 0x8888},
+ {0x200f4, 0x5665},
+ {0x200f5, 0x0},
+ {0x200f6, 0x0},
+ {0x200f7, 0xf000},
+ {0x20025, 0x0},
+ {0x2002d, 0x0},
+ {0x12002d, 0x0},
+ {0x22002d, 0x0},
+ {0x200c7, 0x21},
+ {0x1200c7, 0x21},
+ {0x2200c7, 0x21},
+ {0x200ca, 0x24},
+ {0x1200ca, 0x24},
+ {0x2200ca, 0x24},
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ { 0x200b2, 0x0 },
+ { 0x1200b2, 0x0 },
+ { 0x2200b2, 0x0 },
+ { 0x200cb, 0x0 },
+ { 0x10043, 0x0 },
+ { 0x110043, 0x0 },
+ { 0x210043, 0x0 },
+ { 0x10143, 0x0 },
+ { 0x110143, 0x0 },
+ { 0x210143, 0x0 },
+ { 0x11043, 0x0 },
+ { 0x111043, 0x0 },
+ { 0x211043, 0x0 },
+ { 0x11143, 0x0 },
+ { 0x111143, 0x0 },
+ { 0x211143, 0x0 },
+ { 0x12043, 0x0 },
+ { 0x112043, 0x0 },
+ { 0x212043, 0x0 },
+ { 0x12143, 0x0 },
+ { 0x112143, 0x0 },
+ { 0x212143, 0x0 },
+ { 0x13043, 0x0 },
+ { 0x113043, 0x0 },
+ { 0x213043, 0x0 },
+ { 0x13143, 0x0 },
+ { 0x113143, 0x0 },
+ { 0x213143, 0x0 },
+ { 0x80, 0x0 },
+ { 0x100080, 0x0 },
+ { 0x200080, 0x0 },
+ { 0x1080, 0x0 },
+ { 0x101080, 0x0 },
+ { 0x201080, 0x0 },
+ { 0x2080, 0x0 },
+ { 0x102080, 0x0 },
+ { 0x202080, 0x0 },
+ { 0x3080, 0x0 },
+ { 0x103080, 0x0 },
+ { 0x203080, 0x0 },
+ { 0x4080, 0x0 },
+ { 0x104080, 0x0 },
+ { 0x204080, 0x0 },
+ { 0x5080, 0x0 },
+ { 0x105080, 0x0 },
+ { 0x205080, 0x0 },
+ { 0x6080, 0x0 },
+ { 0x106080, 0x0 },
+ { 0x206080, 0x0 },
+ { 0x7080, 0x0 },
+ { 0x107080, 0x0 },
+ { 0x207080, 0x0 },
+ { 0x8080, 0x0 },
+ { 0x108080, 0x0 },
+ { 0x208080, 0x0 },
+ { 0x9080, 0x0 },
+ { 0x109080, 0x0 },
+ { 0x209080, 0x0 },
+ { 0x10080, 0x0 },
+ { 0x110080, 0x0 },
+ { 0x210080, 0x0 },
+ { 0x10180, 0x0 },
+ { 0x110180, 0x0 },
+ { 0x210180, 0x0 },
+ { 0x11080, 0x0 },
+ { 0x111080, 0x0 },
+ { 0x211080, 0x0 },
+ { 0x11180, 0x0 },
+ { 0x111180, 0x0 },
+ { 0x211180, 0x0 },
+ { 0x12080, 0x0 },
+ { 0x112080, 0x0 },
+ { 0x212080, 0x0 },
+ { 0x12180, 0x0 },
+ { 0x112180, 0x0 },
+ { 0x212180, 0x0 },
+ { 0x13080, 0x0 },
+ { 0x113080, 0x0 },
+ { 0x213080, 0x0 },
+ { 0x13180, 0x0 },
+ { 0x113180, 0x0 },
+ { 0x213180, 0x0 },
+ { 0x10081, 0x0 },
+ { 0x110081, 0x0 },
+ { 0x210081, 0x0 },
+ { 0x10181, 0x0 },
+ { 0x110181, 0x0 },
+ { 0x210181, 0x0 },
+ { 0x11081, 0x0 },
+ { 0x111081, 0x0 },
+ { 0x211081, 0x0 },
+ { 0x11181, 0x0 },
+ { 0x111181, 0x0 },
+ { 0x211181, 0x0 },
+ { 0x12081, 0x0 },
+ { 0x112081, 0x0 },
+ { 0x212081, 0x0 },
+ { 0x12181, 0x0 },
+ { 0x112181, 0x0 },
+ { 0x212181, 0x0 },
+ { 0x13081, 0x0 },
+ { 0x113081, 0x0 },
+ { 0x213081, 0x0 },
+ { 0x13181, 0x0 },
+ { 0x113181, 0x0 },
+ { 0x213181, 0x0 },
+ { 0x100d0, 0x0 },
+ { 0x1100d0, 0x0 },
+ { 0x2100d0, 0x0 },
+ { 0x101d0, 0x0 },
+ { 0x1101d0, 0x0 },
+ { 0x2101d0, 0x0 },
+ { 0x110d0, 0x0 },
+ { 0x1110d0, 0x0 },
+ { 0x2110d0, 0x0 },
+ { 0x111d0, 0x0 },
+ { 0x1111d0, 0x0 },
+ { 0x2111d0, 0x0 },
+ { 0x120d0, 0x0 },
+ { 0x1120d0, 0x0 },
+ { 0x2120d0, 0x0 },
+ { 0x121d0, 0x0 },
+ { 0x1121d0, 0x0 },
+ { 0x2121d0, 0x0 },
+ { 0x130d0, 0x0 },
+ { 0x1130d0, 0x0 },
+ { 0x2130d0, 0x0 },
+ { 0x131d0, 0x0 },
+ { 0x1131d0, 0x0 },
+ { 0x2131d0, 0x0 },
+ { 0x100d1, 0x0 },
+ { 0x1100d1, 0x0 },
+ { 0x2100d1, 0x0 },
+ { 0x101d1, 0x0 },
+ { 0x1101d1, 0x0 },
+ { 0x2101d1, 0x0 },
+ { 0x110d1, 0x0 },
+ { 0x1110d1, 0x0 },
+ { 0x2110d1, 0x0 },
+ { 0x111d1, 0x0 },
+ { 0x1111d1, 0x0 },
+ { 0x2111d1, 0x0 },
+ { 0x120d1, 0x0 },
+ { 0x1120d1, 0x0 },
+ { 0x2120d1, 0x0 },
+ { 0x121d1, 0x0 },
+ { 0x1121d1, 0x0 },
+ { 0x2121d1, 0x0 },
+ { 0x130d1, 0x0 },
+ { 0x1130d1, 0x0 },
+ { 0x2130d1, 0x0 },
+ { 0x131d1, 0x0 },
+ { 0x1131d1, 0x0 },
+ { 0x2131d1, 0x0 },
+ { 0x10068, 0x0 },
+ { 0x10168, 0x0 },
+ { 0x10268, 0x0 },
+ { 0x10368, 0x0 },
+ { 0x10468, 0x0 },
+ { 0x10568, 0x0 },
+ { 0x10668, 0x0 },
+ { 0x10768, 0x0 },
+ { 0x10868, 0x0 },
+ { 0x11068, 0x0 },
+ { 0x11168, 0x0 },
+ { 0x11268, 0x0 },
+ { 0x11368, 0x0 },
+ { 0x11468, 0x0 },
+ { 0x11568, 0x0 },
+ { 0x11668, 0x0 },
+ { 0x11768, 0x0 },
+ { 0x11868, 0x0 },
+ { 0x12068, 0x0 },
+ { 0x12168, 0x0 },
+ { 0x12268, 0x0 },
+ { 0x12368, 0x0 },
+ { 0x12468, 0x0 },
+ { 0x12568, 0x0 },
+ { 0x12668, 0x0 },
+ { 0x12768, 0x0 },
+ { 0x12868, 0x0 },
+ { 0x13068, 0x0 },
+ { 0x13168, 0x0 },
+ { 0x13268, 0x0 },
+ { 0x13368, 0x0 },
+ { 0x13468, 0x0 },
+ { 0x13568, 0x0 },
+ { 0x13668, 0x0 },
+ { 0x13768, 0x0 },
+ { 0x13868, 0x0 },
+ { 0x10069, 0x0 },
+ { 0x10169, 0x0 },
+ { 0x10269, 0x0 },
+ { 0x10369, 0x0 },
+ { 0x10469, 0x0 },
+ { 0x10569, 0x0 },
+ { 0x10669, 0x0 },
+ { 0x10769, 0x0 },
+ { 0x10869, 0x0 },
+ { 0x11069, 0x0 },
+ { 0x11169, 0x0 },
+ { 0x11269, 0x0 },
+ { 0x11369, 0x0 },
+ { 0x11469, 0x0 },
+ { 0x11569, 0x0 },
+ { 0x11669, 0x0 },
+ { 0x11769, 0x0 },
+ { 0x11869, 0x0 },
+ { 0x12069, 0x0 },
+ { 0x12169, 0x0 },
+ { 0x12269, 0x0 },
+ { 0x12369, 0x0 },
+ { 0x12469, 0x0 },
+ { 0x12569, 0x0 },
+ { 0x12669, 0x0 },
+ { 0x12769, 0x0 },
+ { 0x12869, 0x0 },
+ { 0x13069, 0x0 },
+ { 0x13169, 0x0 },
+ { 0x13269, 0x0 },
+ { 0x13369, 0x0 },
+ { 0x13469, 0x0 },
+ { 0x13569, 0x0 },
+ { 0x13669, 0x0 },
+ { 0x13769, 0x0 },
+ { 0x13869, 0x0 },
+ { 0x1008c, 0x0 },
+ { 0x11008c, 0x0 },
+ { 0x21008c, 0x0 },
+ { 0x1018c, 0x0 },
+ { 0x11018c, 0x0 },
+ { 0x21018c, 0x0 },
+ { 0x1108c, 0x0 },
+ { 0x11108c, 0x0 },
+ { 0x21108c, 0x0 },
+ { 0x1118c, 0x0 },
+ { 0x11118c, 0x0 },
+ { 0x21118c, 0x0 },
+ { 0x1208c, 0x0 },
+ { 0x11208c, 0x0 },
+ { 0x21208c, 0x0 },
+ { 0x1218c, 0x0 },
+ { 0x11218c, 0x0 },
+ { 0x21218c, 0x0 },
+ { 0x1308c, 0x0 },
+ { 0x11308c, 0x0 },
+ { 0x21308c, 0x0 },
+ { 0x1318c, 0x0 },
+ { 0x11318c, 0x0 },
+ { 0x21318c, 0x0 },
+ { 0x1008d, 0x0 },
+ { 0x11008d, 0x0 },
+ { 0x21008d, 0x0 },
+ { 0x1018d, 0x0 },
+ { 0x11018d, 0x0 },
+ { 0x21018d, 0x0 },
+ { 0x1108d, 0x0 },
+ { 0x11108d, 0x0 },
+ { 0x21108d, 0x0 },
+ { 0x1118d, 0x0 },
+ { 0x11118d, 0x0 },
+ { 0x21118d, 0x0 },
+ { 0x1208d, 0x0 },
+ { 0x11208d, 0x0 },
+ { 0x21208d, 0x0 },
+ { 0x1218d, 0x0 },
+ { 0x11218d, 0x0 },
+ { 0x21218d, 0x0 },
+ { 0x1308d, 0x0 },
+ { 0x11308d, 0x0 },
+ { 0x21308d, 0x0 },
+ { 0x1318d, 0x0 },
+ { 0x11318d, 0x0 },
+ { 0x21318d, 0x0 },
+ { 0x100c0, 0x0 },
+ { 0x1100c0, 0x0 },
+ { 0x2100c0, 0x0 },
+ { 0x101c0, 0x0 },
+ { 0x1101c0, 0x0 },
+ { 0x2101c0, 0x0 },
+ { 0x102c0, 0x0 },
+ { 0x1102c0, 0x0 },
+ { 0x2102c0, 0x0 },
+ { 0x103c0, 0x0 },
+ { 0x1103c0, 0x0 },
+ { 0x2103c0, 0x0 },
+ { 0x104c0, 0x0 },
+ { 0x1104c0, 0x0 },
+ { 0x2104c0, 0x0 },
+ { 0x105c0, 0x0 },
+ { 0x1105c0, 0x0 },
+ { 0x2105c0, 0x0 },
+ { 0x106c0, 0x0 },
+ { 0x1106c0, 0x0 },
+ { 0x2106c0, 0x0 },
+ { 0x107c0, 0x0 },
+ { 0x1107c0, 0x0 },
+ { 0x2107c0, 0x0 },
+ { 0x108c0, 0x0 },
+ { 0x1108c0, 0x0 },
+ { 0x2108c0, 0x0 },
+ { 0x110c0, 0x0 },
+ { 0x1110c0, 0x0 },
+ { 0x2110c0, 0x0 },
+ { 0x111c0, 0x0 },
+ { 0x1111c0, 0x0 },
+ { 0x2111c0, 0x0 },
+ { 0x112c0, 0x0 },
+ { 0x1112c0, 0x0 },
+ { 0x2112c0, 0x0 },
+ { 0x113c0, 0x0 },
+ { 0x1113c0, 0x0 },
+ { 0x2113c0, 0x0 },
+ { 0x114c0, 0x0 },
+ { 0x1114c0, 0x0 },
+ { 0x2114c0, 0x0 },
+ { 0x115c0, 0x0 },
+ { 0x1115c0, 0x0 },
+ { 0x2115c0, 0x0 },
+ { 0x116c0, 0x0 },
+ { 0x1116c0, 0x0 },
+ { 0x2116c0, 0x0 },
+ { 0x117c0, 0x0 },
+ { 0x1117c0, 0x0 },
+ { 0x2117c0, 0x0 },
+ { 0x118c0, 0x0 },
+ { 0x1118c0, 0x0 },
+ { 0x2118c0, 0x0 },
+ { 0x120c0, 0x0 },
+ { 0x1120c0, 0x0 },
+ { 0x2120c0, 0x0 },
+ { 0x121c0, 0x0 },
+ { 0x1121c0, 0x0 },
+ { 0x2121c0, 0x0 },
+ { 0x122c0, 0x0 },
+ { 0x1122c0, 0x0 },
+ { 0x2122c0, 0x0 },
+ { 0x123c0, 0x0 },
+ { 0x1123c0, 0x0 },
+ { 0x2123c0, 0x0 },
+ { 0x124c0, 0x0 },
+ { 0x1124c0, 0x0 },
+ { 0x2124c0, 0x0 },
+ { 0x125c0, 0x0 },
+ { 0x1125c0, 0x0 },
+ { 0x2125c0, 0x0 },
+ { 0x126c0, 0x0 },
+ { 0x1126c0, 0x0 },
+ { 0x2126c0, 0x0 },
+ { 0x127c0, 0x0 },
+ { 0x1127c0, 0x0 },
+ { 0x2127c0, 0x0 },
+ { 0x128c0, 0x0 },
+ { 0x1128c0, 0x0 },
+ { 0x2128c0, 0x0 },
+ { 0x130c0, 0x0 },
+ { 0x1130c0, 0x0 },
+ { 0x2130c0, 0x0 },
+ { 0x131c0, 0x0 },
+ { 0x1131c0, 0x0 },
+ { 0x2131c0, 0x0 },
+ { 0x132c0, 0x0 },
+ { 0x1132c0, 0x0 },
+ { 0x2132c0, 0x0 },
+ { 0x133c0, 0x0 },
+ { 0x1133c0, 0x0 },
+ { 0x2133c0, 0x0 },
+ { 0x134c0, 0x0 },
+ { 0x1134c0, 0x0 },
+ { 0x2134c0, 0x0 },
+ { 0x135c0, 0x0 },
+ { 0x1135c0, 0x0 },
+ { 0x2135c0, 0x0 },
+ { 0x136c0, 0x0 },
+ { 0x1136c0, 0x0 },
+ { 0x2136c0, 0x0 },
+ { 0x137c0, 0x0 },
+ { 0x1137c0, 0x0 },
+ { 0x2137c0, 0x0 },
+ { 0x138c0, 0x0 },
+ { 0x1138c0, 0x0 },
+ { 0x2138c0, 0x0 },
+ { 0x100c1, 0x0 },
+ { 0x1100c1, 0x0 },
+ { 0x2100c1, 0x0 },
+ { 0x101c1, 0x0 },
+ { 0x1101c1, 0x0 },
+ { 0x2101c1, 0x0 },
+ { 0x102c1, 0x0 },
+ { 0x1102c1, 0x0 },
+ { 0x2102c1, 0x0 },
+ { 0x103c1, 0x0 },
+ { 0x1103c1, 0x0 },
+ { 0x2103c1, 0x0 },
+ { 0x104c1, 0x0 },
+ { 0x1104c1, 0x0 },
+ { 0x2104c1, 0x0 },
+ { 0x105c1, 0x0 },
+ { 0x1105c1, 0x0 },
+ { 0x2105c1, 0x0 },
+ { 0x106c1, 0x0 },
+ { 0x1106c1, 0x0 },
+ { 0x2106c1, 0x0 },
+ { 0x107c1, 0x0 },
+ { 0x1107c1, 0x0 },
+ { 0x2107c1, 0x0 },
+ { 0x108c1, 0x0 },
+ { 0x1108c1, 0x0 },
+ { 0x2108c1, 0x0 },
+ { 0x110c1, 0x0 },
+ { 0x1110c1, 0x0 },
+ { 0x2110c1, 0x0 },
+ { 0x111c1, 0x0 },
+ { 0x1111c1, 0x0 },
+ { 0x2111c1, 0x0 },
+ { 0x112c1, 0x0 },
+ { 0x1112c1, 0x0 },
+ { 0x2112c1, 0x0 },
+ { 0x113c1, 0x0 },
+ { 0x1113c1, 0x0 },
+ { 0x2113c1, 0x0 },
+ { 0x114c1, 0x0 },
+ { 0x1114c1, 0x0 },
+ { 0x2114c1, 0x0 },
+ { 0x115c1, 0x0 },
+ { 0x1115c1, 0x0 },
+ { 0x2115c1, 0x0 },
+ { 0x116c1, 0x0 },
+ { 0x1116c1, 0x0 },
+ { 0x2116c1, 0x0 },
+ { 0x117c1, 0x0 },
+ { 0x1117c1, 0x0 },
+ { 0x2117c1, 0x0 },
+ { 0x118c1, 0x0 },
+ { 0x1118c1, 0x0 },
+ { 0x2118c1, 0x0 },
+ { 0x120c1, 0x0 },
+ { 0x1120c1, 0x0 },
+ { 0x2120c1, 0x0 },
+ { 0x121c1, 0x0 },
+ { 0x1121c1, 0x0 },
+ { 0x2121c1, 0x0 },
+ { 0x122c1, 0x0 },
+ { 0x1122c1, 0x0 },
+ { 0x2122c1, 0x0 },
+ { 0x123c1, 0x0 },
+ { 0x1123c1, 0x0 },
+ { 0x2123c1, 0x0 },
+ { 0x124c1, 0x0 },
+ { 0x1124c1, 0x0 },
+ { 0x2124c1, 0x0 },
+ { 0x125c1, 0x0 },
+ { 0x1125c1, 0x0 },
+ { 0x2125c1, 0x0 },
+ { 0x126c1, 0x0 },
+ { 0x1126c1, 0x0 },
+ { 0x2126c1, 0x0 },
+ { 0x127c1, 0x0 },
+ { 0x1127c1, 0x0 },
+ { 0x2127c1, 0x0 },
+ { 0x128c1, 0x0 },
+ { 0x1128c1, 0x0 },
+ { 0x2128c1, 0x0 },
+ { 0x130c1, 0x0 },
+ { 0x1130c1, 0x0 },
+ { 0x2130c1, 0x0 },
+ { 0x131c1, 0x0 },
+ { 0x1131c1, 0x0 },
+ { 0x2131c1, 0x0 },
+ { 0x132c1, 0x0 },
+ { 0x1132c1, 0x0 },
+ { 0x2132c1, 0x0 },
+ { 0x133c1, 0x0 },
+ { 0x1133c1, 0x0 },
+ { 0x2133c1, 0x0 },
+ { 0x134c1, 0x0 },
+ { 0x1134c1, 0x0 },
+ { 0x2134c1, 0x0 },
+ { 0x135c1, 0x0 },
+ { 0x1135c1, 0x0 },
+ { 0x2135c1, 0x0 },
+ { 0x136c1, 0x0 },
+ { 0x1136c1, 0x0 },
+ { 0x2136c1, 0x0 },
+ { 0x137c1, 0x0 },
+ { 0x1137c1, 0x0 },
+ { 0x2137c1, 0x0 },
+ { 0x138c1, 0x0 },
+ { 0x1138c1, 0x0 },
+ { 0x2138c1, 0x0 },
+ { 0x10020, 0x0 },
+ { 0x110020, 0x0 },
+ { 0x210020, 0x0 },
+ { 0x11020, 0x0 },
+ { 0x111020, 0x0 },
+ { 0x211020, 0x0 },
+ { 0x12020, 0x0 },
+ { 0x112020, 0x0 },
+ { 0x212020, 0x0 },
+ { 0x13020, 0x0 },
+ { 0x113020, 0x0 },
+ { 0x213020, 0x0 },
+ { 0x20072, 0x0 },
+ { 0x20073, 0x0 },
+ { 0x20074, 0x0 },
+ { 0x100aa, 0x0 },
+ { 0x110aa, 0x0 },
+ { 0x120aa, 0x0 },
+ { 0x130aa, 0x0 },
+ { 0x20010, 0x0 },
+ { 0x120010, 0x0 },
+ { 0x220010, 0x0 },
+ { 0x20011, 0x0 },
+ { 0x120011, 0x0 },
+ { 0x220011, 0x0 },
+ { 0x100ae, 0x0 },
+ { 0x1100ae, 0x0 },
+ { 0x2100ae, 0x0 },
+ { 0x100af, 0x0 },
+ { 0x1100af, 0x0 },
+ { 0x2100af, 0x0 },
+ { 0x110ae, 0x0 },
+ { 0x1110ae, 0x0 },
+ { 0x2110ae, 0x0 },
+ { 0x110af, 0x0 },
+ { 0x1110af, 0x0 },
+ { 0x2110af, 0x0 },
+ { 0x120ae, 0x0 },
+ { 0x1120ae, 0x0 },
+ { 0x2120ae, 0x0 },
+ { 0x120af, 0x0 },
+ { 0x1120af, 0x0 },
+ { 0x2120af, 0x0 },
+ { 0x130ae, 0x0 },
+ { 0x1130ae, 0x0 },
+ { 0x2130ae, 0x0 },
+ { 0x130af, 0x0 },
+ { 0x1130af, 0x0 },
+ { 0x2130af, 0x0 },
+ { 0x20020, 0x0 },
+ { 0x120020, 0x0 },
+ { 0x220020, 0x0 },
+ { 0x100a0, 0x0 },
+ { 0x100a1, 0x0 },
+ { 0x100a2, 0x0 },
+ { 0x100a3, 0x0 },
+ { 0x100a4, 0x0 },
+ { 0x100a5, 0x0 },
+ { 0x100a6, 0x0 },
+ { 0x100a7, 0x0 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x0 },
+ { 0x110a2, 0x0 },
+ { 0x110a3, 0x0 },
+ { 0x110a4, 0x0 },
+ { 0x110a5, 0x0 },
+ { 0x110a6, 0x0 },
+ { 0x110a7, 0x0 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x0 },
+ { 0x120a2, 0x0 },
+ { 0x120a3, 0x0 },
+ { 0x120a4, 0x0 },
+ { 0x120a5, 0x0 },
+ { 0x120a6, 0x0 },
+ { 0x120a7, 0x0 },
+ { 0x130a0, 0x0 },
+ { 0x130a1, 0x0 },
+ { 0x130a2, 0x0 },
+ { 0x130a3, 0x0 },
+ { 0x130a4, 0x0 },
+ { 0x130a5, 0x0 },
+ { 0x130a6, 0x0 },
+ { 0x130a7, 0x0 },
+ { 0x2007c, 0x0 },
+ { 0x12007c, 0x0 },
+ { 0x22007c, 0x0 },
+ { 0x2007d, 0x0 },
+ { 0x12007d, 0x0 },
+ { 0x22007d, 0x0 },
+ { 0x400fd, 0x0 },
+ { 0x400c0, 0x0 },
+ { 0x90201, 0x0 },
+ { 0x190201, 0x0 },
+ { 0x290201, 0x0 },
+ { 0x90202, 0x0 },
+ { 0x190202, 0x0 },
+ { 0x290202, 0x0 },
+ { 0x90203, 0x0 },
+ { 0x190203, 0x0 },
+ { 0x290203, 0x0 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x90205, 0x0 },
+ { 0x190205, 0x0 },
+ { 0x290205, 0x0 },
+ { 0x90206, 0x0 },
+ { 0x190206, 0x0 },
+ { 0x290206, 0x0 },
+ { 0x90207, 0x0 },
+ { 0x190207, 0x0 },
+ { 0x290207, 0x0 },
+ { 0x90208, 0x0 },
+ { 0x190208, 0x0 },
+ { 0x290208, 0x0 },
+ { 0x10062, 0x0 },
+ { 0x10162, 0x0 },
+ { 0x10262, 0x0 },
+ { 0x10362, 0x0 },
+ { 0x10462, 0x0 },
+ { 0x10562, 0x0 },
+ { 0x10662, 0x0 },
+ { 0x10762, 0x0 },
+ { 0x10862, 0x0 },
+ { 0x11062, 0x0 },
+ { 0x11162, 0x0 },
+ { 0x11262, 0x0 },
+ { 0x11362, 0x0 },
+ { 0x11462, 0x0 },
+ { 0x11562, 0x0 },
+ { 0x11662, 0x0 },
+ { 0x11762, 0x0 },
+ { 0x11862, 0x0 },
+ { 0x12062, 0x0 },
+ { 0x12162, 0x0 },
+ { 0x12262, 0x0 },
+ { 0x12362, 0x0 },
+ { 0x12462, 0x0 },
+ { 0x12562, 0x0 },
+ { 0x12662, 0x0 },
+ { 0x12762, 0x0 },
+ { 0x12862, 0x0 },
+ { 0x13062, 0x0 },
+ { 0x13162, 0x0 },
+ { 0x13262, 0x0 },
+ { 0x13362, 0x0 },
+ { 0x13462, 0x0 },
+ { 0x13562, 0x0 },
+ { 0x13662, 0x0 },
+ { 0x13762, 0x0 },
+ { 0x13862, 0x0 },
+ { 0x20077, 0x0 },
+ { 0x10001, 0x0 },
+ { 0x11001, 0x0 },
+ { 0x12001, 0x0 },
+ { 0x13001, 0x0 },
+ { 0x10040, 0x0 },
+ { 0x10140, 0x0 },
+ { 0x10240, 0x0 },
+ { 0x10340, 0x0 },
+ { 0x10440, 0x0 },
+ { 0x10540, 0x0 },
+ { 0x10640, 0x0 },
+ { 0x10740, 0x0 },
+ { 0x10840, 0x0 },
+ { 0x10030, 0x0 },
+ { 0x10130, 0x0 },
+ { 0x10230, 0x0 },
+ { 0x10330, 0x0 },
+ { 0x10430, 0x0 },
+ { 0x10530, 0x0 },
+ { 0x10630, 0x0 },
+ { 0x10730, 0x0 },
+ { 0x10830, 0x0 },
+ { 0x11040, 0x0 },
+ { 0x11140, 0x0 },
+ { 0x11240, 0x0 },
+ { 0x11340, 0x0 },
+ { 0x11440, 0x0 },
+ { 0x11540, 0x0 },
+ { 0x11640, 0x0 },
+ { 0x11740, 0x0 },
+ { 0x11840, 0x0 },
+ { 0x11030, 0x0 },
+ { 0x11130, 0x0 },
+ { 0x11230, 0x0 },
+ { 0x11330, 0x0 },
+ { 0x11430, 0x0 },
+ { 0x11530, 0x0 },
+ { 0x11630, 0x0 },
+ { 0x11730, 0x0 },
+ { 0x11830, 0x0 },
+ { 0x12040, 0x0 },
+ { 0x12140, 0x0 },
+ { 0x12240, 0x0 },
+ { 0x12340, 0x0 },
+ { 0x12440, 0x0 },
+ { 0x12540, 0x0 },
+ { 0x12640, 0x0 },
+ { 0x12740, 0x0 },
+ { 0x12840, 0x0 },
+ { 0x12030, 0x0 },
+ { 0x12130, 0x0 },
+ { 0x12230, 0x0 },
+ { 0x12330, 0x0 },
+ { 0x12430, 0x0 },
+ { 0x12530, 0x0 },
+ { 0x12630, 0x0 },
+ { 0x12730, 0x0 },
+ { 0x12830, 0x0 },
+ { 0x13040, 0x0 },
+ { 0x13140, 0x0 },
+ { 0x13240, 0x0 },
+ { 0x13340, 0x0 },
+ { 0x13440, 0x0 },
+ { 0x13540, 0x0 },
+ { 0x13640, 0x0 },
+ { 0x13740, 0x0 },
+ { 0x13840, 0x0 },
+ { 0x13030, 0x0 },
+ { 0x13130, 0x0 },
+ { 0x13230, 0x0 },
+ { 0x13330, 0x0 },
+ { 0x13430, 0x0 },
+ { 0x13530, 0x0 },
+ { 0x13630, 0x0 },
+ { 0x13730, 0x0 },
+ { 0x13830, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54003, 0xbb8},
+ {0x54004, 0x2},
+ {0x54005, 0x2228},
+ {0x54006, 0x11},
+ {0x54008, 0x131f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x2},
+ {0x5400d, 0x100},
+ {0x54012, 0x310},
+ {0x54019, 0x2dd4},
+ {0x5401a, 0x31},
+ {0x5401b, 0x4d66},
+ {0x5401c, 0x4d00},
+ {0x5401e, 0x16},
+ {0x5401f, 0x2dd4},
+ {0x54020, 0x31},
+ {0x54021, 0x4d66},
+ {0x54022, 0x4d00},
+ {0x54024, 0x16},
+ {0x5402b, 0x1000},
+ {0x5402c, 0x3},
+ {0x54032, 0xd400},
+ {0x54033, 0x312d},
+ {0x54034, 0x6600},
+ {0x54035, 0x4d},
+ {0x54036, 0x4d},
+ {0x54037, 0x1600},
+ {0x54038, 0xd400},
+ {0x54039, 0x312d},
+ {0x5403a, 0x6600},
+ {0x5403b, 0x4d},
+ {0x5403c, 0x4d},
+ {0x5403d, 0x1600},
+ {0xd0000, 0x1},
+};
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54002, 0x101},
+ {0x54003, 0x190},
+ {0x54004, 0x2},
+ {0x54005, 0x2228},
+ {0x54006, 0x11},
+ {0x54008, 0x121f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x2},
+ {0x5400d, 0x100},
+ {0x54012, 0x310},
+ {0x54019, 0x84},
+ {0x5401a, 0x31},
+ {0x5401b, 0x4d66},
+ {0x5401c, 0x4d00},
+ {0x5401e, 0x16},
+ {0x5401f, 0x84},
+ {0x54020, 0x31},
+ {0x54021, 0x4d66},
+ {0x54022, 0x4d00},
+ {0x54024, 0x16},
+ {0x5402b, 0x1000},
+ {0x5402c, 0x3},
+ {0x54032, 0x8400},
+ {0x54033, 0x3100},
+ {0x54034, 0x6600},
+ {0x54035, 0x4d},
+ {0x54036, 0x4d},
+ {0x54037, 0x1600},
+ {0x54038, 0x8400},
+ {0x54039, 0x3100},
+ {0x5403a, 0x6600},
+ {0x5403b, 0x4d},
+ {0x5403c, 0x4d},
+ {0x5403d, 0x1600},
+ {0xd0000, 0x1},
+};
+
+/* P2 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp2_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54002, 0x102},
+ {0x54003, 0x64},
+ {0x54004, 0x2},
+ {0x54005, 0x2228},
+ {0x54006, 0x11},
+ {0x54008, 0x121f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x2},
+ {0x5400d, 0x100},
+ {0x54012, 0x310},
+ {0x54019, 0x84},
+ {0x5401a, 0x31},
+ {0x5401b, 0x4d66},
+ {0x5401c, 0x4d00},
+ {0x5401e, 0x16},
+ {0x5401f, 0x84},
+ {0x54020, 0x31},
+ {0x54021, 0x4d66},
+ {0x54022, 0x4d00},
+ {0x54024, 0x16},
+ {0x5402b, 0x1000},
+ {0x5402c, 0x3},
+ {0x54032, 0x8400},
+ {0x54033, 0x3100},
+ {0x54034, 0x6600},
+ {0x54035, 0x4d},
+ {0x54036, 0x4d},
+ {0x54037, 0x1600},
+ {0x54038, 0x8400},
+ {0x54039, 0x3100},
+ {0x5403a, 0x6600},
+ {0x5403b, 0x4d},
+ {0x5403c, 0x4d},
+ {0x5403d, 0x1600},
+ {0xd0000, 0x1},
+};
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54003, 0xbb8},
+ {0x54004, 0x2},
+ {0x54005, 0x2228},
+ {0x54006, 0x11},
+ {0x54008, 0x61},
+ {0x54009, 0xc8},
+ {0x5400b, 0x2},
+ {0x5400f, 0x100},
+ {0x54010, 0x1f7f},
+ {0x54012, 0x310},
+ {0x54019, 0x2dd4},
+ {0x5401a, 0x31},
+ {0x5401b, 0x4d66},
+ {0x5401c, 0x4d00},
+ {0x5401e, 0x16},
+ {0x5401f, 0x2dd4},
+ {0x54020, 0x31},
+ {0x54021, 0x4d66},
+ {0x54022, 0x4d00},
+ {0x54024, 0x16},
+ {0x5402b, 0x1000},
+ {0x5402c, 0x3},
+ {0x54032, 0xd400},
+ {0x54033, 0x312d},
+ {0x54034, 0x6600},
+ {0x54035, 0x4d},
+ {0x54036, 0x4d},
+ {0x54037, 0x1600},
+ {0x54038, 0xd400},
+ {0x54039, 0x312d},
+ {0x5403a, 0x6600},
+ {0x5403b, 0x4d},
+ {0x5403c, 0x4d},
+ {0x5403d, 0x1600},
+ { 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+ {0xd0000, 0x0},
+ {0x90000, 0x10},
+ {0x90001, 0x400},
+ {0x90002, 0x10e},
+ {0x90003, 0x0},
+ {0x90004, 0x0},
+ {0x90005, 0x8},
+ {0x90029, 0xb},
+ {0x9002a, 0x480},
+ {0x9002b, 0x109},
+ {0x9002c, 0x8},
+ {0x9002d, 0x448},
+ {0x9002e, 0x139},
+ {0x9002f, 0x8},
+ {0x90030, 0x478},
+ {0x90031, 0x109},
+ {0x90032, 0x0},
+ {0x90033, 0xe8},
+ {0x90034, 0x109},
+ {0x90035, 0x2},
+ {0x90036, 0x10},
+ {0x90037, 0x139},
+ {0x90038, 0xf},
+ {0x90039, 0x7c0},
+ {0x9003a, 0x139},
+ {0x9003b, 0x44},
+ {0x9003c, 0x630},
+ {0x9003d, 0x159},
+ {0x9003e, 0x14f},
+ {0x9003f, 0x630},
+ {0x90040, 0x159},
+ {0x90041, 0x47},
+ {0x90042, 0x630},
+ {0x90043, 0x149},
+ {0x90044, 0x4f},
+ {0x90045, 0x630},
+ {0x90046, 0x179},
+ {0x90047, 0x8},
+ {0x90048, 0xe0},
+ {0x90049, 0x109},
+ {0x9004a, 0x0},
+ {0x9004b, 0x7c8},
+ {0x9004c, 0x109},
+ {0x9004d, 0x0},
+ {0x9004e, 0x1},
+ {0x9004f, 0x8},
+ {0x90050, 0x0},
+ {0x90051, 0x45a},
+ {0x90052, 0x9},
+ {0x90053, 0x0},
+ {0x90054, 0x448},
+ {0x90055, 0x109},
+ {0x90056, 0x40},
+ {0x90057, 0x630},
+ {0x90058, 0x179},
+ {0x90059, 0x1},
+ {0x9005a, 0x618},
+ {0x9005b, 0x109},
+ {0x9005c, 0x40c0},
+ {0x9005d, 0x630},
+ {0x9005e, 0x149},
+ {0x9005f, 0x8},
+ {0x90060, 0x4},
+ {0x90061, 0x48},
+ {0x90062, 0x4040},
+ {0x90063, 0x630},
+ {0x90064, 0x149},
+ {0x90065, 0x0},
+ {0x90066, 0x4},
+ {0x90067, 0x48},
+ {0x90068, 0x40},
+ {0x90069, 0x630},
+ {0x9006a, 0x149},
+ {0x9006b, 0x10},
+ {0x9006c, 0x4},
+ {0x9006d, 0x18},
+ {0x9006e, 0x0},
+ {0x9006f, 0x4},
+ {0x90070, 0x78},
+ {0x90071, 0x549},
+ {0x90072, 0x630},
+ {0x90073, 0x159},
+ {0x90074, 0xd49},
+ {0x90075, 0x630},
+ {0x90076, 0x159},
+ {0x90077, 0x94a},
+ {0x90078, 0x630},
+ {0x90079, 0x159},
+ {0x9007a, 0x441},
+ {0x9007b, 0x630},
+ {0x9007c, 0x149},
+ {0x9007d, 0x42},
+ {0x9007e, 0x630},
+ {0x9007f, 0x149},
+ {0x90080, 0x1},
+ {0x90081, 0x630},
+ {0x90082, 0x149},
+ {0x90083, 0x0},
+ {0x90084, 0xe0},
+ {0x90085, 0x109},
+ {0x90086, 0xa},
+ {0x90087, 0x10},
+ {0x90088, 0x109},
+ {0x90089, 0x9},
+ {0x9008a, 0x3c0},
+ {0x9008b, 0x149},
+ {0x9008c, 0x9},
+ {0x9008d, 0x3c0},
+ {0x9008e, 0x159},
+ {0x9008f, 0x18},
+ {0x90090, 0x10},
+ {0x90091, 0x109},
+ {0x90092, 0x0},
+ {0x90093, 0x3c0},
+ {0x90094, 0x109},
+ {0x90095, 0x18},
+ {0x90096, 0x4},
+ {0x90097, 0x48},
+ {0x90098, 0x18},
+ {0x90099, 0x4},
+ {0x9009a, 0x58},
+ {0x9009b, 0xa},
+ {0x9009c, 0x10},
+ {0x9009d, 0x109},
+ {0x9009e, 0x2},
+ {0x9009f, 0x10},
+ {0x900a0, 0x109},
+ {0x900a1, 0x5},
+ {0x900a2, 0x7c0},
+ {0x900a3, 0x109},
+ {0x900a4, 0x10},
+ {0x900a5, 0x10},
+ {0x900a6, 0x109},
+ {0x40000, 0x811},
+ {0x40020, 0x880},
+ {0x40040, 0x0},
+ {0x40060, 0x0},
+ {0x40001, 0x4008},
+ {0x40021, 0x83},
+ {0x40041, 0x4f},
+ {0x40061, 0x0},
+ {0x40002, 0x4040},
+ {0x40022, 0x83},
+ {0x40042, 0x51},
+ {0x40062, 0x0},
+ {0x40003, 0x811},
+ {0x40023, 0x880},
+ {0x40043, 0x0},
+ {0x40063, 0x0},
+ {0x40004, 0x720},
+ {0x40024, 0xf},
+ {0x40044, 0x1740},
+ {0x40064, 0x0},
+ {0x40005, 0x16},
+ {0x40025, 0x83},
+ {0x40045, 0x4b},
+ {0x40065, 0x0},
+ {0x40006, 0x716},
+ {0x40026, 0xf},
+ {0x40046, 0x2001},
+ {0x40066, 0x0},
+ {0x40007, 0x716},
+ {0x40027, 0xf},
+ {0x40047, 0x2800},
+ {0x40067, 0x0},
+ {0x40008, 0x716},
+ {0x40028, 0xf},
+ {0x40048, 0xf00},
+ {0x40068, 0x0},
+ {0x40009, 0x720},
+ {0x40029, 0xf},
+ {0x40049, 0x1400},
+ {0x40069, 0x0},
+ {0x4000a, 0xe08},
+ {0x4002a, 0xc15},
+ {0x4004a, 0x0},
+ {0x4006a, 0x0},
+ {0x4000b, 0x623},
+ {0x4002b, 0x15},
+ {0x4004b, 0x0},
+ {0x4006b, 0x0},
+ {0x4000c, 0x4028},
+ {0x4002c, 0x80},
+ {0x4004c, 0x0},
+ {0x4006c, 0x0},
+ {0x4000d, 0xe08},
+ {0x4002d, 0xc1a},
+ {0x4004d, 0x0},
+ {0x4006d, 0x0},
+ {0x4000e, 0x623},
+ {0x4002e, 0x1a},
+ {0x4004e, 0x0},
+ {0x4006e, 0x0},
+ {0x4000f, 0x4040},
+ {0x4002f, 0x80},
+ {0x4004f, 0x0},
+ {0x4006f, 0x0},
+ {0x40010, 0x2604},
+ {0x40030, 0x15},
+ {0x40050, 0x0},
+ {0x40070, 0x0},
+ {0x40011, 0x708},
+ {0x40031, 0x5},
+ {0x40051, 0x0},
+ {0x40071, 0x2002},
+ {0x40012, 0x8},
+ {0x40032, 0x80},
+ {0x40052, 0x0},
+ {0x40072, 0x0},
+ {0x40013, 0x2604},
+ {0x40033, 0x1a},
+ {0x40053, 0x0},
+ {0x40073, 0x0},
+ {0x40014, 0x708},
+ {0x40034, 0xa},
+ {0x40054, 0x0},
+ {0x40074, 0x2002},
+ {0x40015, 0x4040},
+ {0x40035, 0x80},
+ {0x40055, 0x0},
+ {0x40075, 0x0},
+ {0x40016, 0x60a},
+ {0x40036, 0x15},
+ {0x40056, 0x1200},
+ {0x40076, 0x0},
+ {0x40017, 0x61a},
+ {0x40037, 0x15},
+ {0x40057, 0x1300},
+ {0x40077, 0x0},
+ {0x40018, 0x60a},
+ {0x40038, 0x1a},
+ {0x40058, 0x1200},
+ {0x40078, 0x0},
+ {0x40019, 0x642},
+ {0x40039, 0x1a},
+ {0x40059, 0x1300},
+ {0x40079, 0x0},
+ {0x4001a, 0x4808},
+ {0x4003a, 0x880},
+ {0x4005a, 0x0},
+ {0x4007a, 0x0},
+ {0x900a7, 0x0},
+ {0x900a8, 0x790},
+ {0x900a9, 0x11a},
+ {0x900aa, 0x8},
+ {0x900ab, 0x7aa},
+ {0x900ac, 0x2a},
+ {0x900ad, 0x10},
+ {0x900ae, 0x7b2},
+ {0x900af, 0x2a},
+ {0x900b0, 0x0},
+ {0x900b1, 0x7c8},
+ {0x900b2, 0x109},
+ {0x900b3, 0x10},
+ {0x900b4, 0x2a8},
+ {0x900b5, 0x129},
+ {0x900b6, 0x8},
+ {0x900b7, 0x370},
+ {0x900b8, 0x129},
+ {0x900b9, 0xa},
+ {0x900ba, 0x3c8},
+ {0x900bb, 0x1a9},
+ {0x900bc, 0xc},
+ {0x900bd, 0x408},
+ {0x900be, 0x199},
+ {0x900bf, 0x14},
+ {0x900c0, 0x790},
+ {0x900c1, 0x11a},
+ {0x900c2, 0x8},
+ {0x900c3, 0x4},
+ {0x900c4, 0x18},
+ {0x900c5, 0xe},
+ {0x900c6, 0x408},
+ {0x900c7, 0x199},
+ {0x900c8, 0x8},
+ {0x900c9, 0x8568},
+ {0x900ca, 0x108},
+ {0x900cb, 0x18},
+ {0x900cc, 0x790},
+ {0x900cd, 0x16a},
+ {0x900ce, 0x8},
+ {0x900cf, 0x1d8},
+ {0x900d0, 0x169},
+ {0x900d1, 0x10},
+ {0x900d2, 0x8558},
+ {0x900d3, 0x168},
+ {0x900d4, 0x70},
+ {0x900d5, 0x788},
+ {0x900d6, 0x16a},
+ {0x900d7, 0x1ff8},
+ {0x900d8, 0x85a8},
+ {0x900d9, 0x1e8},
+ {0x900da, 0x50},
+ {0x900db, 0x798},
+ {0x900dc, 0x16a},
+ {0x900dd, 0x60},
+ {0x900de, 0x7a0},
+ {0x900df, 0x16a},
+ {0x900e0, 0x8},
+ {0x900e1, 0x8310},
+ {0x900e2, 0x168},
+ {0x900e3, 0x8},
+ {0x900e4, 0xa310},
+ {0x900e5, 0x168},
+ {0x900e6, 0xa},
+ {0x900e7, 0x408},
+ {0x900e8, 0x169},
+ {0x900e9, 0x6e},
+ {0x900ea, 0x0},
+ {0x900eb, 0x68},
+ {0x900ec, 0x0},
+ {0x900ed, 0x408},
+ {0x900ee, 0x169},
+ {0x900ef, 0x0},
+ {0x900f0, 0x8310},
+ {0x900f1, 0x168},
+ {0x900f2, 0x0},
+ {0x900f3, 0xa310},
+ {0x900f4, 0x168},
+ {0x900f5, 0x1ff8},
+ {0x900f6, 0x85a8},
+ {0x900f7, 0x1e8},
+ {0x900f8, 0x68},
+ {0x900f9, 0x798},
+ {0x900fa, 0x16a},
+ {0x900fb, 0x78},
+ {0x900fc, 0x7a0},
+ {0x900fd, 0x16a},
+ {0x900fe, 0x68},
+ {0x900ff, 0x790},
+ {0x90100, 0x16a},
+ {0x90101, 0x8},
+ {0x90102, 0x8b10},
+ {0x90103, 0x168},
+ {0x90104, 0x8},
+ {0x90105, 0xab10},
+ {0x90106, 0x168},
+ {0x90107, 0xa},
+ {0x90108, 0x408},
+ {0x90109, 0x169},
+ {0x9010a, 0x58},
+ {0x9010b, 0x0},
+ {0x9010c, 0x68},
+ {0x9010d, 0x0},
+ {0x9010e, 0x408},
+ {0x9010f, 0x169},
+ {0x90110, 0x0},
+ {0x90111, 0x8b10},
+ {0x90112, 0x168},
+ {0x90113, 0x0},
+ {0x90114, 0xab10},
+ {0x90115, 0x168},
+ {0x90116, 0x0},
+ {0x90117, 0x1d8},
+ {0x90118, 0x169},
+ {0x90119, 0x80},
+ {0x9011a, 0x790},
+ {0x9011b, 0x16a},
+ {0x9011c, 0x18},
+ {0x9011d, 0x7aa},
+ {0x9011e, 0x6a},
+ {0x9011f, 0xa},
+ {0x90120, 0x0},
+ {0x90121, 0x1e9},
+ {0x90122, 0x8},
+ {0x90123, 0x8080},
+ {0x90124, 0x108},
+ {0x90125, 0xf},
+ {0x90126, 0x408},
+ {0x90127, 0x169},
+ {0x90128, 0xc},
+ {0x90129, 0x0},
+ {0x9012a, 0x68},
+ {0x9012b, 0x9},
+ {0x9012c, 0x0},
+ {0x9012d, 0x1a9},
+ {0x9012e, 0x0},
+ {0x9012f, 0x408},
+ {0x90130, 0x169},
+ {0x90131, 0x0},
+ {0x90132, 0x8080},
+ {0x90133, 0x108},
+ {0x90134, 0x8},
+ {0x90135, 0x7aa},
+ {0x90136, 0x6a},
+ {0x90137, 0x0},
+ {0x90138, 0x8568},
+ {0x90139, 0x108},
+ {0x9013a, 0xb7},
+ {0x9013b, 0x790},
+ {0x9013c, 0x16a},
+ {0x9013d, 0x1f},
+ {0x9013e, 0x0},
+ {0x9013f, 0x68},
+ {0x90140, 0x8},
+ {0x90141, 0x8558},
+ {0x90142, 0x168},
+ {0x90143, 0xf},
+ {0x90144, 0x408},
+ {0x90145, 0x169},
+ {0x90146, 0xc},
+ {0x90147, 0x0},
+ {0x90148, 0x68},
+ {0x90149, 0x0},
+ {0x9014a, 0x408},
+ {0x9014b, 0x169},
+ {0x9014c, 0x0},
+ {0x9014d, 0x8558},
+ {0x9014e, 0x168},
+ {0x9014f, 0x8},
+ {0x90150, 0x3c8},
+ {0x90151, 0x1a9},
+ {0x90152, 0x3},
+ {0x90153, 0x370},
+ {0x90154, 0x129},
+ {0x90155, 0x20},
+ {0x90156, 0x2aa},
+ {0x90157, 0x9},
+ {0x90158, 0x0},
+ {0x90159, 0x400},
+ {0x9015a, 0x10e},
+ {0x9015b, 0x8},
+ {0x9015c, 0xe8},
+ {0x9015d, 0x109},
+ {0x9015e, 0x0},
+ {0x9015f, 0x8140},
+ {0x90160, 0x10c},
+ {0x90161, 0x10},
+ {0x90162, 0x8138},
+ {0x90163, 0x10c},
+ {0x90164, 0x8},
+ {0x90165, 0x7c8},
+ {0x90166, 0x101},
+ {0x90167, 0x8},
+ {0x90168, 0x0},
+ {0x90169, 0x8},
+ {0x9016a, 0x8},
+ {0x9016b, 0x448},
+ {0x9016c, 0x109},
+ {0x9016d, 0xf},
+ {0x9016e, 0x7c0},
+ {0x9016f, 0x109},
+ {0x90170, 0x0},
+ {0x90171, 0xe8},
+ {0x90172, 0x109},
+ {0x90173, 0x47},
+ {0x90174, 0x630},
+ {0x90175, 0x109},
+ {0x90176, 0x8},
+ {0x90177, 0x618},
+ {0x90178, 0x109},
+ {0x90179, 0x8},
+ {0x9017a, 0xe0},
+ {0x9017b, 0x109},
+ {0x9017c, 0x0},
+ {0x9017d, 0x7c8},
+ {0x9017e, 0x109},
+ {0x9017f, 0x8},
+ {0x90180, 0x8140},
+ {0x90181, 0x10c},
+ {0x90182, 0x0},
+ {0x90183, 0x1},
+ {0x90184, 0x8},
+ {0x90185, 0x8},
+ {0x90186, 0x4},
+ {0x90187, 0x8},
+ {0x90188, 0x8},
+ {0x90189, 0x7c8},
+ {0x9018a, 0x101},
+ {0x90006, 0x0},
+ {0x90007, 0x0},
+ {0x90008, 0x8},
+ {0x90009, 0x0},
+ {0x9000a, 0x0},
+ {0x9000b, 0x0},
+ {0xd00e7, 0x400},
+ {0x90017, 0x0},
+ {0x9001f, 0x2a},
+ {0x90026, 0x6a},
+ {0x400d0, 0x0},
+ {0x400d1, 0x101},
+ {0x400d2, 0x105},
+ {0x400d3, 0x107},
+ {0x400d4, 0x10f},
+ {0x400d5, 0x202},
+ {0x400d6, 0x20a},
+ {0x400d7, 0x20b},
+ {0x2003a, 0x2},
+ {0x2000b, 0x5d},
+ {0x2000c, 0xbb},
+ {0x2000d, 0x753},
+ {0x2000e, 0x2c},
+ {0x12000b, 0xc},
+ {0x12000c, 0x19},
+ {0x12000d, 0xfa},
+ {0x12000e, 0x10},
+ {0x22000b, 0x3},
+ {0x22000c, 0x6},
+ {0x22000d, 0x3e},
+ {0x22000e, 0x10},
+ {0x9000c, 0x0},
+ {0x9000d, 0x173},
+ {0x9000e, 0x60},
+ {0x9000f, 0x6110},
+ {0x90010, 0x2152},
+ {0x90011, 0xdfbd},
+ {0x90012, 0x60},
+ {0x90013, 0x6152},
+ {0x20010, 0x5a},
+ {0x20011, 0x3},
+ {0x120010, 0x5a},
+ {0x120011, 0x3},
+ {0x220010, 0x5a},
+ {0x220011, 0x3},
+ {0x40080, 0xe0},
+ {0x40081, 0x12},
+ {0x40082, 0xe0},
+ {0x40083, 0x12},
+ {0x40084, 0xe0},
+ {0x40085, 0x12},
+ {0x140080, 0xe0},
+ {0x140081, 0x12},
+ {0x140082, 0xe0},
+ {0x140083, 0x12},
+ {0x140084, 0xe0},
+ {0x140085, 0x12},
+ {0x240080, 0xe0},
+ {0x240081, 0x12},
+ {0x240082, 0xe0},
+ {0x240083, 0x12},
+ {0x240084, 0xe0},
+ {0x240085, 0x12},
+ {0x400fd, 0xf},
+ {0x10011, 0x1},
+ {0x10012, 0x1},
+ {0x10013, 0x180},
+ {0x10018, 0x1},
+ {0x10002, 0x6209},
+ {0x100b2, 0x1},
+ {0x101b4, 0x1},
+ {0x102b4, 0x1},
+ {0x103b4, 0x1},
+ {0x104b4, 0x1},
+ {0x105b4, 0x1},
+ {0x106b4, 0x1},
+ {0x107b4, 0x1},
+ {0x108b4, 0x1},
+ {0x11011, 0x1},
+ {0x11012, 0x1},
+ {0x11013, 0x180},
+ {0x11018, 0x1},
+ {0x11002, 0x6209},
+ {0x110b2, 0x1},
+ {0x111b4, 0x1},
+ {0x112b4, 0x1},
+ {0x113b4, 0x1},
+ {0x114b4, 0x1},
+ {0x115b4, 0x1},
+ {0x116b4, 0x1},
+ {0x117b4, 0x1},
+ {0x118b4, 0x1},
+ {0x12011, 0x1},
+ {0x12012, 0x1},
+ {0x12013, 0x180},
+ {0x12018, 0x1},
+ {0x12002, 0x6209},
+ {0x120b2, 0x1},
+ {0x121b4, 0x1},
+ {0x122b4, 0x1},
+ {0x123b4, 0x1},
+ {0x124b4, 0x1},
+ {0x125b4, 0x1},
+ {0x126b4, 0x1},
+ {0x127b4, 0x1},
+ {0x128b4, 0x1},
+ {0x13011, 0x1},
+ {0x13012, 0x1},
+ {0x13013, 0x180},
+ {0x13018, 0x1},
+ {0x13002, 0x6209},
+ {0x130b2, 0x1},
+ {0x131b4, 0x1},
+ {0x132b4, 0x1},
+ {0x133b4, 0x1},
+ {0x134b4, 0x1},
+ {0x135b4, 0x1},
+ {0x136b4, 0x1},
+ {0x137b4, 0x1},
+ {0x138b4, 0x1},
+ {0x2003a, 0x2},
+ {0xc0080, 0x2},
+ {0xd0000, 0x1}
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 3000mts 1D */
+ .drate = 3000,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P1 400mts 1D */
+ .drate = 400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+ },
+ {
+ /* P2 100mts 1D */
+ .drate = 100,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp2_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+ },
+ {
+ /* P0 3000mts 2D */
+ .drate = 3000,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 3000, 400, 100, },
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Kontron Electronics GmbH
+ */
+
+#include <asm/arch/imx-regs.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <fdt_support.h>
+#include <linux/errno.h>
+#include <net.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_phys_sdram_size(phys_size_t *size)
+{
+ u32 ddr_size = readl(M4_BOOTROM_BASE_ADDR);
+
+ if (ddr_size == 4) {
+ *size = 0x100000000;
+ } else if (ddr_size == 3) {
+ *size = 0xc0000000;
+ } else if (ddr_size == 2) {
+ *size = 0x80000000;
+ } else if (ddr_size == 1) {
+ *size = 0x40000000;
+ } else {
+ printf("Unknown DDR type!!!\n");
+ *size = 0x40000000;
+ }
+
+ return 0;
+}
+
+/*
+ * If the SoM is mounted on a baseboard with a USB ethernet controller,
+ * there might be an additional MAC address programmed to the MAC OTP fuses.
+ * Although the i.MX8MM has only one MAC, the MAC0, MAC1 and MAC2 registers
+ * in the OTP fuses can still be used to store two separate addresses.
+ * Try to read the secondary address from MAC1 and MAC2 and adjust the
+ * devicetree so Linux can pick up the MAC address.
+ */
+int fdt_set_usb_eth_addr(void *blob)
+{
+ u32 value = readl(OCOTP_BASE_ADDR + 0x660);
+ unsigned char mac[6];
+ int node, ret;
+
+ mac[0] = value >> 24;
+ mac[1] = value >> 16;
+ mac[2] = value >> 8;
+ mac[3] = value;
+
+ value = readl(OCOTP_BASE_ADDR + 0x650);
+ mac[4] = value >> 24;
+ mac[5] = value >> 16;
+
+ node = fdt_path_offset(blob, fdt_get_alias(blob, "ethernet1"));
+ if (node < 0) {
+ /*
+ * There is no node for the USB ethernet in the devicetree. Just skip.
+ */
+ return 0;
+ }
+
+ if (is_zero_ethaddr(mac)) {
+ printf("\nNo MAC address for USB ethernet set in OTP fuses!\n");
+ return 0;
+ }
+
+ if (!is_valid_ethaddr(mac)) {
+ printf("\nInvalid MAC address for USB ethernet set in OTP fuses!\n");
+ return -EINVAL;
+ }
+
+ ret = fdt_setprop(blob, node, "local-mac-address", &mac, 6);
+ if (ret)
+ ret = fdt_setprop(blob, node, "mac-address", &mac, 6);
+
+ if (ret)
+ printf("\nMissing mac-address or local-mac-address property in dt, skip setting MAC address for USB ethernet\n");
+
+ return 0;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ int ret = fdt_set_usb_eth_addr(blob);
+
+ if (ret)
+ return ret;
+
+ return fdt_fixup_memory(blob, PHYS_SDRAM, gd->ram_size);
+}
+
+int board_init(void)
+{
+ return 0;
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Kontron Electronics GmbH
+ */
+
+#include <asm/arch/imx8mm_pins.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <dm/uclass.h>
+#include <hang.h>
+#include <i2c.h>
+#include <init.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <power/pca9450.h>
+#include <power/pmic.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+ BOARD_TYPE_KTN_N801X,
+ BOARD_TYPE_KTN_N801X_LVDS,
+ BOARD_TYPE_MAX
+};
+
+#define GPIO_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+
+#define TOUCH_RESET_GPIO IMX_GPIO_NR(3, 23)
+
+static iomux_v3_cfg_t const i2c1_pads[] = {
+ IMX8MM_PAD_I2C1_SCL_I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL) | MUX_MODE_SION,
+ IMX8MM_PAD_I2C1_SDA_I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL) | MUX_MODE_SION
+};
+
+static iomux_v3_cfg_t const i2c2_pads[] = {
+ IMX8MM_PAD_I2C2_SCL_I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL) | MUX_MODE_SION,
+ IMX8MM_PAD_I2C2_SDA_I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL) | MUX_MODE_SION
+};
+
+static iomux_v3_cfg_t const touch_gpio[] = {
+ IMX8MM_PAD_SAI5_RXD2_GPIO3_IO23 | MUX_PAD_CTRL(GPIO_PAD_CTRL)
+};
+
+static iomux_v3_cfg_t const uart_pads[] = {
+ IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+ IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+ switch (boot_dev_spl) {
+ case USB_BOOT:
+ return BOOT_DEVICE_BOARD;
+ case SPI_NOR_BOOT:
+ return BOOT_DEVICE_SPI;
+ case SD1_BOOT:
+ case MMC1_BOOT:
+ return BOOT_DEVICE_MMC1;
+ case SD2_BOOT:
+ case MMC2_BOOT:
+ return BOOT_DEVICE_MMC2;
+ default:
+ return BOOT_DEVICE_NONE;
+ }
+}
+
+bool check_ram_available(long size)
+{
+ long sz = get_ram_size((long *)PHYS_SDRAM, size);
+
+ if (sz == size)
+ return true;
+
+ return false;
+}
+
+static void spl_dram_init(void)
+{
+ u32 size = 0;
+
+ /*
+ * Try the default DDR settings in lpddr4_timing.c to
+ * comply with the Micron 4GB DDR.
+ */
+ if (!ddr_init(&dram_timing) && check_ram_available(SZ_4G)) {
+ size = 4;
+ } else {
+ /*
+ * Overwrite some values to comply with the Micron 1GB/2GB DDRs.
+ */
+ dram_timing.ddrc_cfg[2].val = 0xa1080020;
+ dram_timing.ddrc_cfg[37].val = 0x1f;
+
+ dram_timing.fsp_msg[0].fsp_cfg[9].val = 0x110;
+ dram_timing.fsp_msg[0].fsp_cfg[21].val = 0x1;
+ dram_timing.fsp_msg[1].fsp_cfg[10].val = 0x110;
+ dram_timing.fsp_msg[1].fsp_cfg[22].val = 0x1;
+ dram_timing.fsp_msg[2].fsp_cfg[10].val = 0x110;
+ dram_timing.fsp_msg[2].fsp_cfg[22].val = 0x1;
+ dram_timing.fsp_msg[3].fsp_cfg[10].val = 0x110;
+ dram_timing.fsp_msg[3].fsp_cfg[22].val = 0x1;
+
+ if (!ddr_init(&dram_timing)) {
+ if (check_ram_available(SZ_2G))
+ size = 2;
+ else if (check_ram_available(SZ_1G))
+ size = 1;
+ }
+ }
+
+ if (size == 0) {
+ printf("Failed to initialize DDR RAM!\n");
+ size = 1;
+ }
+
+ printf("Kontron SL i.MX8MM (N801X) module, %u GB RAM detected\n", size);
+ writel(size, M4_BOOTROM_BASE_ADDR);
+}
+
+static void touch_reset(void)
+{
+ /*
+ * Toggle the reset of the touch panel.
+ */
+ imx_iomux_v3_setup_multiple_pads(touch_gpio, ARRAY_SIZE(touch_gpio));
+
+ gpio_request(TOUCH_RESET_GPIO, "touch_reset");
+ gpio_direction_output(TOUCH_RESET_GPIO, 0);
+ mdelay(20);
+ gpio_direction_output(TOUCH_RESET_GPIO, 1);
+ mdelay(20);
+}
+
+static int i2c_detect(u8 bus, u16 addr)
+{
+ struct udevice *udev;
+ int ret;
+
+ /*
+ * Try to probe the touch controller to check if an LVDS panel is
+ * connected.
+ */
+ ret = i2c_get_chip_for_busnum(bus, addr, 0, &udev);
+ if (ret == 0)
+ return 0;
+
+ return 1;
+}
+
+int do_board_detect(void)
+{
+ bool lvds = false;
+
+ /*
+ * Check the I2C touch controller to detect a LVDS panel.
+ */
+ imx_iomux_v3_setup_multiple_pads(i2c2_pads, ARRAY_SIZE(i2c2_pads));
+ touch_reset();
+
+ if (i2c_detect(1, 0x5d) == 0) {
+ printf("Touch controller detected, assuming LVDS panel...\n");
+ lvds = true;
+ }
+
+ /*
+ * Check the I2C PMIC to detect the deprecated SoM with DA9063.
+ */
+ imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
+
+ if (i2c_detect(0, 0x58) == 0) {
+ printf("### ATTENTION: DEPRECATED SOM REVISION (N8010 Rev0) DETECTED! ###\n");
+ printf("### THIS HW IS NOT SUPPRTED AND BOOTING WILL PROBABLY FAIL ###\n");
+ printf("### PLEASE UPGRADE TO LATEST MODULE ###\n");
+ }
+
+ if (lvds)
+ gd->board_type = BOARD_TYPE_KTN_N801X_LVDS;
+ else
+ gd->board_type = BOARD_TYPE_KTN_N801X;
+
+ return 0;
+}
+
+int board_fit_config_name_match(const char *name)
+{
+ if (gd->board_type == BOARD_TYPE_KTN_N801X_LVDS && is_imx8mm() &&
+ !strncmp(name, "imx8mm-kontron-n801x-s-lvds", 27))
+ return 0;
+
+ if (gd->board_type == BOARD_TYPE_KTN_N801X && is_imx8mm() &&
+ !strncmp(name, "imx8mm-kontron-n801x-s", 22))
+ return 0;
+
+ return -1;
+}
+
+void spl_board_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ puts("Normal Boot\n");
+
+ ret = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@30380000",
+ &dev);
+ if (ret < 0)
+ printf("Failed to find clock node. Check device tree\n");
+}
+
+int board_early_init_f(void)
+{
+ struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+ imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+ set_wdog_reset(wdog);
+
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+ return 0;
+}
+
+static int power_init_board(void)
+{
+ struct udevice *dev;
+ int ret = pmic_get("pmic@25", &dev);
+
+ if (ret == -ENODEV)
+ puts("No pmic found\n");
+
+ if (ret)
+ return ret;
+
+ /* BUCKxOUT_DVS0/1 control BUCK123 output, clear PRESET_EN */
+ pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
+
+ /* increase VDD_DRAM to 0.95V for 1.5GHz DDR */
+ pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x1c);
+
+ /* set VDD_SNVS_0V8 from default 0.85V to 0.8V */
+ pmic_reg_write(dev, PCA9450_LDO2CTRL, 0xC0);
+
+ /* set WDOG_B_CFG to cold reset */
+ pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
+
+ return 0;
+}
+
+void board_init_f(ulong dummy)
+{
+ int ret;
+
+ arch_cpu_init();
+
+ init_uart_clk(2);
+
+ board_early_init_f();
+
+ timer_init();
+
+ preloader_console_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ ret = spl_init();
+ if (ret) {
+ debug("spl_init() failed: %d\n", ret);
+ hang();
+ }
+
+ enable_tzc380();
+
+ /* PMIC initialization */
+ power_init_board();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ /* Detect the board type */
+ do_board_detect();
+
+ board_init_r(NULL, 0);
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+ u32 bootdev = spl_boot_device();
+
+ /*
+ * The default boot fuse settings use the SD card (MMC2) as primary
+ * boot device, but allow SPI NOR as a fallback boot device.
+ * We can't detect the fallback case and spl_boot_device() will return
+ * BOOT_DEVICE_MMC2 despite the actual boot device being SPI NOR.
+ * Therefore we try to load U-Boot proper vom SPI NOR after loading
+ * from MMC has failed.
+ */
+ spl_boot_list[0] = bootdev;
+
+ switch (bootdev) {
+ case BOOT_DEVICE_MMC1:
+ case BOOT_DEVICE_MMC2:
+ spl_boot_list[1] = BOOT_DEVICE_SPI;
+ break;
+ }
+}
Kontron SMARC-sAL28 board
M: Michael Walle <michael@walle.cc>
S: Maintained
+F: arch/arm/dts/fsl-ls1028a.dtsi
F: arch/arm/dts/fsl-ls1028a-kontron-sl28-*
F: board/kontron/sl28/
F: configs/kontron_sl28_defconfig
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/iomux-mx53.h>
+#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/mx5_video.h>
#include <asm/mach-imx/video.h>
#include <asm/gpio.h>
int board_late_init(void)
{
+#ifdef CONFIG_CMD_BMODE
+ add_board_boot_modes(NULL);
+#endif
+
#if defined(CONFIG_VIDEO_IPUV3)
struct udevice *dev;
int xpos, ypos, ret;
default "phycore_imx8mm"
config IMX_CONFIG
- default "arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg"
+ default "board/phytec/phycore_imx8mm/imximage-8mm-sd.cfg"
endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 Phytec Messtechnik GmbH
+ */
+
+#define __ASSEMBLY__
+
+BOOT_FROM sd
+LOADER u-boot-spl-ddr.bin 0x7E1000
#include <asm/global_data.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/iomux-v3.h>
-#include <dm/device.h>
-#include <dm/uclass.h>
#include <hang.h>
#include <init.h>
#include <log.h>
}
}
-void spl_dram_init(void)
+static void spl_dram_init(void)
{
ddr_init(&dram_timing);
}
puts("Normal Boot\n");
}
-#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
- /* Just empty function now - can't decide what to choose */
- debug("%s: %s\n", __func__, name);
-
return 0;
}
-#endif
#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE)
void board_init_f(ulong dummy)
{
- struct udevice *dev;
int ret;
arch_cpu_init();
board_early_init_f();
- timer_init();
-
preloader_console_init();
/* Clear the BSS. */
hang();
}
- ret = uclass_get_device_by_name(UCLASS_CLK,
- "clock-controller@30380000", &dev);
- if (ret < 0) {
- printf("Failed to find clock node. Check device tree\n");
- hang();
- }
-
enable_tzc380();
/* DDR initialization */
ROM_VERSION v2
BOOT_FROM sd
-LOADER mkimage.flash.mkimage 0x920000
+LOADER u-boot-spl-ddr.bin 0x920000
/*
* If the firmware passed a device tree use it for U-Boot.
*/
-void *board_fdt_blob_setup(void)
+void *board_fdt_blob_setup(int *err)
{
- if (fdt_magic(fw_dtb_pointer) != FDT_MAGIC)
+ *err = 0;
+ if (fdt_magic(fw_dtb_pointer) != FDT_MAGIC) {
+ *err = -ENXIO;
return NULL;
+ }
+
return (void *)fw_dtb_pointer;
}
--- /dev/null
+config SYS_CONFIG_NAME
+ string "Board configuration name"
+ default "exynos78x0-common.h"
+ help
+ This option contains information about board configuration name.
+ Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
+ will be used for board configuration.
+
+if TARGET_A5Y17LTE
+config SYS_BOARD
+ default "axy17lte"
+ help
+ a5y17lte is a production board for SM-A520F phone on Exynos7880 SoC.
+
+config SYS_VENDOR
+ default "samsung"
+
+config SYS_CONFIG_NAME
+ default "a5y17lte"
+
+config EXYNOS7880
+ bool "Exynos 7880 SOC support"
+ default y
+endif
+
+if TARGET_A7Y17LTE
+config SYS_BOARD
+ default "axy17lte"
+ help
+ a5y17lte is a production board for SM-A520F phone on Exynos7880 SoC.
+
+config SYS_VENDOR
+ default "samsung"
+
+config SYS_CONFIG_NAME
+ default "a5y17lte"
+
+config EXYNOS7880
+ bool "Exynos 7880 SOC support"
+ default y
+endif
+
+if TARGET_A3Y17LTE
+config SYS_BOARD
+ default "axy17lte"
+ help
+ a3y17lte is a production board for SM-A520F phone on Exynos7880 SoC.
+
+config SYS_VENDOR
+ default "samsung"
+
+config SYS_CONFIG_NAME
+ default "a3y17lte"
+
+config EXYNOS7870
+ bool "Exynos 7870 SOC support"
+ default y
+endif
--- /dev/null
+Samsung A series 2017 phones Board
+M: Dzmitry Sankouski <dsankouski@gmail.com>
+S: Maintained
+F: board/samsung/axy17lte/
+F: include/configs/exynos78x0-common.h
+F: configs/a3y17lte_defconfig
+F: configs/a5y17lte_defconfig
+F: configs/a7y17lte_defconfig
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+obj-y += axy17lte.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Samsung A5Y17 and A3Y17 LTE boards based on Exynos 7880 and Exynos 7870 SoCs
+ */
+
+#include <common.h>
+
+int exynos_init(void)
+{
+ return 0;
+}
if TARGET_ESPRESSO7420
+config EXYNOS7420
+ def_bool y
+
config SYS_BOARD
default "espresso7420"
help
--- /dev/null
+if TARGET_STARQLTECHN
+
+config SYS_BOARD
+ default "starqltechn"
+ help
+ starqltechn is a production board for S9 and S9+ phones(SM-G96x0) phones based on SDM845 SoC.
+
+config SYS_CONFIG_NAME
+ string "Board configuration name"
+ default "sdm845"
+ help
+ This option contains information about board configuration name.
+ Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
+ will be used for board configuration.
+
+config SYS_VENDOR
+ default "samsung"
+
+config SYS_CONFIG_NAME
+ default "starqltechn"
+
+endif
--- /dev/null
+Samsung S9 (SM-G9600)(starqltechn) Board
+M: Dzmitry Sankouski <dsankouski@gmail.com>
+S: Maintained
+F: board/samsung/starqltechn/
+F: include/configs/starqltechn.h
+F: configs/starqltechn_defconfig
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
+#
+# This empty file prevents make error.
+# Board logic defined in board/qualcomm/common/sdm845.c, no custom logic for starqltechn so far.
+#
+
+obj-y += starqltechn.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * This empty file prevents make linking error.
+ * No custom logic for starqltechn so far.
+ *
+ * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
+ *
+ */
+
+void nooop(void) {}
{
}
-#if CONFIG_IS_ENABLED(LED) && CONFIG_IS_ENABLED(BOOTSTAGE)
+#if CONFIG_IS_ENABLED(LED) && CONFIG_IS_ENABLED(SHOW_BOOT_PROGRESS)
/*
* Indicate any error or (accidental?) entering of CLI via the red status LED.
*/
struct udevice *dev;
int ret;
- if (progress < 0 || progress == BOOTSTAGE_ID_ENTER_CLI_LOOP) {
+ if ((progress < 0 && progress != -BOOTSTAGE_ID_NET_ETH_START) ||
+ progress == BOOTSTAGE_ID_ENTER_CLI_LOOP) {
ret = led_get_by_label("status-led-green", &dev);
if (ret == 0)
led_set_state(dev, LEDST_OFF);
#endif
-void *board_fdt_blob_setup(void)
+void *board_fdt_blob_setup(int *err)
{
+ *err = 0;
if (IS_ENABLED(CONFIG_OF_SEPARATE)) {
if (gd->arch.firmware_fdt_addr)
- return (ulong *)gd->arch.firmware_fdt_addr;
- else
- return (ulong *)&_end;
+ return (ulong *)(uintptr_t)gd->arch.firmware_fdt_addr;
}
+
+ return (ulong *)&_end;
}
int board_init(void)
#include <dm.h>
#include <asm/sections.h>
-void *board_fdt_blob_setup(void)
+void *board_fdt_blob_setup(int *err)
{
+ *err = 0;
if (IS_ENABLED(CONFIG_OF_SEPARATE)) {
if (gd->arch.firmware_fdt_addr)
- return (ulong *)gd->arch.firmware_fdt_addr;
- else
- return (ulong *)&_end;
+ return (ulong *)(uintptr_t)gd->arch.firmware_fdt_addr;
}
+
+ return (ulong *)&_end;
}
int board_init(void)
{
gd->bd->bi_boot_params = CONFIG_SYS_LOAD_ADDR + LOAD_OFFSET;
- gd->env_addr = (ulong)&default_environment[0];
-
synquacer_setup_scbm_smmu();
return 0;
#endif /* CONFIG_OF_BOARD_SETUP */
#if defined(CONFIG_OF_SEPARATE)
-void *board_fdt_blob_setup(void)
+void *board_fdt_blob_setup(int *err)
{
void *fw_dtb;
+ *err = 0;
fw_dtb = (void *)(CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SECT_SIZE);
if (fdt_magic(fw_dtb) != FDT_MAGIC) {
printf("DTB is not passed via %x\n", (u32)fw_dtb);
+ *err = -ENXIO;
return NULL;
}
#include <asm/io.h>
#include <asm/armv7m.h>
#include <asm/arch/stm32.h>
-#include <asm/arch/gpio.h>
#include <asm/arch/syscfg.h>
#include <asm/gpio.h>
#include <linux/delay.h>
default "st"
config SYS_CONFIG_NAME
- default "stm32mp1"
+ default "stm32mp15_st_common"
source "board/st/common/Kconfig"
endif
F: configs/stm32mp15_defconfig
F: configs/stm32mp15_basic_defconfig
F: configs/stm32mp15_trusted_defconfig
-F: include/configs/stm32mp1.h
+F: include/configs/stm32mp15_common.h
+F: include/configs/stm32mp15_st_common.h
if (IS_ENABLED(CONFIG_DM_REGULATOR))
regulators_enable_boot_on(_DEBUG);
- if (!IS_ENABLED(CONFIG_TFABOOT))
+ /*
+ * sysconf initialisation done only when U-Boot is running in secure
+ * done in TF-A for TFABOOT.
+ */
+ if (IS_ENABLED(CONFIG_ARMV7_NONSEC))
sysconf_init();
if (CONFIG_IS_ENABLED(LED))
Apalis iMX8X
-M: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
+M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
W: http://developer.toradex.com/software/linux/linux-software
S: Maintained
F: arch/arm/dts/fsl-imx8x-apalis.dts
Apalis iMX6
-M: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
+M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
W: http://developer.toradex.com/software/linux/linux-software
W: https://www.toradex.com/community
S: Maintained
writel(table[2 * i + 1], table[2 * i]);
}
+/* Perform DDR DRAM calibration */
+static void spl_dram_perform_cal(void)
+{
+#ifdef CONFIG_MX6_DDRCAL
+ int err;
+ struct mx6_ddr_sysinfo ddr_sysinfo = {
+ .dsize = 2,
+ };
+
+ err = mmdc_do_write_level_calibration(&ddr_sysinfo);
+ if (err)
+ printf("error %d from write level calibration\n", err);
+ err = mmdc_do_dqs_calibration(&ddr_sysinfo);
+ if (err)
+ printf("error %d from dqs calibration\n", err);
+#endif
+}
+
static void spl_dram_init(void)
{
int minc, maxc;
break;
};
udelay(100);
+ spl_dram_perform_cal();
}
void board_init_f(ulong dummy)
if TARGET_COLIBRI_IMX6ULL
+choice
+ prompt "Colibri iMX6ULL variant"
+ optional
+
+config TARGET_COLIBRI_IMX6ULL_NAND
+ bool "Support Colibri iMX6ULL 256MB / 512MB (raw NAND) modules"
+ imply NAND_MXS
+ help
+ Choose this option if you build for a Toradex Colibri iMX6ULL
+ 256MB or 512MB module which do have raw NAND on-module.
+
+config TARGET_COLIBRI_IMX6ULL_EMMC
+ bool "Support Colibri iMX6ULL 1GB (eMMC) modules"
+ help
+ Choose this option if you build for a Toradex Colibri iMX6ULL
+ 1GB module which does have eMMC on-module.
+
+endchoice
+
config SYS_BOARD
default "colibri-imx6ull"
default "toradex"
config SYS_CONFIG_NAME
- default "colibri-imx6ull"
+ default "colibri-imx6ull-tezi-recovery" if (!TARGET_COLIBRI_IMX6ULL_NAND && !TARGET_COLIBRI_IMX6ULL_EMMC)
config TDX_CFG_BLOCK
default y
+if TARGET_COLIBRI_IMX6ULL_NAND
+
+config SYS_CONFIG_NAME
+ default "colibri-imx6ull"
+
config TDX_HAVE_NAND
default y
config TDX_CFG_BLOCK_OFFSET2
default "133120"
+endif
+
+if TARGET_COLIBRI_IMX6ULL_EMMC
+
+config SYS_CONFIG_NAME
+ default "colibri-imx6ull"
+
+config TDX_HAVE_MMC
+ default y
+
+config TDX_CFG_BLOCK_DEV
+ default "0"
+
+config TDX_CFG_BLOCK_PART
+ default "1"
+
+# Toradex config block in eMMC, at the end of 1st "boot sector"
+config TDX_CFG_BLOCK_OFFSET
+ default "-512"
+
+endif
+
config TDX_CFG_BLOCK_2ND_ETHADDR
default y
Colibri iMX6ULL
-M: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
+M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
W: http://developer.toradex.com/software/linux/linux-software
W: https://www.toradex.com/community
S: Maintained
F: arch/arm/dts/imx6ull-colibri.dts
-F: arch/arm/dts/imx6ull-colibri-u-boot.dtsi
F: arch/arm/dts/imx6ull-colibri.dtsi
+F: arch/arm/dts/imx6ull-colibri-emmc.dts
+F: arch/arm/dts/imx6ull-colibri-u-boot.dtsi
F: board/toradex/colibri-imx6ull/
F: configs/colibri-imx6ull_defconfig
+F: configs/colibri-imx6ull-emmc_defconfig
F: include/configs/colibri-imx6ull.h
#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_PUS_22K_UP)
+#define FLASH_DETECTION_CTRL (PAD_CTL_HYS | PAD_CTL_PUE)
+#define FLASH_DET_GPIO IMX_GPIO_NR(4, 1)
+static const iomux_v3_cfg_t flash_detection_pads[] = {
+ MX6_PAD_NAND_WE_B__GPIO4_IO01 | MUX_PAD_CTRL(FLASH_DETECTION_CTRL),
+};
+
+static bool is_emmc;
+
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
#ifdef CONFIG_NAND_MXS
static void setup_gpmi_nand(void)
{
- setup_gpmi_io_clk((3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
- (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
+ setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
+ MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)));
}
#endif /* CONFIG_NAND_MXS */
#ifdef CONFIG_DM_VIDEO
-static iomux_v3_cfg_t const backlight_pads[] = {
+static const iomux_v3_cfg_t backlight_pads[] = {
/* Backlight On */
MX6_PAD_JTAG_TMS__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* Backlight PWM<A> (multiplexed pin) */
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+ /*
+ * Enable GPIO on NAND_WE_B/eMMC_RST with 100k pull-down. eMMC_RST
+ * is pulled high with 4.7k for eMMC devices. This allows to reliably
+ * detect eMMC/NAND flash
+ */
+ imx_iomux_v3_setup_multiple_pads(flash_detection_pads, ARRAY_SIZE(flash_detection_pads));
+ gpio_request(FLASH_DET_GPIO, "flash-detection-gpio");
+ is_emmc = gpio_get_value(FLASH_DET_GPIO);
+ gpio_free(FLASH_DET_GPIO);
+
#ifdef CONFIG_FEC_MXC
setup_fec();
#endif
* Wi-Fi/Bluetooth make sure we use the -wifi device tree.
*/
if (tdx_hw_tag.prodid == COLIBRI_IMX6ULL_WIFI_BT_IT ||
- tdx_hw_tag.prodid == COLIBRI_IMX6ULL_WIFI_BT)
+ tdx_hw_tag.prodid == COLIBRI_IMX6ULL_WIFI_BT) {
env_set("variant", "-wifi");
+ } else {
+ if (is_emmc)
+ env_set("variant", "-emmc");
+ }
+#else
+ if (is_emmc)
+ env_set("variant", "-emmc");
#endif
/*
DATA 4 0x021B08b8 0x00000800
DATA 4 0x021B0004 0x0002002D
DATA 4 0x021B0008 0x1B333030
-DATA 4 0x021B000C 0x676B52F3
+DATA 4 0x021B000C 0x8B8F52F3
DATA 4 0x021B0010 0xB66D0B63
DATA 4 0x021B0014 0x01FF00DB
DATA 4 0x021B0018 0x00201740
-DATA 4 0x021B001C 0x00008000
DATA 4 0x021B002C 0x000026D2
-DATA 4 0x021B0030 0x006B1023
-DATA 4 0x021B0040 0x0000004F
-DATA 4 0x021B0000 0x84180000
-DATA 4 0x021B0890 0x00400000
+DATA 4 0x021B0030 0x008F1023
+DATA 4 0x021B0040 0x0000005F
+DATA 4 0x021B0000 0x85180000
DATA 4 0x021B001C 0x02008032
DATA 4 0x021B001C 0x00008033
DATA 4 0x021B001C 0x00048031
DATA 4 0x021B001C 0x04008040
DATA 4 0x021B0020 0x00000800
DATA 4 0x021B0818 0x00000227
-DATA 4 0x021B0004 0x0002552D
+DATA 4 0x021B0004 0x0002556D
DATA 4 0x021B0404 0x00011006
DATA 4 0x021B001C 0x00000000
-
Colibri iMX6
-M: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
+M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
W: http://developer.toradex.com/software/linux/linux-software
W: https://www.toradex.com/community
S: Maintained
writel(table[2 * i + 1], table[2 * i]);
}
+/* Perform DDR DRAM calibration */
+static void spl_dram_perform_cal(u8 dsize)
+{
+#ifdef CONFIG_MX6_DDRCAL
+ int err;
+ struct mx6_ddr_sysinfo ddr_sysinfo = {
+ .dsize = dsize,
+ };
+
+ err = mmdc_do_write_level_calibration(&ddr_sysinfo);
+ if (err)
+ printf("error %d from write level calibration\n", err);
+ err = mmdc_do_dqs_calibration(&ddr_sysinfo);
+ if (err)
+ printf("error %d from dqs calibration\n", err);
+#endif
+}
+
static void spl_dram_init(void)
{
int minc, maxc;
+ u8 dsize = 2;
switch (get_cpu_temp_grade(&minc, &maxc)) {
case TEMP_COMMERCIAL:
ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
} else {
puts("Commercial temperature grade DDR3 timings, 32bit bus width.\n");
+ dsize = 1;
ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
}
break;
ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
} else {
puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n");
+ dsize = 1;
ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
}
break;
};
udelay(100);
+ spl_dram_perform_cal(dsize);
}
static iomux_v3_cfg_t const gpio_reset_pad[] = {
Colibri iMX7
-M: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
+M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
W: http://developer.toradex.com/software/linux/linux-software
W: https://www.toradex.com/community
S: Maintained
COLIBRI_T20
-M: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
+M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
S: Maintained
F: board/toradex/colibri_t20/
F: include/configs/colibri_t20.h
Colibri T30
-M: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
+M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
S: Maintained
F: board/toradex/colibri_t30/
F: include/configs/colibri_t30.h
Colibri VFxx
-M: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
+M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
W: http://developer.toradex.com/software/linux/linux-software
W: https://www.toradex.com/community
S: Maintained
[59] = "Verdin iMX8M Mini Quad 2GB IT",
[60] = "Verdin iMX8M Mini DualLite 1GB WB IT",
[61] = "Verdin iMX8M Plus Quad 2GB",
+ [62] = "Colibri iMX6ULL 1GB IT (eMMC)",
+ [63] = "Verdin iMX8M Plus Quad 4GB IT",
+ [64] = "Verdin iMX8M Plus Quad 2GB Wi-Fi / BT IT",
+ [65] = "Verdin iMX8M Plus QuadLite 1GB IT",
+ [66] = "Verdin iMX8M Plus Quad 8GB Wi-Fi / BT",
};
const char * const toradex_carrier_boards[] = {
if (cpu_is_pxa27x())
sprintf(message, "Is the module the 312 MHz version? [y/N] ");
else
- it = 'y';
+ sprintf(message, "Is the module an IT version? [y/N] ");
+
+ len = cli_readline(message);
+ it = console_buffer[0];
#if defined(CONFIG_TARGET_APALIS_IMX8) || \
defined(CONFIG_TARGET_APALIS_IMX8X) || \
if (wb == 'y' || wb == 'Y')
tdx_hw_tag.prodid = COLIBRI_IMX6ULL_WIFI_BT_IT;
else
- tdx_hw_tag.prodid = COLIBRI_IMX6ULL_IT;
+ if (gd->ram_size == 0x20000000)
+ tdx_hw_tag.prodid = COLIBRI_IMX6ULL_IT;
+ else
+ tdx_hw_tag.prodid = COLIBRI_IMX6ULL_IT_EMMC;
} else {
if (wb == 'y' || wb == 'Y')
tdx_hw_tag.prodid = COLIBRI_IMX6ULL_WIFI_BT;
}
#endif
} else if (!strcmp("imx7d", soc))
- tdx_hw_tag.prodid = COLIBRI_IMX7D;
+ if (gd->ram_size == 0x20000000)
+ tdx_hw_tag.prodid = COLIBRI_IMX7D;
+ else
+ tdx_hw_tag.prodid = COLIBRI_IMX7D_EMMC;
else if (!strcmp("imx7s", soc))
tdx_hw_tag.prodid = COLIBRI_IMX7S;
else if (is_cpu_type(MXC_CPU_IMX8QM)) {
tdx_hw_tag.prodid = VERDIN_IMX8MMQ_IT;
} else if (is_cpu_type(MXC_CPU_IMX8MN)) {
tdx_hw_tag.prodid = VERDIN_IMX8MNQ_WIFI_BT;
+ } else if (is_cpu_type(MXC_CPU_IMX8MPL)) {
+ tdx_hw_tag.prodid = VERDIN_IMX8MPQL_IT;
} else if (is_cpu_type(MXC_CPU_IMX8MP)) {
if (wb == 'y' || wb == 'Y')
- tdx_hw_tag.prodid = VERDIN_IMX8MPQ_WIFI_BT_IT;
+ if (gd->ram_size == 0x80000000)
+ tdx_hw_tag.prodid = VERDIN_IMX8MPQ_2GB_WIFI_BT_IT;
+ else if (gd->ram_size == 0x200000000)
+ tdx_hw_tag.prodid = VERDIN_IMX8MPQ_8GB_WIFI_BT;
+ else
+ tdx_hw_tag.prodid = VERDIN_IMX8MPQ_WIFI_BT_IT;
else
- tdx_hw_tag.prodid = VERDIN_IMX8MPQ;
+ if (it == 'y' || it == 'Y')
+ tdx_hw_tag.prodid = VERDIN_IMX8MPQ_IT;
+ else
+ tdx_hw_tag.prodid = VERDIN_IMX8MPQ;
} else if (!strcmp("tegra20", soc)) {
if (it == 'y' || it == 'Y')
if (gd->ram_size == 0x10000000)
VERDIN_IMX8MMQ_IT,
VERDIN_IMX8MMDL_WIFI_BT_IT, /* 60 */
VERDIN_IMX8MPQ,
+ COLIBRI_IMX6ULL_IT_EMMC,
+ VERDIN_IMX8MPQ_IT,
+ VERDIN_IMX8MPQ_2GB_WIFI_BT_IT,
+ VERDIN_IMX8MPQL_IT, /* 65 */
+ VERDIN_IMX8MPQ_8GB_WIFI_BT,
};
enum {
Verdin iMX8M Mini
-M: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
+M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
W: https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-mini
S: Maintained
F: arch/arm/dts/imx8mm-verdin.dts
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2020 Toradex
+ * Copyright 2020-2021 Toradex
*/
#define __ASSEMBLY__
-FIT
BOOT_FROM emmc_fastboot
-LOADER spl/u-boot-spl-ddr.bin 0x7E1000
-SECOND_LOADER u-boot.itb 0x40200000 0x60000
-
-DDR_FW lpddr4_pmu_train_1d_imem.bin
-DDR_FW lpddr4_pmu_train_1d_dmem.bin
-DDR_FW lpddr4_pmu_train_2d_imem.bin
-DDR_FW lpddr4_pmu_train_2d_dmem.bin
+LOADER u-boot-spl-ddr.bin 0x7e1000
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2020 Toradex
+ * Copyright 2020-2021 Toradex
*/
#include <common.h>
#include <asm/arch/sys_proto.h>
#include <asm/global_data.h>
#include <asm/io.h>
+#include <hang.h>
#include <i2c.h>
+#include <micrel.h>
#include <miiphy.h>
#include <netdev.h>
-#include <micrel.h>
#include "../common/tdx-cfg-block.h"
return 0;
}
-
-int board_phy_config(struct phy_device *phydev)
-{
- int tmp;
-
- switch (ksz9xx1_phy_get_id(phydev) & MII_KSZ9x31_SILICON_REV_MASK) {
- case PHY_ID_KSZ9031:
- /*
- * The PHY adds 1.2ns for the RXC and 0ns for TXC clock by
- * default. The MAC and the layout don't add a skew between
- * clock and data.
- * Add 0.3ns for the RXC path and 0.96 + 0.42 ns (1.38 ns) for
- * the TXC path to get the required clock skews.
- */
- /* control data pad skew - devaddr = 0x02, register = 0x04 */
- ksz9031_phy_extended_write(phydev, 0x02,
- MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
- MII_KSZ9031_MOD_DATA_NO_POST_INC,
- 0x0070);
- /* rx data pad skew - devaddr = 0x02, register = 0x05 */
- ksz9031_phy_extended_write(phydev, 0x02,
- MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
- MII_KSZ9031_MOD_DATA_NO_POST_INC,
- 0x7777);
- /* tx data pad skew - devaddr = 0x02, register = 0x06 */
- ksz9031_phy_extended_write(phydev, 0x02,
- MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
- MII_KSZ9031_MOD_DATA_NO_POST_INC,
- 0x0000);
- /* gtx and rx clock pad skew - devaddr = 0x02,register = 0x08 */
- ksz9031_phy_extended_write(phydev, 0x02,
- MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
- MII_KSZ9031_MOD_DATA_NO_POST_INC,
- 0x03f4);
- break;
- case PHY_ID_KSZ9131:
- default:
- /* read rxc dll control - devaddr = 0x2, register = 0x4c */
- tmp = ksz9031_phy_extended_read(phydev, 0x02,
- MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
- MII_KSZ9031_MOD_DATA_NO_POST_INC);
- /* disable rxdll bypass (enable 2ns skew delay on RXC) */
- tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
- /* rxc data pad skew 2ns - devaddr = 0x02, register = 0x4c */
- tmp = ksz9031_phy_extended_write(phydev, 0x02,
- MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
- MII_KSZ9031_MOD_DATA_NO_POST_INC, tmp);
- /* read txc dll control - devaddr = 0x02, register = 0x4d */
- tmp = ksz9031_phy_extended_read(phydev, 0x02,
- MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
- MII_KSZ9031_MOD_DATA_NO_POST_INC);
- /* disable txdll bypass (enable 2ns skew delay on TXC) */
- tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
- /* rxc data pad skew 2ns - devaddr = 0x02, register = 0x4d */
- tmp = ksz9031_phy_extended_write(phydev, 0x02,
- MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
- MII_KSZ9031_MOD_DATA_NO_POST_INC, tmp);
- break;
- }
-
- if (phydev->drv->config)
- phydev->drv->config(phydev);
- return 0;
-}
#endif
int board_init(void)
switch (get_pcb_revision()) {
case PCB_VERSION_1_0:
- printf("Detected a V1.0 module\n");
- if (is_wifi)
- strncpy(&variant[0], "wifi", sizeof(variant));
- else
- strncpy(&variant[0], "nonwifi", sizeof(variant));
- break;
+ printf("Detected a V1.0 module which is no longer supported in this BSP version\n");
+ hang();
default:
if (is_wifi)
- strncpy(&variant[0], "wifi-v1.1", sizeof(variant));
+ strlcpy(&variant[0], "wifi", sizeof(variant));
else
- strncpy(&variant[0], "nonwifi-v1.1", sizeof(variant));
+ strlcpy(&variant[0], "nonwifi", sizeof(variant));
break;
}
* x0 is the physical address of the device tree blob (dtb) in system RAM.
* This is stored in rom_pointer during low level init.
*/
-void *board_fdt_blob_setup(void)
+void *board_fdt_blob_setup(int *err)
{
- if (fdt_magic(rom_pointer[0]) != FDT_MAGIC)
+ *err = 0;
+ if (fdt_magic(rom_pointer[0]) != FDT_MAGIC) {
+ *err = -ENXIO;
return NULL;
+ }
return (void *)rom_pointer[0];
}
}
#if defined(CONFIG_OF_BOARD) || defined(CONFIG_OF_SEPARATE)
-void *board_fdt_blob_setup(void)
+void *board_fdt_blob_setup(int *err)
{
void *fdt_blob;
+ *err = 0;
if (!IS_ENABLED(CONFIG_SPL_BUILD) &&
!IS_ENABLED(CONFIG_VERSAL_NO_DDR) &&
!IS_ENABLED(CONFIG_ZYNQMP_NO_DDR)) {
device memory. Assure this size does not extend past expected storage
space.
+config SPL_FIT_RSASSA_PSS
+ bool "Support rsassa-pss signature scheme of FIT image contents in SPL"
+ depends on SPL_FIT_SIGNATURE
+ help
+ Enable this to support the pss padding algorithm as described
+ in the rfc8017 (https://tools.ietf.org/html/rfc8017) in SPL.
+
config SPL_LOAD_FIT
bool "Enable SPL loading U-Boot as a FIT (basic fitImage features)"
select SPL_FIT
-150 common/cmd_nand.c Incorrect FIT image format
151 common/cmd_nand.c FIT image format OK
+config SPL_SHOW_BOOT_PROGRESS
+ bool "Show boot progress in a board-specific manner in SPL"
+ depends on SPL
+ help
+ Defining this option allows to add some board-specific code (calling
+ a user-provided function show_boot_progress(int) that enables you to
+ show the system's boot progress on some display (for example, some
+ LEDs) on your board. For details see SHOW_BOOT_PROGRESS.
+
endmenu
menu "Boot media"
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2004-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+ifndef CONFIG_SPL_BUILD
+
+# This option is not just y/n - it can have a numeric value
+ifdef CONFIG_BOOT_RETRY_TIME
+obj-y += bootretry.o
+endif
+
+obj-$(CONFIG_CMD_BOOTM) += bootm.o bootm_os.o
+obj-$(CONFIG_CMD_BOOTZ) += bootm.o bootm_os.o
+obj-$(CONFIG_CMD_BOOTI) += bootm.o bootm_os.o
+
+obj-$(CONFIG_CMD_PXE) += pxe_utils.o
+obj-$(CONFIG_CMD_SYSBOOT) += pxe_utils.o
+
+endif
+
+obj-y += image.o image-board.o
+obj-$(CONFIG_ANDROID_AB) += android_ab.o
+obj-$(CONFIG_ANDROID_BOOT_IMAGE) += image-android.o image-android-dt.o
+obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += image-fdt.o
+obj-$(CONFIG_$(SPL_TPL_)FIT_SIGNATURE) += fdt_region.o
+obj-$(CONFIG_$(SPL_TPL_)FIT) += image-fit.o
+obj-$(CONFIG_$(SPL_)MULTI_DTB_FIT) += boot_fit.o common_fit.o
+obj-$(CONFIG_$(SPL_TPL_)IMAGE_SIGN_INFO) += image-sig.o
+obj-$(CONFIG_$(SPL_TPL_)FIT_SIGNATURE) += image-fit-sig.o
+obj-$(CONFIG_$(SPL_TPL_)FIT_CIPHER) += image-cipher.o
+
+obj-$(CONFIG_CMD_ADTIMG) += image-android-dt.o
+
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_SPL_LOAD_FIT) += common_fit.o
+endif
}
#endif /* CONFIG_BOOTM_NETBSD*/
-#ifdef CONFIG_LYNXKDI
-static int do_bootm_lynxkdi(int flag, int argc, char *const argv[],
- bootm_headers_t *images)
-{
- image_header_t *hdr = &images->legacy_hdr_os_copy;
-
- if (flag != BOOTM_STATE_OS_GO)
- return 0;
-
-#if defined(CONFIG_FIT)
- if (!images->legacy_hdr_valid) {
- fit_unsupported_reset("Lynx");
- return 1;
- }
-#endif
-
- lynxkdi_boot((image_header_t *)hdr);
-
- return 1;
-}
-#endif /* CONFIG_LYNXKDI */
-
#ifdef CONFIG_BOOTM_RTEMS
static int do_bootm_rtems(int flag, int argc, char *const argv[],
bootm_headers_t *images)
#ifdef CONFIG_BOOTM_NETBSD
[IH_OS_NETBSD] = do_bootm_netbsd,
#endif
-#ifdef CONFIG_LYNXKDI
- [IH_OS_LYNXOS] = do_bootm_lynxkdi,
-#endif
#ifdef CONFIG_BOOTM_RTEMS
[IH_OS_RTEMS] = do_bootm_rtems,
#endif
debug("## kernel board info at 0x%08lx\n", (ulong)*kbd);
#if defined(DEBUG)
- if (IS_ENABLED(CONFIG_CMD_BDI)
+ if (IS_ENABLED(CONFIG_CMD_BDI))
do_bdinfo(NULL, 0, 0, NULL);
#endif
memset(info, '\0', sizeof(*info));
info->keyname = fdt_getprop(fit, noffset, FIT_KEY_HINT, NULL);
- info->fit = (void *)fit;
+ info->fit = fit;
info->node_offset = noffset;
info->name = algo_name;
info->checksum = image_get_checksum_algo(algo_name);
{ IH_OS_INVALID, "invalid", "Invalid OS", },
{ IH_OS_ARM_TRUSTED_FIRMWARE, "arm-trusted-firmware", "ARM Trusted Firmware" },
{ IH_OS_LINUX, "linux", "Linux", },
-#if defined(CONFIG_LYNXKDI) || defined(USE_HOSTCC)
+#if defined(USE_HOSTCC)
{ IH_OS_LYNXOS, "lynxos", "LynxOS", },
#endif
{ IH_OS_NETBSD, "netbsd", "NetBSD", },
#define MAX_TFTP_PATH_LEN 512
-bool is_pxe;
+int pxe_get_file_size(ulong *sizep)
+{
+ const char *val;
-/*
- * Convert an ethaddr from the environment to the format used by pxelinux
- * filenames based on mac addresses. Convert's ':' to '-', and adds "01-" to
- * the beginning of the ethernet address to indicate a hardware type of
- * Ethernet. Also converts uppercase hex characters into lowercase, to match
- * pxelinux's behavior.
+ val = from_env("filesize");
+ if (!val)
+ return -ENOENT;
+
+ if (strict_strtoul(val, 16, sizep) < 0)
+ return -EINVAL;
+
+ return 0;
+}
+
+/**
+ * format_mac_pxe() - obtain a MAC address in the PXE format
+ *
+ * This produces a MAC-address string in the format for the current ethernet
+ * device:
*
- * Returns 1 for success, -ENOENT if 'ethaddr' is undefined in the
- * environment, or some other value < 0 on error.
+ * 01-aa-bb-cc-dd-ee-ff
+ *
+ * where aa-ff is the MAC address in hex
+ *
+ * @outbuf: Buffer to write string to
+ * @outbuf_len: length of buffer
+ * @return 1 if OK, -ENOSPC if buffer is too small, -ENOENT is there is no
+ * current ethernet device
*/
int format_mac_pxe(char *outbuf, size_t outbuf_len)
{
if (outbuf_len < 21) {
printf("outbuf is too small (%zd < 21)\n", outbuf_len);
-
- return -EINVAL;
+ return -ENOSPC;
}
if (!eth_env_get_enetaddr_by_index("eth", eth_get_dev_index(), ethaddr))
return 1;
}
-/*
- * Returns the directory the file specified in the bootfile env variable is
- * in. If bootfile isn't defined in the environment, return NULL, which should
- * be interpreted as "don't prepend anything to paths".
- */
-static int get_bootfile_path(const char *file_path, char *bootfile_path,
- size_t bootfile_path_size)
-{
- char *bootfile, *last_slash;
- size_t path_len = 0;
-
- /* Only syslinux allows absolute paths */
- if (file_path[0] == '/' && !is_pxe)
- goto ret;
-
- bootfile = from_env("bootfile");
-
- if (!bootfile)
- goto ret;
-
- last_slash = strrchr(bootfile, '/');
-
- if (!last_slash)
- goto ret;
-
- path_len = (last_slash - bootfile) + 1;
-
- if (bootfile_path_size < path_len) {
- printf("bootfile_path too small. (%zd < %zd)\n",
- bootfile_path_size, path_len);
-
- return -1;
- }
-
- strncpy(bootfile_path, bootfile, path_len);
-
- ret:
- bootfile_path[path_len] = '\0';
-
- return 1;
-}
-
-int (*do_getfile)(struct cmd_tbl *cmdtp, const char *file_path,
- char *file_addr);
-
-/*
+/**
+ * get_relfile() - read a file relative to the PXE file
+ *
* As in pxelinux, paths to files referenced from files we retrieve are
* relative to the location of bootfile. get_relfile takes such a path and
* joins it with the bootfile path to get the full path to the target file. If
* the bootfile path is NULL, we use file_path as is.
*
- * Returns 1 for success, or < 0 on error.
+ * @ctx: PXE context
+ * @file_path: File path to read (relative to the PXE file)
+ * @file_addr: Address to load file to
+ * @filesizep: If not NULL, returns the file size in bytes
+ * Returns 1 for success, or < 0 on error
*/
-static int get_relfile(struct cmd_tbl *cmdtp, const char *file_path,
- unsigned long file_addr)
+static int get_relfile(struct pxe_context *ctx, const char *file_path,
+ unsigned long file_addr, ulong *filesizep)
{
size_t path_len;
char relfile[MAX_TFTP_PATH_LEN + 1];
char addr_buf[18];
- int err;
+ ulong size;
+ int ret;
- err = get_bootfile_path(file_path, relfile, sizeof(relfile));
+ if (file_path[0] == '/' && ctx->allow_abs_path)
+ *relfile = '\0';
+ else
+ strncpy(relfile, ctx->bootdir, MAX_TFTP_PATH_LEN);
- if (err < 0)
- return err;
-
- path_len = strlen(file_path);
- path_len += strlen(relfile);
+ path_len = strlen(file_path) + strlen(relfile);
if (path_len > MAX_TFTP_PATH_LEN) {
printf("Base path too long (%s%s)\n", relfile, file_path);
sprintf(addr_buf, "%lx", file_addr);
- return do_getfile(cmdtp, relfile, addr_buf);
+ ret = ctx->getfile(ctx, relfile, addr_buf, &size);
+ if (ret < 0)
+ return log_msg_ret("get", ret);
+ if (filesizep)
+ *filesizep = size;
+
+ return 1;
}
-/*
- * Retrieve the file at 'file_path' to the locate given by 'file_addr'. If
- * 'bootfile' was specified in the environment, the path to bootfile will be
- * prepended to 'file_path' and the resulting path will be used.
+/**
+ * get_pxe_file() - read a file
*
- * Returns 1 on success, or < 0 for error.
+ * The file is read and nul-terminated
+ *
+ * @ctx: PXE context
+ * @file_path: File path to read (relative to the PXE file)
+ * @file_addr: Address to load file to
+ * Returns 1 for success, or < 0 on error
*/
-int get_pxe_file(struct cmd_tbl *cmdtp, const char *file_path,
- unsigned long file_addr)
+int get_pxe_file(struct pxe_context *ctx, const char *file_path,
+ ulong file_addr)
{
- unsigned long config_file_size;
- char *tftp_filesize;
+ ulong size;
int err;
char *buf;
- err = get_relfile(cmdtp, file_path, file_addr);
-
+ err = get_relfile(ctx, file_path, file_addr, &size);
if (err < 0)
return err;
- /*
- * the file comes without a NUL byte at the end, so find out its size
- * and add the NUL byte.
- */
- tftp_filesize = from_env("filesize");
-
- if (!tftp_filesize)
- return -ENOENT;
-
- if (strict_strtoul(tftp_filesize, 16, &config_file_size) < 0)
- return -EINVAL;
-
- buf = map_sysmem(file_addr + config_file_size, 1);
+ buf = map_sysmem(file_addr + size, 1);
*buf = '\0';
unmap_sysmem(buf);
#define PXELINUX_DIR "pxelinux.cfg/"
-/*
- * Retrieves a file in the 'pxelinux.cfg' folder. Since this uses get_pxe_file
- * to do the hard work, the location of the 'pxelinux.cfg' folder is generated
- * from the bootfile path, as described above.
+/**
+ * get_pxelinux_path() - Get a file in the pxelinux.cfg/ directory
*
- * Returns 1 on success or < 0 on error.
+ * @ctx: PXE context
+ * @file: Filename to process (relative to pxelinux.cfg/)
+ * Returns 1 for success, -ENAMETOOLONG if the resulting path is too long.
+ * or other value < 0 on other error
*/
-int get_pxelinux_path(struct cmd_tbl *cmdtp, const char *file,
+int get_pxelinux_path(struct pxe_context *ctx, const char *file,
unsigned long pxefile_addr_r)
{
size_t base_len = strlen(PXELINUX_DIR);
sprintf(path, PXELINUX_DIR "%s", file);
- return get_pxe_file(cmdtp, path, pxefile_addr_r);
+ return get_pxe_file(ctx, path, pxefile_addr_r);
}
-/*
+/**
+ * get_relfile_envaddr() - read a file to an address in an env var
+ *
* Wrapper to make it easier to store the file at file_path in the location
* specified by envaddr_name. file_path will be joined to the bootfile path,
* if any is specified.
*
- * Returns 1 on success or < 0 on error.
+ * @ctx: PXE context
+ * @file_path: File path to read (relative to the PXE file)
+ * @envaddr_name: Name of environment variable which contains the address to
+ * load to
+ * @filesizep: Returns the file size in bytes
+ * Returns 1 on success, -ENOENT if @envaddr_name does not exist as an
+ * environment variable, -EINVAL if its format is not valid hex, or other
+ * value < 0 on other error
*/
-static int get_relfile_envaddr(struct cmd_tbl *cmdtp, const char *file_path,
- const char *envaddr_name)
+static int get_relfile_envaddr(struct pxe_context *ctx, const char *file_path,
+ const char *envaddr_name, ulong *filesizep)
{
unsigned long file_addr;
char *envaddr;
envaddr = from_env(envaddr_name);
-
if (!envaddr)
return -ENOENT;
if (strict_strtoul(envaddr, 16, &file_addr) < 0)
return -EINVAL;
- return get_relfile(cmdtp, file_path, file_addr);
+ return get_relfile(ctx, file_path, file_addr, filesizep);
}
-/*
+/**
+ * label_create() - crate a new PXE label
+ *
* Allocates memory for and initializes a pxe_label. This uses malloc, so the
* result must be free()'d to reclaim the memory.
*
- * Returns NULL if malloc fails.
+ * Returns a pointer to the label, or NULL if out of memory
*/
static struct pxe_label *label_create(void)
{
struct pxe_label *label;
label = malloc(sizeof(struct pxe_label));
-
if (!label)
return NULL;
return label;
}
-/*
- * Free the memory used by a pxe_label, including that used by its name,
- * kernel, append and initrd members, if they're non NULL.
+/**
+ * label_destroy() - free the memory used by a pxe_label
+ *
+ * This frees @label itself as well as memory used by its name,
+ * kernel, config, append, initrd, fdt, fdtdir and fdtoverlay members, if
+ * they're non-NULL.
*
* So - be sure to only use dynamically allocated memory for the members of
* the pxe_label struct, unless you want to clean it up first. These are
* currently only created by the pxe file parsing code.
+ *
+ * @label: Label to free
*/
static void label_destroy(struct pxe_label *label)
{
- if (label->name)
- free(label->name);
-
- if (label->kernel)
- free(label->kernel);
-
- if (label->config)
- free(label->config);
-
- if (label->append)
- free(label->append);
-
- if (label->initrd)
- free(label->initrd);
-
- if (label->fdt)
- free(label->fdt);
-
- if (label->fdtdir)
- free(label->fdtdir);
-
- if (label->fdtoverlays)
- free(label->fdtoverlays);
-
+ free(label->name);
+ free(label->kernel);
+ free(label->config);
+ free(label->append);
+ free(label->initrd);
+ free(label->fdt);
+ free(label->fdtdir);
+ free(label->fdtoverlays);
free(label);
}
-/*
- * Print a label and its string members if they're defined.
+/**
+ * label_print() - Print a label and its string members if they're defined
*
* This is passed as a callback to the menu code for displaying each
* menu entry.
+ *
+ * @data: Label to print (is cast to struct pxe_label *)
*/
static void label_print(void *data)
{
printf("%s:\t%s\n", label->num, c);
}
-/*
- * Boot a label that specified 'localboot'. This requires that the 'localcmd'
- * environment variable is defined. Its contents will be executed as U-Boot
- * command. If the label specified an 'append' line, its contents will be
- * used to overwrite the contents of the 'bootargs' environment variable prior
- * to running 'localcmd'.
+/**
+ * label_localboot() - Boot a label that specified 'localboot'
+ *
+ * This requires that the 'localcmd' environment variable is defined. Its
+ * contents will be executed as U-Boot commands. If the label specified an
+ * 'append' line, its contents will be used to overwrite the contents of the
+ * 'bootargs' environment variable prior to running 'localcmd'.
*
- * Returns 1 on success or < 0 on error.
+ * @label: Label to process
+ * Returns 1 on success or < 0 on error
*/
static int label_localboot(struct pxe_label *label)
{
char *localcmd;
localcmd = from_env("localcmd");
-
if (!localcmd)
return -ENOENT;
return run_command_list(localcmd, strlen(localcmd), 0);
}
-/*
- * Loads fdt overlays specified in 'fdtoverlays'.
+/**
+ * label_boot_fdtoverlay() - Loads fdt overlays specified in 'fdtoverlays'
+ *
+ * @ctx: PXE context
+ * @label: Label to process
*/
#ifdef CONFIG_OF_LIBFDT_OVERLAY
-static void label_boot_fdtoverlay(struct cmd_tbl *cmdtp, struct pxe_label *label)
+static void label_boot_fdtoverlay(struct pxe_context *ctx,
+ struct pxe_label *label)
{
char *fdtoverlay = label->fdtoverlays;
struct fdt_header *working_fdt;
goto skip_overlay;
/* Load overlay file */
- err = get_relfile_envaddr(cmdtp, overlayfile,
- "fdtoverlay_addr_r");
+ err = get_relfile_envaddr(ctx, overlayfile, "fdtoverlay_addr_r",
+ NULL);
if (err < 0) {
printf("Failed loading overlay %s\n", overlayfile);
goto skip_overlay;
}
#endif
-/*
- * Boot according to the contents of a pxe_label.
+/**
+ * label_boot() - Boot according to the contents of a pxe_label
*
* If we can't boot for any reason, we return. A successful boot never
* returns.
*
* If the label specifies an 'append' line, its contents will overwrite that
* of the 'bootargs' environment variable.
+ *
+ * @ctx: PXE context
+ * @label: Label to process
+ * Returns does not return on success, otherwise returns 0 if a localboot
+ * label was processed, or 1 on error
*/
-static int label_boot(struct cmd_tbl *cmdtp, struct pxe_label *label)
+static int label_boot(struct pxe_context *ctx, struct pxe_label *label)
{
char *bootm_argv[] = { "bootm", NULL, NULL, NULL, NULL };
+ char *zboot_argv[] = { "zboot", NULL, "0", NULL, NULL };
+ char *kernel_addr = NULL;
+ char *initrd_addr_str = NULL;
+ char initrd_filesize[10];
char initrd_str[28];
char mac_str[29] = "";
char ip_str[68] = "";
char *fit_addr = NULL;
int bootm_argc = 2;
+ int zboot_argc = 3;
int len = 0;
- ulong kernel_addr;
+ ulong kernel_addr_r;
void *buf;
label_print(label);
}
if (label->initrd) {
- if (get_relfile_envaddr(cmdtp, label->initrd, "ramdisk_addr_r") < 0) {
+ ulong size;
+
+ if (get_relfile_envaddr(ctx, label->initrd, "ramdisk_addr_r",
+ &size) < 0) {
printf("Skipping %s for failure retrieving initrd\n",
label->name);
return 1;
}
- bootm_argv[2] = initrd_str;
- strncpy(bootm_argv[2], env_get("ramdisk_addr_r"), 18);
- strcat(bootm_argv[2], ":");
- strncat(bootm_argv[2], env_get("filesize"), 9);
- bootm_argc = 3;
+ initrd_addr_str = env_get("ramdisk_addr_r");
+ strcpy(initrd_filesize, simple_xtoa(size));
+
+ strncpy(initrd_str, initrd_addr_str, 18);
+ strcat(initrd_str, ":");
+ strncat(initrd_str, initrd_filesize, 9);
}
- if (get_relfile_envaddr(cmdtp, label->kernel, "kernel_addr_r") < 0) {
+ if (get_relfile_envaddr(ctx, label->kernel, "kernel_addr_r",
+ NULL) < 0) {
printf("Skipping %s for failure retrieving kernel\n",
label->name);
return 1;
printf("append: %s\n", finalbootargs);
}
- bootm_argv[1] = env_get("kernel_addr_r");
+ kernel_addr = env_get("kernel_addr_r");
+
/* for FIT, append the configuration identifier */
if (label->config) {
- int len = strlen(bootm_argv[1]) + strlen(label->config) + 1;
+ int len = strlen(kernel_addr) + strlen(label->config) + 1;
fit_addr = malloc(len);
if (!fit_addr) {
printf("malloc fail (FIT address)\n");
return 1;
}
- snprintf(fit_addr, len, "%s%s", bootm_argv[1], label->config);
- bootm_argv[1] = fit_addr;
+ snprintf(fit_addr, len, "%s%s", kernel_addr, label->config);
+ kernel_addr = fit_addr;
}
/*
}
if (fdtfile) {
- int err = get_relfile_envaddr(cmdtp, fdtfile,
- "fdt_addr_r");
+ int err = get_relfile_envaddr(ctx, fdtfile,
+ "fdt_addr_r", NULL);
free(fdtfilefree);
if (err < 0) {
#ifdef CONFIG_OF_LIBFDT_OVERLAY
if (label->fdtoverlays)
- label_boot_fdtoverlay(cmdtp, label);
+ label_boot_fdtoverlay(ctx, label);
#endif
} else {
bootm_argv[3] = NULL;
}
}
+ bootm_argv[1] = kernel_addr;
+ zboot_argv[1] = kernel_addr;
+
+ if (initrd_addr_str) {
+ bootm_argv[2] = initrd_str;
+ bootm_argc = 3;
+
+ zboot_argv[3] = initrd_addr_str;
+ zboot_argv[4] = initrd_filesize;
+ zboot_argc = 5;
+ }
+
if (!bootm_argv[3])
bootm_argv[3] = env_get("fdt_addr");
bootm_argc = 4;
}
- kernel_addr = genimg_get_kernel_addr(bootm_argv[1]);
- buf = map_sysmem(kernel_addr, 0);
+ kernel_addr_r = genimg_get_kernel_addr(kernel_addr);
+ buf = map_sysmem(kernel_addr_r, 0);
/* Try bootm for legacy and FIT format image */
if (genimg_get_format(buf) != IMAGE_FORMAT_INVALID)
- do_bootm(cmdtp, 0, bootm_argc, bootm_argv);
+ do_bootm(ctx->cmdtp, 0, bootm_argc, bootm_argv);
/* Try booting an AArch64 Linux kernel image */
else if (IS_ENABLED(CONFIG_CMD_BOOTI))
- do_booti(cmdtp, 0, bootm_argc, bootm_argv);
+ do_booti(ctx->cmdtp, 0, bootm_argc, bootm_argv);
/* Try booting a Image */
else if (IS_ENABLED(CONFIG_CMD_BOOTZ))
- do_bootz(cmdtp, 0, bootm_argc, bootm_argv);
+ do_bootz(ctx->cmdtp, 0, bootm_argc, bootm_argv);
/* Try booting an x86_64 Linux kernel image */
else if (IS_ENABLED(CONFIG_CMD_ZBOOT))
- do_zboot_parent(cmdtp, 0, bootm_argc, bootm_argv, NULL);
+ do_zboot_parent(ctx->cmdtp, 0, zboot_argc, zboot_argv, NULL);
unmap_sysmem(buf);
cleanup:
- if (fit_addr)
- free(fit_addr);
+ free(fit_addr);
+
return 1;
}
-/*
- * Tokens for the pxe file parser.
- */
+/** enum token_type - Tokens for the pxe file parser */
enum token_type {
T_EOL,
T_STRING,
T_INVALID
};
-/*
- * A token - given by a value and a type.
- */
+/** struct token - token - given by a value and a type */
struct token {
char *val;
enum token_type type;
};
-/*
- * Keywords recognized.
- */
+/* Keywords recognized */
static const struct token keywords[] = {
{"menu", T_MENU},
{"title", T_TITLE},
{NULL, T_INVALID}
};
-/*
+/**
+ * enum lex_state - lexer state
+ *
* Since pxe(linux) files don't have a token to identify the start of a
* literal, we have to keep track of when we're in a state where a literal is
* expected vs when we're in a state a keyword is expected.
L_SLITERAL
};
-/*
- * get_string retrieves a string from *p and stores it as a token in
- * *t.
+/**
+ * get_string() - retrieves a string from *p and stores it as a token in *t.
*
- * get_string used for scanning both string literals and keywords.
+ * This is used for scanning both string literals and keywords.
*
* Characters from *p are copied into t-val until a character equal to
* delim is found, or a NUL byte is reached. If delim has the special value of
* The location of *p is updated to point to the first character after the end
* of the token - the ending delimiter.
*
- * On success, the new value of t->val is returned. Memory for t->val is
- * allocated using malloc and must be free()'d to reclaim it. If insufficient
- * memory is available, NULL is returned.
+ * Memory for t->val is allocated using malloc and must be free()'d to reclaim
+ * it.
+ *
+ * @p: Points to a pointer to the current position in the input being processed.
+ * Updated to point at the first character after the current token
+ * @t: Pointers to a token to fill in
+ * @delim: Delimiter character to look for, either newline or space
+ * @lower: true to convert the string to lower case when storing
+ * Returns the new value of t->val, on success, NULL if out of memory
*/
static char *get_string(char **p, struct token *t, char delim, int lower)
{
*/
b = *p;
e = *p;
-
while (*e) {
if ((delim == ' ' && isspace(*e)) || delim == *e)
break;
t->val[len] = '\0';
- /*
- * Update *p so the caller knows where to continue scanning.
- */
+ /* Update *p so the caller knows where to continue scanning */
*p = e;
-
t->type = T_STRING;
return t->val;
}
-/*
- * Populate a keyword token with a type and value.
+/**
+ * get_keyword() - Populate a keyword token with a type and value
+ *
+ * Updates the ->type field based on the keyword string in @val
+ * @t: Token to populate
*/
static void get_keyword(struct token *t)
{
}
}
-/*
- * Get the next token. We have to keep track of which state we're in to know
- * if we're looking to get a string literal or a keyword.
+/**
+ * get_token() - Get the next token
+ *
+ * We have to keep track of which state we're in to know if we're looking to get
+ * a string literal or a keyword.
*
- * *p is updated to point at the first character after the current token.
+ * @p: Points to a pointer to the current position in the input being processed.
+ * Updated to point at the first character after the current token
*/
static void get_token(char **p, struct token *t, enum lex_state state)
{
*p = c;
}
-/*
- * Increment *c until we get to the end of the current line, or EOF.
+/**
+ * eol_or_eof() - Find end of line
+ *
+ * Increment *c until we get to the end of the current line, or EOF
+ *
+ * @c: Points to a pointer to the current position in the input being processed.
+ * Updated to point at the first character after the current token
*/
static void eol_or_eof(char **c)
{
char *s = *c;
get_token(c, &t, L_SLITERAL);
-
if (t.type != T_STRING) {
printf("Expected string: %.*s\n", (int)(*c - s), s);
return -EINVAL;
return 1;
}
-static int parse_pxefile_top(struct cmd_tbl *cmdtp, char *p, unsigned long base,
+static int parse_pxefile_top(struct pxe_context *ctx, char *p, ulong base,
struct pxe_menu *cfg, int nest_level);
/*
* include, nest_level has already been incremented and doesn't need to be
* incremented here.
*/
-static int handle_include(struct cmd_tbl *cmdtp, char **c, unsigned long base,
+static int handle_include(struct pxe_context *ctx, char **c, unsigned long base,
struct pxe_menu *cfg, int nest_level)
{
char *include_path;
int ret;
err = parse_sliteral(c, &include_path);
-
if (err < 0) {
printf("Expected include path: %.*s\n", (int)(*c - s), s);
return err;
}
- err = get_pxe_file(cmdtp, include_path, base);
-
+ err = get_pxe_file(ctx, include_path, base);
if (err < 0) {
printf("Couldn't retrieve %s\n", include_path);
return err;
}
buf = map_sysmem(base, 0);
- ret = parse_pxefile_top(cmdtp, buf, base, cfg, nest_level);
+ ret = parse_pxefile_top(ctx, buf, base, cfg, nest_level);
unmap_sysmem(buf);
return ret;
* nest_level should be 1 when parsing the top level pxe file, 2 when parsing
* a file it includes, 3 when parsing a file included by that file, and so on.
*/
-static int parse_menu(struct cmd_tbl *cmdtp, char **c, struct pxe_menu *cfg,
+static int parse_menu(struct pxe_context *ctx, char **c, struct pxe_menu *cfg,
unsigned long base, int nest_level)
{
struct token t;
break;
case T_INCLUDE:
- err = handle_include(cmdtp, c, base, cfg, nest_level + 1);
+ err = handle_include(ctx, c, base, cfg, nest_level + 1);
break;
case T_BACKGROUND:
printf("Ignoring malformed menu command: %.*s\n",
(int)(*c - s), s);
}
-
if (err < 0)
return err;
*
* Returns 1 on success, < 0 on error.
*/
-static int parse_pxefile_top(struct cmd_tbl *cmdtp, char *p, unsigned long base,
+static int parse_pxefile_top(struct pxe_context *ctx, char *p, unsigned long base,
struct pxe_menu *cfg, int nest_level)
{
struct token t;
switch (t.type) {
case T_MENU:
cfg->prompt = 1;
- err = parse_menu(cmdtp, &p, cfg,
+ err = parse_menu(ctx, &p, cfg,
base + ALIGN(strlen(b) + 1, 4),
nest_level);
break;
break;
case T_INCLUDE:
- err = handle_include(cmdtp, &p,
+ err = handle_include(ctx, &p,
base + ALIGN(strlen(b), 4), cfg,
nest_level + 1);
break;
}
/*
- * Free the memory used by a pxe_menu and its labels.
*/
void destroy_pxe_menu(struct pxe_menu *cfg)
{
struct list_head *pos, *n;
struct pxe_label *label;
- if (cfg->title)
- free(cfg->title);
-
- if (cfg->default_label)
- free(cfg->default_label);
+ free(cfg->title);
+ free(cfg->default_label);
list_for_each_safe(pos, n, &cfg->labels) {
label = list_entry(pos, struct pxe_label, list);
free(cfg);
}
-/*
- * Entry point for parsing a pxe file. This is only used for the top level
- * file.
- *
- * Returns NULL if there is an error, otherwise, returns a pointer to a
- * pxe_menu struct populated with the results of parsing the pxe file (and any
- * files it includes). The resulting pxe_menu struct can be free()'d by using
- * the destroy_pxe_menu() function.
- */
-struct pxe_menu *parse_pxefile(struct cmd_tbl *cmdtp, unsigned long menucfg)
+struct pxe_menu *parse_pxefile(struct pxe_context *ctx, unsigned long menucfg)
{
struct pxe_menu *cfg;
char *buf;
int r;
cfg = malloc(sizeof(struct pxe_menu));
-
if (!cfg)
return NULL;
INIT_LIST_HEAD(&cfg->labels);
buf = map_sysmem(menucfg, 0);
- r = parse_pxefile_top(cmdtp, buf, menucfg, cfg, 1);
+ r = parse_pxefile_top(ctx, buf, menucfg, cfg, 1);
unmap_sysmem(buf);
-
if (r < 0) {
destroy_pxe_menu(cfg);
return NULL;
*/
m = menu_create(cfg->title, DIV_ROUND_UP(cfg->timeout, 10),
cfg->prompt, NULL, label_print, NULL, NULL);
-
if (!m)
return NULL;
/*
* Try to boot any labels we have yet to attempt to boot.
*/
-static void boot_unattempted_labels(struct cmd_tbl *cmdtp, struct pxe_menu *cfg)
+static void boot_unattempted_labels(struct pxe_context *ctx,
+ struct pxe_menu *cfg)
{
struct list_head *pos;
struct pxe_label *label;
label = list_entry(pos, struct pxe_label, list);
if (!label->attempted)
- label_boot(cmdtp, label);
+ label_boot(ctx, label);
}
}
-/*
- * Boot the system as prescribed by a pxe_menu.
- *
- * Use the menu system to either get the user's choice or the default, based
- * on config or user input. If there is no default or user's choice,
- * attempted to boot labels in the order they were given in pxe files.
- * If the default or user's choice fails to boot, attempt to boot other
- * labels in the order they were given in pxe files.
- *
- * If this function returns, there weren't any labels that successfully
- * booted, or the user interrupted the menu selection via ctrl+c.
- */
-void handle_pxe_menu(struct cmd_tbl *cmdtp, struct pxe_menu *cfg)
+void handle_pxe_menu(struct pxe_context *ctx, struct pxe_menu *cfg)
{
void *choice;
struct menu *m;
if (IS_ENABLED(CONFIG_CMD_BMP)) {
/* display BMP if available */
if (cfg->bmp) {
- if (get_relfile(cmdtp, cfg->bmp, image_load_addr)) {
+ if (get_relfile(ctx, cfg->bmp, image_load_addr, NULL)) {
if (CONFIG_IS_ENABLED(CMD_CLS))
run_command("cls", 0);
bmp_display(image_load_addr,
return;
err = menu_get_choice(m, &choice);
-
menu_destroy(m);
/*
*/
if (err == 1) {
- err = label_boot(cmdtp, choice);
+ err = label_boot(ctx, choice);
if (!err)
return;
} else if (err != -ENOENT) {
return;
}
- boot_unattempted_labels(cmdtp, cfg);
+ boot_unattempted_labels(ctx, cfg);
+}
+
+int pxe_setup_ctx(struct pxe_context *ctx, struct cmd_tbl *cmdtp,
+ pxe_getfile_func getfile, void *userdata,
+ bool allow_abs_path, const char *bootfile)
+{
+ const char *last_slash;
+ size_t path_len = 0;
+
+ memset(ctx, '\0', sizeof(*ctx));
+ ctx->cmdtp = cmdtp;
+ ctx->getfile = getfile;
+ ctx->userdata = userdata;
+ ctx->allow_abs_path = allow_abs_path;
+
+ /* figure out the boot directory, if there is one */
+ if (bootfile && strlen(bootfile) >= MAX_TFTP_PATH_LEN)
+ return -ENOSPC;
+ ctx->bootdir = strdup(bootfile ? bootfile : "");
+ if (!ctx->bootdir)
+ return -ENOMEM;
+
+ if (bootfile) {
+ last_slash = strrchr(bootfile, '/');
+ if (last_slash)
+ path_len = (last_slash - bootfile) + 1;
+ }
+ ctx->bootdir[path_len] = '\0';
+
+ return 0;
+}
+
+void pxe_destroy_ctx(struct pxe_context *ctx)
+{
+ free(ctx->bootdir);
+}
+
+int pxe_process(struct pxe_context *ctx, ulong pxefile_addr_r, bool prompt)
+{
+ struct pxe_menu *cfg;
+
+ cfg = parse_pxefile(ctx, pxefile_addr_r);
+ if (!cfg) {
+ printf("Error parsing config file\n");
+ return 1;
+ }
+
+ if (prompt)
+ cfg->prompt = 1;
+
+ handle_pxe_menu(ctx, cfg);
+
+ destroy_pxe_menu(cfg);
+
+ return 0;
}
obj-$(CONFIG_CMD_PMC) += pmc.o
obj-$(CONFIG_CMD_PSTORE) += pstore.o
obj-$(CONFIG_CMD_PWM) += pwm.o
-obj-$(CONFIG_CMD_PXE) += pxe.o pxe_utils.o
+obj-$(CONFIG_CMD_PXE) += pxe.o
obj-$(CONFIG_CMD_WOL) += wol.o
obj-$(CONFIG_CMD_QFW) += qfw.o
obj-$(CONFIG_CMD_READ) += read.o
obj-$(CONFIG_CMD_SPI) += spi.o
obj-$(CONFIG_CMD_STRINGS) += strings.o
obj-$(CONFIG_CMD_SMC) += smccc.o
-obj-$(CONFIG_CMD_SYSBOOT) += sysboot.o pxe_utils.o
+obj-$(CONFIG_CMD_SYSBOOT) += sysboot.o
obj-$(CONFIG_CMD_STACKPROTECTOR_TEST) += stackprot_test.o
obj-$(CONFIG_CMD_TERMINAL) += terminal.o
obj-$(CONFIG_CMD_TIME) += time.o
{
struct efi_device_path *initrd_path = NULL;
struct efi_load_option lo;
- u16 *dp_str;
efi_status_t ret;
- efi_uintn_t initrd_dp_size;
- const efi_guid_t lf2_initrd_guid = EFI_INITRD_MEDIA_GUID;
ret = efi_deserialize_load_option(&lo, data, size);
if (ret != EFI_SUCCESS) {
lo.attributes);
printf(" label: %ls\n", lo.label);
- dp_str = efi_dp_str(lo.file_path);
- printf(" file_path: %ls\n", dp_str);
- efi_free_pool(dp_str);
+ printf(" file_path: %pD\n", lo.file_path);
- initrd_path = efi_dp_from_lo(&lo, &initrd_dp_size, lf2_initrd_guid);
+ initrd_path = efi_dp_from_lo(&lo, &efi_lf2_initrd_guid);
if (initrd_path) {
- dp_str = efi_dp_str(initrd_path);
- printf(" initrd_path: %ls\n", dp_str);
- efi_free_pool(dp_str);
+ printf(" initrd_path: %pD\n", initrd_path);
efi_free_pool(initrd_path);
}
#include <exports.h>
#include <flash.h>
#include <image.h>
+#include <lmb.h>
#include <mapmem.h>
#include <net.h>
#include <s_record.h>
static ulong load_serial(long offset)
{
+ struct lmb lmb;
char record[SREC_MAXRECLEN + 1]; /* buffer for one S-Record */
char binbuf[SREC_MAXBINLEN]; /* buffer for binary data */
int binlen; /* no. of data bytes in S-Rec. */
ulong start_addr = ~0;
ulong end_addr = 0;
int line_count = 0;
+ long ret;
+
+ lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob);
while (read_record(record, SREC_MAXRECLEN + 1) >= 0) {
type = srec_decode(record, &binlen, &addr, binbuf);
} else
#endif
{
+ ret = lmb_reserve(&lmb, store_addr, binlen);
+ if (ret) {
+ printf("\nCannot overwrite reserved area (%08lx..%08lx)\n",
+ store_addr, store_addr + binlen);
+ return ret;
+ }
memcpy((char *)(store_addr), binbuf, binlen);
+ lmb_free(&lmb, store_addr, binlen);
}
if ((store_addr) < start_addr)
start_addr = store_addr;
}
#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
-static int parse_hwpart_user(struct mmc_hwpart_conf *pconf,
+static void parse_hwpart_user_enh_size(struct mmc *mmc,
+ struct mmc_hwpart_conf *pconf,
+ char *argv)
+{
+ int ret;
+
+ pconf->user.enh_size = 0;
+
+ if (!strcmp(argv, "-")) { /* The rest of eMMC */
+ ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
+ ret = mmc_send_ext_csd(mmc, ext_csd);
+ if (ret)
+ return;
+ /* This value is in 512B block units */
+ pconf->user.enh_size =
+ ((ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT + 2] << 16) +
+ (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT + 1] << 8) +
+ ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT]) * 1024 *
+ ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] *
+ ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
+ pconf->user.enh_size -= pconf->user.enh_start;
+ } else {
+ pconf->user.enh_size = dectoul(argv, NULL);
+ }
+}
+
+static int parse_hwpart_user(struct mmc *mmc, struct mmc_hwpart_conf *pconf,
int argc, char *const argv[])
{
int i = 0;
return -1;
pconf->user.enh_start =
dectoul(argv[i + 1], NULL);
- pconf->user.enh_size =
- dectoul(argv[i + 2], NULL);
+ parse_hwpart_user_enh_size(mmc, pconf, argv[i + 2]);
i += 3;
} else if (!strcmp(argv[i], "wrrel")) {
if (i + 1 >= argc)
if (!mmc)
return CMD_RET_FAILURE;
+ if (IS_SD(mmc)) {
+ puts("SD doesn't support partitioning\n");
+ return CMD_RET_FAILURE;
+ }
+
if (argc < 1)
return CMD_RET_USAGE;
i = 1;
while (i < argc) {
if (!strcmp(argv[i], "user")) {
i++;
- r = parse_hwpart_user(&pconf, argc-i, &argv[i]);
+ r = parse_hwpart_user(mmc, &pconf, argc - i, &argv[i]);
if (r < 0)
return CMD_RET_USAGE;
i += r;
};
#endif
-/* Structure of the main header, version 1 (Armada 370/38x/XP) */
+/* Structure of the main header, version 1 (Armada 370/XP/375/38x/39x) */
struct a38x_main_hdr_v1 {
u8 blockid; /* 0x0 */
u8 flags; /* 0x1 */
- u16 reserved2; /* 0x2-0x3 */
+ u16 nandpagesize; /* 0x2-0x3 */
u32 blocksize; /* 0x4-0x7 */
u8 version; /* 0x8 */
u8 headersz_msb; /* 0x9 */
* and/or modified under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
+ *
+ * The function nand_biterror() in this file is inspired from
+ * mtd-utils/nand-utils/nandflipbits.c which was released under GPLv2
+ * only
*/
#include <common.h>
u8 *part_num, struct part_info **part);
#endif
+#define MAX_NUM_PAGES 64
+
+static int nand_biterror(struct mtd_info *mtd, ulong off, int bit)
+{
+ int ret = 0;
+ int page = 0;
+ ulong block_off;
+ u_char *datbuf[MAX_NUM_PAGES]; /* Data and OOB */
+ u_char data;
+ int pages_per_blk = mtd->erasesize / mtd->writesize;
+ struct erase_info einfo;
+
+ if (pages_per_blk > MAX_NUM_PAGES) {
+ printf("Too many pages in one erase block\n");
+ return 1;
+ }
+
+ if (bit < 0 || bit > 7) {
+ printf("bit position 0 to 7 is allowed\n");
+ return 1;
+ }
+
+ /* Allocate memory */
+ memset(datbuf, 0, sizeof(datbuf));
+ for (page = 0; page < pages_per_blk ; page++) {
+ datbuf[page] = malloc(mtd->writesize + mtd->oobsize);
+ if (!datbuf[page]) {
+ printf("No memory for page buffer\n");
+ ret = -ENOMEM;
+ goto free_memory;
+ }
+ }
+
+ /* Align to erase block boundary */
+ block_off = off & (~(mtd->erasesize - 1));
+
+ /* Read out memory as first step */
+ for (page = 0; page < pages_per_blk ; page++) {
+ struct mtd_oob_ops ops;
+ loff_t addr = (loff_t)block_off;
+
+ memset(&ops, 0, sizeof(ops));
+ ops.datbuf = datbuf[page];
+ ops.oobbuf = datbuf[page] + mtd->writesize;
+ ops.len = mtd->writesize;
+ ops.ooblen = mtd->oobsize;
+ ops.mode = MTD_OPS_RAW;
+ ret = mtd_read_oob(mtd, addr, &ops);
+ if (ret < 0) {
+ printf("Error (%d) reading page %08lx\n",
+ ret, block_off);
+ ret = 1;
+ goto free_memory;
+ }
+ block_off += mtd->writesize;
+ }
+
+ /* Erase the block */
+ memset(&einfo, 0, sizeof(einfo));
+ einfo.mtd = mtd;
+ /* Align to erase block boundary */
+ einfo.addr = (loff_t)(off & (~(mtd->erasesize - 1)));
+ einfo.len = mtd->erasesize;
+ ret = mtd_erase(mtd, &einfo);
+ if (ret < 0) {
+ printf("Error (%d) nand_erase_nand page %08llx\n",
+ ret, einfo.addr);
+ ret = 1;
+ goto free_memory;
+ }
+
+ /* Twist a bit in data part */
+ block_off = off & (mtd->erasesize - 1);
+ data = datbuf[block_off / mtd->writesize][block_off % mtd->writesize];
+ data ^= (1 << bit);
+ datbuf[block_off / mtd->writesize][block_off % mtd->writesize] = data;
+
+ printf("Flip data at 0x%lx with xor 0x%02x (bit=%d) to value=0x%02x\n",
+ off, (1 << bit), bit, data);
+
+ /* Write back twisted data and unmodified OOB */
+ /* Align to erase block boundary */
+ block_off = off & (~(mtd->erasesize - 1));
+ for (page = 0; page < pages_per_blk; page++) {
+ struct mtd_oob_ops ops;
+ loff_t addr = (loff_t)block_off;
+
+ memset(&ops, 0, sizeof(ops));
+ ops.datbuf = datbuf[page];
+ ops.oobbuf = datbuf[page] + mtd->writesize;
+ ops.len = mtd->writesize;
+ ops.ooblen = mtd->oobsize;
+ ops.mode = MTD_OPS_RAW;
+ ret = mtd_write_oob(mtd, addr, &ops);
+ if (ret < 0) {
+ printf("Error (%d) write page %08lx\n", ret, block_off);
+ ret = 1;
+ goto free_memory;
+ }
+ block_off += mtd->writesize;
+ }
+
+free_memory:
+ for (page = 0; page < pages_per_blk ; page++) {
+ if (datbuf[page])
+ free(datbuf[page]);
+ }
+ return ret;
+}
+
static int nand_dump(struct mtd_info *mtd, ulong off, int only_oob,
int repeat)
{
}
if (strcmp(cmd, "biterr") == 0) {
- /* todo */
- return 1;
+ int bit;
+
+ if (argc != 4)
+ goto usage;
+
+ off = (int)simple_strtoul(argv[2], NULL, 16);
+ bit = (int)simple_strtoul(argv[3], NULL, 10);
+ ret = nand_biterror(mtd, off, bit);
+ return ret;
}
#ifdef CONFIG_CMD_NAND_LOCK_UNLOCK
"nand scrub [-y] off size | scrub.part partition | scrub.chip\n"
" really clean NAND erasing bad blocks (UNSAFE)\n"
"nand markbad off [...] - mark bad block(s) at offset (UNSAFE)\n"
- "nand biterr off - make a bit error at offset (UNSAFE)"
+ "nand biterr off bit - make a bit error at offset and bit position (UNSAFE)"
#ifdef CONFIG_CMD_NAND_LOCK_UNLOCK
"\n"
"nand lock [tight] [status]\n"
#include <env.h>
#include <env_internal.h>
#include <log.h>
-#include <net.h>
#include <search.h>
#include <errno.h>
#include <malloc.h>
#include <asm/global_data.h>
#include <linux/bitops.h>
#include <u-boot/crc.h>
-#include <watchdog.h>
#include <linux/stddef.h>
#include <asm/byteorder.h>
#include <asm/io.h>
return _do_env_set(0, 3, (char * const *)argv, H_PROGRAMMATIC);
}
-/**
- * Set an environment variable to an integer value
- *
- * @param varname Environment variable to set
- * @param value Value to set it to
- * @return 0 if ok, 1 on error
- */
-int env_set_ulong(const char *varname, ulong value)
-{
- /* TODO: this should be unsigned */
- char *str = simple_itoa(value);
-
- return env_set(varname, str);
-}
-
-/**
- * Set an environment variable to an value in hex
- *
- * @param varname Environment variable to set
- * @param value Value to set it to
- * @return 0 if ok, 1 on error
- */
-int env_set_hex(const char *varname, ulong value)
-{
- char str[17];
-
- sprintf(str, "%lx", value);
- return env_set(varname, str);
-}
-
-ulong env_get_hex(const char *varname, ulong default_val)
-{
- const char *s;
- ulong value;
- char *endp;
-
- s = env_get(varname);
- if (s)
- value = hextoul(s, &endp);
- if (!s || endp == s)
- return default_val;
-
- return value;
-}
-
-int eth_env_get_enetaddr(const char *name, uint8_t *enetaddr)
-{
- string_to_enetaddr(env_get(name), enetaddr);
- return is_valid_ethaddr(enetaddr);
-}
-
-int eth_env_set_enetaddr(const char *name, const uint8_t *enetaddr)
-{
- char buf[ARP_HLEN_ASCII + 1];
-
- if (eth_env_get_enetaddr(name, (uint8_t *)buf))
- return -EEXIST;
-
- sprintf(buf, "%pM", enetaddr);
-
- return env_set(name, buf);
-}
-
#ifndef CONFIG_SPL_BUILD
static int do_env_set(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
}
}
#endif /* CONFIG_CMD_EDITENV */
-#endif /* CONFIG_SPL_BUILD */
-
-/*
- * Look up variable from environment,
- * return address of storage for that variable,
- * or NULL if not found
- */
-char *env_get(const char *name)
-{
- if (gd->flags & GD_FLG_ENV_READY) { /* after import into hashtable */
- struct env_entry e, *ep;
-
- WATCHDOG_RESET();
-
- e.key = name;
- e.data = NULL;
- hsearch_r(e, ENV_FIND, &ep, &env_htab, 0);
-
- return ep ? ep->data : NULL;
- }
-
- /* restricted capabilities before import */
- if (env_get_f(name, (char *)(gd->env_buf), sizeof(gd->env_buf)) > 0)
- return (char *)(gd->env_buf);
-
- return NULL;
-}
-/*
- * Like env_get, but prints an error if envvar isn't defined in the
- * environment. It always returns what env_get does, so it can be used in
- * place of env_get without changing error handling otherwise.
- */
-char *from_env(const char *envvar)
-{
- char *ret;
-
- ret = env_get(envvar);
-
- if (!ret)
- printf("missing environment variable: %s\n", envvar);
-
- return ret;
-}
-
-/*
- * Look up variable from environment for restricted C runtime env.
- */
-int env_get_f(const char *name, char *buf, unsigned len)
-{
- int i, nxt, c;
-
- for (i = 0; env_get_char(i) != '\0'; i = nxt + 1) {
- int val, n;
-
- for (nxt = i; (c = env_get_char(nxt)) != '\0'; ++nxt) {
- if (c < 0)
- return c;
- if (nxt >= CONFIG_ENV_SIZE)
- return -1;
- }
-
- val = env_match((uchar *)name, i);
- if (val < 0)
- continue;
-
- /* found; copy out */
- for (n = 0; n < len; ++n, ++buf) {
- c = env_get_char(val++);
- if (c < 0)
- return c;
- *buf = c;
- if (*buf == '\0')
- return n;
- }
-
- if (n)
- *--buf = '\0';
-
- printf("env_buf [%u bytes] too small for value of \"%s\"\n",
- len, name);
-
- return n;
- }
-
- return -1;
-}
-
-/**
- * Decode the integer value of an environment variable and return it.
- *
- * @param name Name of environment variable
- * @param base Number base to use (normally 10, or 16 for hex)
- * @param default_val Default value to return if the variable is not
- * found
- * @return the decoded value, or default_val if not found
- */
-ulong env_get_ulong(const char *name, int base, ulong default_val)
-{
- /*
- * We can use env_get() here, even before relocation, since the
- * environment variable value is an integer and thus short.
- */
- const char *str = env_get(name);
-
- return str ? simple_strtoul(str, NULL, base) : default_val;
-}
-
-#ifndef CONFIG_SPL_BUILD
#if defined(CONFIG_CMD_SAVEENV) && defined(ENV_IS_IN_DEVICE)
static int do_env_save(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
#endif /* CONFIG_SPL_BUILD */
-int env_match(uchar *s1, int i2)
-{
- if (s1 == NULL)
- return -1;
-
- while (*s1 == env_get_char(i2++))
- if (*s1++ == '=')
- return i2;
-
- if (*s1 == '\0' && env_get_char(i2-1) == '=')
- return i2;
-
- return -1;
-}
-
#ifndef CONFIG_SPL_BUILD
static int do_env_default(struct cmd_tbl *cmdtp, int flag,
int argc, char *const argv[])
static int onenand_block_erase(u32 start, u32 size, int force)
{
struct onenand_chip *this = mtd->priv;
- struct erase_info instr = {
- .callback = NULL,
- };
+ struct erase_info instr = {};
loff_t ofs;
int ret;
int blocksize = 1 << this->erase_shift;
static int onenand_block_test(u32 start, u32 size)
{
struct onenand_chip *this = mtd->priv;
- struct erase_info instr = {
- .callback = NULL,
- .priv = 0,
- };
+ struct erase_info instr = {};
int blocks;
loff_t ofs;
NULL
};
-static int do_get_tftp(struct cmd_tbl *cmdtp, const char *file_path,
- char *file_addr)
+static int do_get_tftp(struct pxe_context *ctx, const char *file_path,
+ char *file_addr, ulong *sizep)
{
char *tftp_argv[] = {"tftp", NULL, NULL, NULL};
+ int ret;
tftp_argv[1] = file_addr;
tftp_argv[2] = (void *)file_path;
- if (do_tftpb(cmdtp, 0, 3, tftp_argv))
+ if (do_tftpb(ctx->cmdtp, 0, 3, tftp_argv))
return -ENOENT;
+ ret = pxe_get_file_size(sizep);
+ if (ret)
+ return log_msg_ret("tftp", ret);
+ ctx->pxe_file_size = *sizep;
return 1;
}
*
* Returns 1 on success or < 0 on error.
*/
-static int pxe_uuid_path(struct cmd_tbl *cmdtp, unsigned long pxefile_addr_r)
+static int pxe_uuid_path(struct pxe_context *ctx, unsigned long pxefile_addr_r)
{
char *uuid_str;
if (!uuid_str)
return -ENOENT;
- return get_pxelinux_path(cmdtp, uuid_str, pxefile_addr_r);
+ return get_pxelinux_path(ctx, uuid_str, pxefile_addr_r);
}
/*
*
* Returns 1 on success or < 0 on error.
*/
-static int pxe_mac_path(struct cmd_tbl *cmdtp, unsigned long pxefile_addr_r)
+static int pxe_mac_path(struct pxe_context *ctx, unsigned long pxefile_addr_r)
{
char mac_str[21];
int err;
if (err < 0)
return err;
- return get_pxelinux_path(cmdtp, mac_str, pxefile_addr_r);
+ return get_pxelinux_path(ctx, mac_str, pxefile_addr_r);
}
/*
*
* Returns 1 on success or < 0 on error.
*/
-static int pxe_ipaddr_paths(struct cmd_tbl *cmdtp, unsigned long pxefile_addr_r)
+static int pxe_ipaddr_paths(struct pxe_context *ctx, unsigned long pxefile_addr_r)
{
char ip_addr[9];
int mask_pos, err;
sprintf(ip_addr, "%08X", ntohl(net_ip.s_addr));
for (mask_pos = 7; mask_pos >= 0; mask_pos--) {
- err = get_pxelinux_path(cmdtp, ip_addr, pxefile_addr_r);
+ err = get_pxelinux_path(ctx, ip_addr, pxefile_addr_r);
if (err > 0)
return err;
return -ENOENT;
}
+
+int pxe_get(ulong pxefile_addr_r, char **bootdirp, ulong *sizep)
+{
+ struct cmd_tbl cmdtp[] = {}; /* dummy */
+ struct pxe_context ctx;
+ int i;
+
+ if (pxe_setup_ctx(&ctx, cmdtp, do_get_tftp, NULL, false,
+ env_get("bootfile")))
+ return -ENOMEM;
+ /*
+ * Keep trying paths until we successfully get a file we're looking
+ * for.
+ */
+ if (pxe_uuid_path(&ctx, pxefile_addr_r) > 0 ||
+ pxe_mac_path(&ctx, pxefile_addr_r) > 0 ||
+ pxe_ipaddr_paths(&ctx, pxefile_addr_r) > 0)
+ goto done;
+
+ i = 0;
+ while (pxe_default_paths[i]) {
+ if (get_pxelinux_path(&ctx, pxe_default_paths[i],
+ pxefile_addr_r) > 0)
+ goto done;
+ i++;
+ }
+
+ pxe_destroy_ctx(&ctx);
+
+ return -ENOENT;
+done:
+ *bootdirp = env_get("bootfile");
+
+ /*
+ * The PXE file size is returned but not the name. It is probably not
+ * that useful.
+ */
+ *sizep = ctx.pxe_file_size;
+ pxe_destroy_ctx(&ctx);
+
+ return 0;
+}
+
/*
* Entry point for the 'pxe get' command.
* This Follows pxelinux's rules to download a config file from a tftp server.
do_pxe_get(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
char *pxefile_addr_str;
- unsigned long pxefile_addr_r;
- int err, i = 0;
-
- do_getfile = do_get_tftp;
+ ulong pxefile_addr_r;
+ char *fname;
+ ulong size;
+ int ret;
if (argc != 1)
return CMD_RET_USAGE;
if (!pxefile_addr_str)
return 1;
- err = strict_strtoul(pxefile_addr_str, 16,
+ ret = strict_strtoul(pxefile_addr_str, 16,
(unsigned long *)&pxefile_addr_r);
- if (err < 0)
+ if (ret < 0)
return 1;
- /*
- * Keep trying paths until we successfully get a file we're looking
- * for.
- */
- if (pxe_uuid_path(cmdtp, pxefile_addr_r) > 0 ||
- pxe_mac_path(cmdtp, pxefile_addr_r) > 0 ||
- pxe_ipaddr_paths(cmdtp, pxefile_addr_r) > 0) {
- printf("Config file found\n");
-
- return 0;
+ ret = pxe_get(pxefile_addr_r, &fname, &size);
+ switch (ret) {
+ case 0:
+ printf("Config file '%s' found\n", fname);
+ break;
+ case -ENOMEM:
+ printf("Out of memory\n");
+ return CMD_RET_FAILURE;
+ default:
+ printf("Config file not found\n");
+ return CMD_RET_FAILURE;
}
- while (pxe_default_paths[i]) {
- if (get_pxelinux_path(cmdtp, pxe_default_paths[i],
- pxefile_addr_r) > 0) {
- printf("Config file found\n");
- return 0;
- }
- i++;
- }
-
- printf("Config file not found\n");
-
- return 1;
+ return 0;
}
/*
do_pxe_boot(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
unsigned long pxefile_addr_r;
- struct pxe_menu *cfg;
char *pxefile_addr_str;
-
- do_getfile = do_get_tftp;
+ struct pxe_context ctx;
+ int ret;
if (argc == 1) {
pxefile_addr_str = from_env("pxefile_addr_r");
return 1;
}
- cfg = parse_pxefile(cmdtp, pxefile_addr_r);
-
- if (!cfg) {
- printf("Error parsing config file\n");
- return 1;
+ if (pxe_setup_ctx(&ctx, cmdtp, do_get_tftp, NULL, false,
+ env_get("bootfile"))) {
+ printf("Out of memory\n");
+ return CMD_RET_FAILURE;
}
-
- handle_pxe_menu(cmdtp, cfg);
-
- destroy_pxe_menu(cfg);
+ ret = pxe_process(&ctx, pxefile_addr_r, false);
+ pxe_destroy_ctx(&ctx);
+ if (ret)
+ return CMD_RET_FAILURE;
copy_filename(net_boot_file_name, "", sizeof(net_boot_file_name));
if (argc < 2)
return CMD_RET_USAGE;
- is_pxe = true;
-
/* drop initial "pxe" arg */
argc--;
argv++;
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-
-#ifndef __PXE_UTILS_H
-#define __PXE_UTILS_H
-
-#include <linux/list.h>
-
-/*
- * A note on the pxe file parser.
- *
- * We're parsing files that use syslinux grammar, which has a few quirks.
- * String literals must be recognized based on context - there is no
- * quoting or escaping support. There's also nothing to explicitly indicate
- * when a label section completes. We deal with that by ending a label
- * section whenever we see a line that doesn't include.
- *
- * As with the syslinux family, this same file format could be reused in the
- * future for non pxe purposes. The only action it takes during parsing that
- * would throw this off is handling of include files. It assumes we're using
- * pxe, and does a tftp download of a file listed as an include file in the
- * middle of the parsing operation. That could be handled by refactoring it to
- * take a 'include file getter' function.
- */
-
-/*
- * Describes a single label given in a pxe file.
- *
- * Create these with the 'label_create' function given below.
- *
- * name - the name of the menu as given on the 'menu label' line.
- * kernel - the path to the kernel file to use for this label.
- * append - kernel command line to use when booting this label
- * initrd - path to the initrd to use for this label.
- * attempted - 0 if we haven't tried to boot this label, 1 if we have.
- * localboot - 1 if this label specified 'localboot', 0 otherwise.
- * list - lets these form a list, which a pxe_menu struct will hold.
- */
-struct pxe_label {
- char num[4];
- char *name;
- char *menu;
- char *kernel;
- char *config;
- char *append;
- char *initrd;
- char *fdt;
- char *fdtdir;
- char *fdtoverlays;
- int ipappend;
- int attempted;
- int localboot;
- int localboot_val;
- struct list_head list;
-};
-
-/*
- * Describes a pxe menu as given via pxe files.
- *
- * title - the name of the menu as given by a 'menu title' line.
- * default_label - the name of the default label, if any.
- * bmp - the bmp file name which is displayed in background
- * timeout - time in tenths of a second to wait for a user key-press before
- * booting the default label.
- * prompt - if 0, don't prompt for a choice unless the timeout period is
- * interrupted. If 1, always prompt for a choice regardless of
- * timeout.
- * labels - a list of labels defined for the menu.
- */
-struct pxe_menu {
- char *title;
- char *default_label;
- char *bmp;
- int timeout;
- int prompt;
- struct list_head labels;
-};
-
-extern bool is_pxe;
-
-extern int (*do_getfile)(struct cmd_tbl *cmdtp, const char *file_path,
- char *file_addr);
-void destroy_pxe_menu(struct pxe_menu *cfg);
-int get_pxe_file(struct cmd_tbl *cmdtp, const char *file_path,
- unsigned long file_addr);
-int get_pxelinux_path(struct cmd_tbl *cmdtp, const char *file,
- unsigned long pxefile_addr_r);
-void handle_pxe_menu(struct cmd_tbl *cmdtp, struct pxe_menu *cfg);
-struct pxe_menu *parse_pxefile(struct cmd_tbl *cmdtp, unsigned long menucfg);
-int format_mac_pxe(char *outbuf, size_t outbuf_len);
-
-#endif /* __PXE_UTILS_H */
static int do_sbi(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
- int i;
+ int i, impl_id;
long ret;
ret = sbi_get_spec_version();
if (ret >= 0)
- printf("SBI %ld.%ld\n", ret >> 24, ret & 0xffffff);
- ret = sbi_get_impl_id();
- if (ret >= 0) {
+ printf("SBI %ld.%ld", ret >> 24, ret & 0xffffff);
+ impl_id = sbi_get_impl_id();
+ if (impl_id >= 0) {
for (i = 0; i < ARRAY_SIZE(implementations); ++i) {
- if (ret == implementations[i].id) {
- printf("%s\n", implementations[i].name);
+ if (impl_id == implementations[i].id) {
+ long vers;
+
+ printf("\n%s ", implementations[i].name);
+ ret = sbi_get_impl_version(&vers);
+ if (ret < 0)
+ break;
+ if (impl_id == 1)
+ printf("%ld.%ld",
+ vers >> 16, vers & 0xffff);
+ else
+ printf("0x%lx", vers);
break;
}
}
if (i == ARRAY_SIZE(implementations))
- printf("Unknown implementation ID %ld\n", ret);
+ printf("Unknown implementation ID %ld", ret);
}
- printf("Extensions:\n");
+ printf("\nExtensions:\n");
for (i = 0; i < ARRAY_SIZE(extensions); ++i) {
ret = sbi_probe_extension(extensions[i].id);
if (ret > 0)
#include <command.h>
#include <env.h>
#include <fs.h>
-#include "pxe_utils.h"
+#include <pxe_utils.h>
-static char *fs_argv[5];
-
-static int do_get_ext2(struct cmd_tbl *cmdtp, const char *file_path,
- char *file_addr)
-{
-#ifdef CONFIG_CMD_EXT2
- fs_argv[0] = "ext2load";
- fs_argv[3] = file_addr;
- fs_argv[4] = (void *)file_path;
-
- if (!do_ext2load(cmdtp, 0, 5, fs_argv))
- return 1;
-#endif
- return -ENOENT;
-}
-
-static int do_get_fat(struct cmd_tbl *cmdtp, const char *file_path,
- char *file_addr)
-{
-#ifdef CONFIG_CMD_FAT
- fs_argv[0] = "fatload";
- fs_argv[3] = file_addr;
- fs_argv[4] = (void *)file_path;
-
- if (!do_fat_fsload(cmdtp, 0, 5, fs_argv))
- return 1;
-#endif
- return -ENOENT;
-}
-
-static int do_get_any(struct cmd_tbl *cmdtp, const char *file_path,
- char *file_addr)
+/**
+ * struct sysboot_info - useful information for sysboot helpers
+ *
+ * @fstype: Filesystem type (FS_TYPE_...)
+ * @ifname: Interface name (e.g. "ide", "scsi")
+ * @dev_part_str is in the format:
+ * <dev>.<hw_part>:<part> where <dev> is the device number,
+ * <hw_part> is the optional hardware partition number and
+ * <part> is the partition number
+ */
+struct sysboot_info {
+ int fstype;
+ const char *ifname;
+ const char *dev_part_str;
+};
+
+static int sysboot_read_file(struct pxe_context *ctx, const char *file_path,
+ char *file_addr, ulong *sizep)
{
-#ifdef CONFIG_CMD_FS_GENERIC
- fs_argv[0] = "load";
- fs_argv[3] = file_addr;
- fs_argv[4] = (void *)file_path;
+ struct sysboot_info *info = ctx->userdata;
+ loff_t len_read;
+ ulong addr;
+ int ret;
+
+ addr = simple_strtoul(file_addr, NULL, 16);
+ ret = fs_set_blk_dev(info->ifname, info->dev_part_str, info->fstype);
+ if (ret)
+ return ret;
+ ret = fs_read(file_path, addr, 0, 0, &len_read);
+ if (ret)
+ return ret;
+ *sizep = len_read;
- if (!do_load(cmdtp, 0, 5, fs_argv, FS_TYPE_ANY))
- return 1;
-#endif
- return -ENOENT;
+ return 0;
}
/*
char *const argv[])
{
unsigned long pxefile_addr_r;
- struct pxe_menu *cfg;
+ struct pxe_context ctx;
char *pxefile_addr_str;
+ struct sysboot_info info;
char *filename;
int prompt = 0;
-
- is_pxe = false;
+ int ret;
if (argc > 1 && strstr(argv[1], "-p")) {
prompt = 1;
}
if (strstr(argv[3], "ext2")) {
- do_getfile = do_get_ext2;
+ info.fstype = FS_TYPE_EXT;
} else if (strstr(argv[3], "fat")) {
- do_getfile = do_get_fat;
+ info.fstype = FS_TYPE_FAT;
} else if (strstr(argv[3], "any")) {
- do_getfile = do_get_any;
+ info.fstype = FS_TYPE_ANY;
} else {
printf("Invalid filesystem: %s\n", argv[3]);
return 1;
}
- fs_argv[1] = argv[1];
- fs_argv[2] = argv[2];
+ info.ifname = argv[1];
+ info.dev_part_str = argv[2];
if (strict_strtoul(pxefile_addr_str, 16, &pxefile_addr_r) < 0) {
printf("Invalid pxefile address: %s\n", pxefile_addr_str);
return 1;
}
- if (get_pxe_file(cmdtp, filename, pxefile_addr_r) < 0) {
- printf("Error reading config file\n");
- return 1;
+ if (pxe_setup_ctx(&ctx, cmdtp, sysboot_read_file, &info, true,
+ filename)) {
+ printf("Out of memory\n");
+ return CMD_RET_FAILURE;
}
- cfg = parse_pxefile(cmdtp, pxefile_addr_r);
-
- if (!cfg) {
- printf("Error parsing config file\n");
+ if (get_pxe_file(&ctx, filename, pxefile_addr_r) < 0) {
+ printf("Error reading config file\n");
+ pxe_destroy_ctx(&ctx);
return 1;
}
- if (prompt)
- cfg->prompt = 1;
-
- handle_pxe_menu(cmdtp, cfg);
-
- destroy_pxe_menu(cfg);
+ ret = pxe_process(&ctx, pxefile_addr_r, prompt);
+ pxe_destroy_ctx(&ctx);
+ if (ret)
+ return CMD_RET_FAILURE;
return 0;
}
{
int tlv_end;
int curr_tlv;
+#ifdef DEBUG
+ int i;
+#endif
struct tlvinfo_header *eeprom_hdr = to_header(eeprom);
struct tlvinfo_tlv *eeprom_tlv;
if (!devnum_part_str)
break;
- partnum = blk_get_device_part_str(devtype, devnum_part_str,
- &block_dev, &info, 1);
+ partnum = part_get_info_by_dev_and_name_or_num(devtype, devnum_part_str,
+ &block_dev, &info, 1);
if (partnum < 0)
goto cleanup;
-source "common/Kconfig.boot"
-
menu "Console"
config MENU
obj-$(CONFIG_HUSH_PARSER) += cli_hush.o
obj-$(CONFIG_AUTOBOOT) += autoboot.o
-# This option is not just y/n - it can have a numeric value
-ifdef CONFIG_BOOT_RETRY_TIME
-obj-y += bootretry.o
-endif
-
# # boards
obj-y += board_f.o
obj-y += board_r.o
obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
obj-$(CONFIG_DISPLAY_BOARDINFO_LATE) += board_info.o
-obj-$(CONFIG_CMD_BOOTM) += bootm.o bootm_os.o
-obj-$(CONFIG_CMD_BOOTZ) += bootm.o bootm_os.o
-obj-$(CONFIG_CMD_BOOTI) += bootm.o bootm_os.o
-
obj-$(CONFIG_CMD_BEDBUG) += bedbug.o
obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += fdt_support.o
obj-$(CONFIG_MII) += miiphyutil.o
endif
obj-$(CONFIG_LCD_ROTATION) += lcd_console_rotation.o
obj-$(CONFIG_LCD_DT_SIMPLEFB) += lcd_simplefb.o
-obj-$(CONFIG_LYNXKDI) += lynxkdi.o
obj-$(CONFIG_MENU) += menu.o
obj-$(CONFIG_UPDATE_COMMON) += update.o
obj-$(CONFIG_USB_KEYBOARD) += usb_kbd.o
ifdef CONFIG_SPL_DFU
obj-$(CONFIG_DFU_OVER_USB) += dfu.o
endif
-obj-$(CONFIG_SPL_LOAD_FIT) += common_fit.o
obj-$(CONFIG_SPL_NET) += miiphyutil.o
obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += fdt_support.o
endif
endif
-obj-y += image.o image-board.o
obj-$(CONFIG_$(SPL_TPL_)HASH) += hash.o
-obj-$(CONFIG_ANDROID_AB) += android_ab.o
-obj-$(CONFIG_ANDROID_BOOT_IMAGE) += image-android.o image-android-dt.o
-obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += image-fdt.o
-obj-$(CONFIG_$(SPL_TPL_)FIT_SIGNATURE) += fdt_region.o
-obj-$(CONFIG_$(SPL_TPL_)FIT) += image-fit.o
-obj-$(CONFIG_$(SPL_)MULTI_DTB_FIT) += boot_fit.o common_fit.o
-obj-$(CONFIG_$(SPL_TPL_)IMAGE_SIGN_INFO) += image-sig.o
-obj-$(CONFIG_$(SPL_TPL_)FIT_SIGNATURE) += image-fit-sig.o
-obj-$(CONFIG_$(SPL_TPL_)FIT_CIPHER) += image-cipher.o
obj-$(CONFIG_IO_TRACE) += iotrace.o
obj-y += memsize.o
obj-y += stdio.o
-obj-$(CONFIG_CMD_ADTIMG) += image-android-dt.o
-
ifdef CONFIG_CMD_EEPROM_LAYOUT
obj-y += eeprom/eeprom_field.o eeprom/eeprom_layout.o
endif
board_init_f_init_stack_protection();
}
-#if CONFIG_IS_ENABLED(BOOTSTAGE)
+#if CONFIG_IS_ENABLED(SHOW_BOOT_PROGRESS)
/*
* Board-specific Platform code can reimplement show_boot_progress () if needed
*/
+++ /dev/null
-/*
- * Copyright (c) Orbacom Systems, Inc <www.orbacom.com>
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are freely
- * permitted provided that the above copyright notice and this
- * paragraph and the following disclaimer are duplicated in all
- * such forms.
- *
- * This software is provided "AS IS" and without any express or
- * implied warranties, including, without limitation, the implied
- * warranties of merchantability and fitness for a particular
- * purpose.
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <image.h>
-#include <net.h>
-
-#include <lynxkdi.h>
-
-#error "Lynx KDI support not implemented for configured CPU"
/* Define board data structure */
static struct bd_info bdata __attribute__ ((section(".data")));
-#if CONFIG_IS_ENABLED(BOOTSTAGE)
+#if CONFIG_IS_ENABLED(SHOW_BOOT_PROGRESS)
/*
* Board-specific Platform code can reimplement show_boot_progress () if needed
*/
* 0 to not start u-boot
* positive if u-boot should start
*/
-#ifdef CONFIG_SPL_OS_BOOT
+#if CONFIG_IS_ENABLED(OS_BOOT)
__weak int spl_start_uboot(void)
{
puts(SPL_TPL_PROMPT
{
}
+#if CONFIG_IS_ENABLED(OPTEE_IMAGE)
+__weak void __noreturn jump_to_image_optee(struct spl_image_info *spl_image)
+{
+ spl_optee_entry(NULL, NULL, spl_image->fdt_addr,
+ (void *)spl_image->entry_point);
+}
+#endif
+
__weak void spl_board_prepare_for_boot(void)
{
/* Nothing to do! */
panic("** no mkimage signature but raw image not supported");
#endif
-#ifdef CONFIG_SPL_OS_BOOT
+#if CONFIG_IS_ENABLED(OS_BOOT)
ulong start, end;
if (!bootz_setup((ulong)header, &start, &end)) {
case IH_OS_TEE:
debug("Jumping to U-Boot via OP-TEE\n");
spl_board_prepare_for_optee(spl_image.fdt_addr);
- spl_optee_entry(NULL, NULL, spl_image.fdt_addr,
- (void *)spl_image.entry_point);
+ jump_to_image_optee(&spl_image);
break;
#endif
#if CONFIG_IS_ENABLED(OPENSBI)
spl_invoke_opensbi(&spl_image);
break;
#endif
-#ifdef CONFIG_SPL_OS_BOOT
+#if CONFIG_IS_ENABLED(OS_BOOT)
case IH_OS_LINUX:
debug("Jumping to Linux\n");
#if defined(CONFIG_SYS_SPL_ARGS_ADDR)
return err < 0;
}
-#ifdef CONFIG_SPL_OS_BOOT
+#if CONFIG_IS_ENABLED(OS_BOOT)
int spl_load_image_ext_os(struct spl_image_info *spl_image,
struct blk_desc *block_dev, int partition)
{
return (err <= 0);
}
-#ifdef CONFIG_SPL_OS_BOOT
+#if CONFIG_IS_ENABLED(OS_BOOT)
int spl_load_image_fat_os(struct spl_image_info *spl_image,
struct blk_desc *block_dev, int partition)
{
return buf;
}
+__weak void *board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len)
+{
+ return spl_get_fit_load_buffer(sectors * bl_len);
+}
+
/*
* Weak default function to allow customizing SPL fit loading for load-only
* use cases by allowing to skip the parsing/processing of the FIT contents
return false;
}
+/*
+ * Weak default function to allow fixes after fit header
+ * is loaded.
+ */
+__weak void *spl_load_simple_fit_fix_load(const void *fit)
+{
+ return (void *)fit;
+}
+
static void warn_deprecated(const char *msg)
{
printf("DEPRECATED: %s\n", msg);
* For FIT with external data, data is not loaded in this step.
*/
sectors = get_aligned_image_size(info, size, 0);
- buf = spl_get_fit_load_buffer(sectors * info->bl_len);
+ buf = board_spl_fit_buffer_addr(size, sectors, info->bl_len);
count = info->read(info, sector, sectors, buf);
ctx->fit = buf;
if (spl_load_simple_fit_skip_processing())
return 0;
+ ctx.fit = spl_load_simple_fit_fix_load(ctx.fit);
+
ret = spl_simple_fit_parse(&ctx);
if (ret < 0)
return ret;
}
#endif
-#ifdef CONFIG_SPL_OS_BOOT
+#if CONFIG_IS_ENABLED(OS_BOOT)
static int mmc_load_image_raw_os(struct spl_image_info *spl_image,
struct mmc *mmc)
{
header = spl_get_load_buffer(0, sizeof(*header));
-#ifdef CONFIG_SPL_OS_BOOT
+#if CONFIG_IS_ENABLED(OS_BOOT)
if (!spl_start_uboot()) {
/*
* load parameter image
*/
spl_image->flags |= SPL_COPY_PAYLOAD_ONLY;
-#ifdef CONFIG_SPL_OS_BOOT
+#if CONFIG_IS_ENABLED(OS_BOOT)
if (!spl_start_uboot()) {
/*
* Load Linux from its location in NOR flash to its defined
return -ENODEV;
}
-#ifdef CONFIG_SPL_OS_BOOT
+#if CONFIG_IS_ENABLED(OS_BOOT)
if (spl_start_uboot() ||
spl_load_image_fat_os(spl_image, stor_dev,
CONFIG_SYS_SATA_FAT_BOOT_PARTITION))
#include <asm/global_data.h>
#include <dm/ofnode.h>
-#ifdef CONFIG_SPL_OS_BOOT
+#if CONFIG_IS_ENABLED(OS_BOOT)
/*
* Load the kernel, check for a valid header we can parse, and if found load
* the kernel and then device tree.
payload_offs);
}
-#ifdef CONFIG_SPL_OS_BOOT
+#if CONFIG_IS_ENABLED(OS_BOOT)
if (spl_start_uboot() || spi_load_image_os(spl_image, flash, header))
#endif
{
info.leb_start = CONFIG_SPL_UBI_LEB_START;
info.peb_count = CONFIG_SPL_UBI_MAX_PEBS - info.peb_offset;
-#ifdef CONFIG_SPL_OS_BOOT
+#if CONFIG_IS_ENABLED(OS_BOOT)
if (!spl_start_uboot()) {
volumes[0].vol_id = CONFIG_SPL_UBI_LOAD_KERNEL_ID;
volumes[0].load_addr = (void *)CONFIG_SYS_LOAD_ADDR;
debug("boot mode - FAT\n");
-#ifdef CONFIG_SPL_OS_BOOT
+#if CONFIG_IS_ENABLED(OS_BOOT)
if (spl_start_uboot() ||
spl_load_image_fat_os(spl_image, stor_dev, partition))
#endif
static int spl_xip(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev)
{
-#ifdef CONFIG_SPL_OS_BOOT
+#if CONFIG_IS_ENABLED(OS_BOOT)
if (!spl_start_uboot()) {
spl_image->arg = (void *)CONFIG_SYS_FDT_BASE;
spl_image->name = "Linux";
CONFIG_NIOS2=y
CONFIG_SYS_CONFIG_NAME="10m50_devboard"
+CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="10m50_devboard"
CONFIG_SYS_LOAD_ADDR=0xcc000000
CONFIG_NIOS2=y
CONFIG_SYS_CONFIG_NAME="3c120_devboard"
+CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="3c120_devboard"
CONFIG_SYS_LOAD_ADDR=0xd4000000
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x0
+CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_SECT_SIZE=0x2000
-CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_DEFAULT_DEVICE_TREE="M5208EVBE"
CONFIG_TARGET_M5208EVBE=y
CONFIG_SYS_LOAD_ADDR=0x40010000
CONFIG_DM_ETH=y
CONFIG_MCFFEC=y
CONFIG_MII=y
+CONFIG_MCFUART=y
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFFC00000
+CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x2000
-CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_DEFAULT_DEVICE_TREE="M5235EVB_Flash32"
CONFIG_TARGET_M5235EVB=y
CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_DM_ETH=y
CONFIG_MCFFEC=y
CONFIG_MII=y
+CONFIG_MCFUART=y
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFFE00000
+CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x2000
-CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_DEFAULT_DEVICE_TREE="M5235EVB"
CONFIG_TARGET_M5235EVB=y
CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_DM_ETH=y
CONFIG_MCFFEC=y
CONFIG_MII=y
+CONFIG_MCFUART=y
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFFE00000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x2000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="M5249EVB"
CONFIG_TARGET_M5249EVB=y
CONFIG_SYS_LOAD_ADDR=0x200000
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_MCFUART=y
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
+CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_SECT_SIZE=0x1000
-CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_DEFAULT_DEVICE_TREE="M5253DEMO"
CONFIG_TARGET_M5253DEMO=y
CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_SYS_I2C_SLAVE=0x7F
CONFIG_SYS_I2C_SPEED=80000
CONFIG_MTD_NOR_FLASH=y
+CONFIG_MCFUART=y
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFFE00000
+CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x2000
-CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_DEFAULT_DEVICE_TREE="M5272C3"
CONFIG_TARGET_M5272C3=y
CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_DM_ETH=y
CONFIG_MCFFEC=y
CONFIG_MII=y
+CONFIG_MCFUART=y
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFFE00000
+CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x2000
-CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_DEFAULT_DEVICE_TREE="M5275EVB"
CONFIG_TARGET_M5275EVB=y
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_DM_ETH=y
CONFIG_MCFFEC=y
CONFIG_MII=y
+CONFIG_MCFUART=y
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFFE00000
+CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x2000
-CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_DEFAULT_DEVICE_TREE="M5282EVB"
CONFIG_TARGET_M5282EVB=y
CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_DM_ETH=y
CONFIG_MCFFEC=y
CONFIG_MII=y
+CONFIG_MCFUART=y
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x0
+CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_SECT_SIZE=0x8000
-CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_DEFAULT_DEVICE_TREE="M53017EVB"
CONFIG_TARGET_M53017EVB=y
CONFIG_SYS_LOAD_ADDR=0x40010000
CONFIG_DM_ETH=y
CONFIG_MCFFEC=y
CONFIG_MII=y
+CONFIG_MCFUART=y
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x0
+CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x2000
-CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_DEFAULT_DEVICE_TREE="M5329AFEE"
CONFIG_TARGET_M5329EVB=y
CONFIG_SYS_LOAD_ADDR=0x40010000
CONFIG_DM_ETH=y
CONFIG_MCFFEC=y
CONFIG_MII=y
+CONFIG_MCFUART=y
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x0
+CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x2000
-CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_DEFAULT_DEVICE_TREE="M5329BFEE"
CONFIG_TARGET_M5329EVB=y
CONFIG_SYS_LOAD_ADDR=0x40010000
CONFIG_DM_ETH=y
CONFIG_MCFFEC=y
CONFIG_MII=y
+CONFIG_MCFUART=y
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x0
+CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x2000
-CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_DEFAULT_DEVICE_TREE="M5373EVB"
CONFIG_TARGET_M5373EVB=y
CONFIG_SYS_LOAD_ADDR=0x40010000
CONFIG_DM_ETH=y
CONFIG_MCFFEC=y
CONFIG_MII=y
+CONFIG_MCFUART=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DEFAULT_DEVICE_TREE="mpc8379erdb"
CONFIG_SYS_CLK_FREQ=66666667
CONFIG_MPC83xx=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFF80000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds_36b"
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFF80000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds"
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFF80000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds"
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11001000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x100000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b"
CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_SPL_SERIAL=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_BLOCK_SIZE=0x4000
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b"
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11001000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x0
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b"
CONFIG_SPL_TEXT_BASE=0xD0001000
CONFIG_SPL_MMC=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11001000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b"
CONFIG_SPL_TEXT_BASE=0xD0001000
CONFIG_SPL_SERIAL=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11001000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x100000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa"
CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_SPL_SERIAL=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_BLOCK_SIZE=0x4000
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa"
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11001000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x0
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa"
CONFIG_SPL_TEXT_BASE=0xD0001000
CONFIG_SPL_MMC=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11001000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa"
CONFIG_SPL_TEXT_BASE=0xD0001000
CONFIG_SPL_SERIAL=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11001000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x100000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b"
CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_SPL_SERIAL=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b"
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11001000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x0
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b"
CONFIG_SPL_TEXT_BASE=0xD0001000
CONFIG_SPL_MMC=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11001000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b"
CONFIG_SPL_TEXT_BASE=0xD0001000
CONFIG_SPL_SERIAL=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11001000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x100000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb"
CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_SPL_SERIAL=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb"
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11001000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x0
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb"
CONFIG_SPL_TEXT_BASE=0xD0001000
CONFIG_SPL_MMC=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11001000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb"
CONFIG_SPL_TEXT_BASE=0xD0001000
CONFIG_SPL_SERIAL=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11001000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x100000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b"
CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_SPL_SERIAL=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11001000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x0
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b"
CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_SPL_MMC=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11001000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b"
CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_SPL_SERIAL=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b"
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11001000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x100000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc"
CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_SPL_SERIAL=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11001000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x0
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc"
CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_SPL_MMC=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11001000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc"
CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_SPL_SERIAL=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc"
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11001000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x100000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd"
CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_SPL_SERIAL=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11001000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x0
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd"
CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_SPL_MMC=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11001000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd"
CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_SPL_SERIAL=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd"
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11001000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x100000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b"
CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_SPL_SERIAL=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11001000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x0
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b"
CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_SPL_MMC=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11001000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b"
CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_SPL_SERIAL=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b"
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11001000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x100000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc"
CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_SPL_SERIAL=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11001000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x0
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc"
CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_SPL_MMC=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11001000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc"
CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_SPL_SERIAL=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc"
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFF40000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xE0000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
CONFIG_MPC85xx=y
CONFIG_TARGET_P2041RDB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x100000
CONFIG_MII=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFF40000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xCF400
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
CONFIG_MPC85xx=y
CONFIG_TARGET_P2041RDB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0xD2000
CONFIG_MII=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFF40000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
CONFIG_MPC85xx=y
CONFIG_TARGET_P2041RDB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x110000
CONFIG_MII=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
CONFIG_MPC85xx=y
CONFIG_TARGET_P2041RDB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000
CONFIG_MII=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFF40000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xE0000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p3041ds"
CONFIG_MPC85xx=y
CONFIG_TARGET_P3041DS=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x100000
CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFF40000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xCF400
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p3041ds"
CONFIG_MPC85xx=y
CONFIG_TARGET_P3041DS=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0xD2000
CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFF40000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p3041ds"
CONFIG_MPC85xx=y
CONFIG_TARGET_P3041DS=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x110000
CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p3041ds"
CONFIG_MPC85xx=y
CONFIG_TARGET_P3041DS=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000
CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFF40000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xCF400
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p4080ds"
CONFIG_MPC85xx=y
CONFIG_TARGET_P4080DS=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0xD2000
CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFF40000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p4080ds"
CONFIG_MPC85xx=y
CONFIG_TARGET_P4080DS=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x110000
CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p4080ds"
CONFIG_MPC85xx=y
CONFIG_TARGET_P4080DS=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000
CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFF40000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xE0000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p5040ds"
CONFIG_MPC85xx=y
CONFIG_TARGET_P5040DS=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x100000
CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFF40000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xCF400
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p5040ds"
CONFIG_MPC85xx=y
CONFIG_TARGET_P5040DS=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0xD2000
CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFF40000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p5040ds"
CONFIG_MPC85xx=y
CONFIG_TARGET_P5040DS=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x110000
CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p5040ds"
CONFIG_MPC85xx=y
CONFIG_TARGET_P5040DS=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000
CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_SNTP=y
+CONFIG_DOS_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_KIRKWOOD_SPI=y
+CONFIG_MD5=y
CONFIG_CMD_PING=y
CONFIG_CMD_SNTP=y
# CONFIG_CMD_LED is not set
+CONFIG_DOS_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_KIRKWOOD_SPI=y
+CONFIG_MD5=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x30001000
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
-CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DEFAULT_DEVICE_TREE="t1024rdb"
CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_SERIAL=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_FMAN_ENET=y
CONFIG_MII=y
CONFIG_PCIE_FSL=y
+CONFIG_SYS_QE_FW_ADDR=0x200000
CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x30001000
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
-CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DEFAULT_DEVICE_TREE="t1024rdb"
CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_MMC=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x104000
CONFIG_MII=y
CONFIG_PCIE_FSL=y
+CONFIG_SYS_QE_FW_ADDR=0x124000
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x30001000
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DEFAULT_DEVICE_TREE="t1024rdb"
CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_SERIAL=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x110000
CONFIG_MII=y
CONFIG_PCIE_FSL=y
+CONFIG_SYS_QE_FW_ADDR=0x130000
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DEFAULT_DEVICE_TREE="t1024rdb"
CONFIG_MPC85xx=y
CONFIG_TARGET_T1024RDB=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000
CONFIG_MII=y
CONFIG_PCIE_FSL=y
+CONFIG_SYS_QE_FW_ADDR=0xEFE00000
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x280000
CONFIG_MII=y
CONFIG_PCIE_FSL=y
+CONFIG_SYS_QE_FW_ADDR=0x380000
CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x10400
CONFIG_MII=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x110000
CONFIG_MII=y
CONFIG_PCIE_FSL=y
+CONFIG_SYS_QE_FW_ADDR=0x130000
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000
CONFIG_MII=y
CONFIG_PCIE_FSL=y
+CONFIG_SYS_QE_FW_ADDR=0xEFF10000
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x160000
CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x104000
CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000
CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x110000
CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0xFFE00000
CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000
CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x180000
CONFIG_MII=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x104000
CONFIG_MII=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x110000
CONFIG_MII=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x180000
CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x104000
CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x110000
CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000
CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x104000
CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000
CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="exynos78x0-common"
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_ARCH_EXYNOS=y
+CONFIG_SYS_TEXT_BASE=0x40001000
+CONFIG_ARCH_EXYNOS7=y
+CONFIG_TARGET_A3Y17LTE=y
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_DEFAULT_DEVICE_TREE="exynos78x0-axy17lte"
+CONFIG_SYS_LOAD_ADDR=0x40001000
+CONFIG_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_DM_I2C_GPIO=y
+CONFIG_PINCTRL_EXYNOS78x0=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="exynos78x0-common"
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_ARCH_EXYNOS=y
+CONFIG_SYS_TEXT_BASE=0x40001000
+CONFIG_ARCH_EXYNOS7=y
+CONFIG_TARGET_A5Y17LTE=y
+CONFIG_NR_DRAM_BANKS=12
+CONFIG_DEFAULT_DEVICE_TREE="exynos78x0-axy17lte"
+CONFIG_SYS_LOAD_ADDR=0x40001000
+CONFIG_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_DM_I2C_GPIO=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="exynos78x0-common"
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_ARCH_EXYNOS=y
+CONFIG_SYS_TEXT_BASE=0x40001000
+CONFIG_ARCH_EXYNOS7=y
+CONFIG_TARGET_A7Y17LTE=y
+CONFIG_NR_DRAM_BANKS=12
+CONFIG_DEFAULT_DEVICE_TREE="exynos78x0-axy17lte"
+CONFIG_SYS_LOAD_ADDR=0x40001000
+CONFIG_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_DM_I2C_GPIO=y
CONFIG_NDS32=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_TEXT_BASE=0x4A000000
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x140000
CONFIG_ENV_SECT_SIZE=0x1000
-CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DEFAULT_DEVICE_TREE="ae3xx"
CONFIG_TARGET_ADP_AE3XX=y
CONFIG_SYS_LOAD_ADDR=0x300000
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NDS32=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_TEXT_BASE=0x11000000
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DEFAULT_DEVICE_TREE="ag101p"
CONFIG_TARGET_ADP_AG101P=y
CONFIG_SYS_LOAD_ADDR=0x300000
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0x80140000
CONFIG_RISCV=y
CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SECT_SIZE=0x1000
-CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
CONFIG_TARGET_AX25_AE350=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_RISCV=y
CONFIG_SYS_TEXT_BASE=0x01200000
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SECT_SIZE=0x1000
-CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
CONFIG_SPL=y
CONFIG_RISCV=y
CONFIG_SYS_TEXT_BASE=0x01200000
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SECT_SIZE=0x1000
-CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
CONFIG_SPL_TEXT_BASE=0x80000000
CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
CONFIG_RISCV=y
CONFIG_SYS_TEXT_BASE=0x80000000
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SECT_SIZE=0x1000
-CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
CONFIG_TARGET_AX25_AE350=y
CONFIG_XIP=y
CONFIG_RISCV=y
CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SECT_SIZE=0x1000
-CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
CONFIG_TARGET_AX25_AE350=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV=y
CONFIG_SYS_TEXT_BASE=0x01200000
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SECT_SIZE=0x1000
-CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
CONFIG_SPL=y
CONFIG_RISCV=y
CONFIG_SYS_TEXT_BASE=0x01200000
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SECT_SIZE=0x1000
-CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
CONFIG_SPL_TEXT_BASE=0x80000000
CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
CONFIG_RISCV=y
CONFIG_SYS_TEXT_BASE=0x80000000
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SECT_SIZE=0x1000
-CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
CONFIG_TARGET_AX25_AE350=y
CONFIG_ARCH_RV64I=y
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_TEXT_BASE=0x50000000
+CONFIG_SYS_MALLOC_LEN=0x100000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r8a7794-alt-u-boot"
CONFIG_SPL_TEXT_BASE=0xe6300000
CONFIG_USB_ETHER=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_AM335X_LCD=y
+CONFIG_BMP_16BPP=y
CONFIG_SPL_WDT=y
# CONFIG_SPL_USE_TINY_PRINTF is not set
CONFIG_SPL_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x18000
CONFIG_DEFAULT_DEVICE_TREE="am335x-base0033"
CONFIG_AM33XX=y
CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_FDT_FIXUP_PARTITIONS=y
-# CONFIG_GENERATE_SMBIOS_TABLE is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80100000
-CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="am3517-evm"
CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_ENV_SIZE=0x10000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_ENV_SIZE=0x10000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_ISW_ENTRY_ADDR=0x403018e0
-CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_ENV_SIZE=0x10000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_SECURE_DEVICE=y
-CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_ISW_ENTRY_ADDR=0x40306d50
-CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_K3=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_AM642=y
CONFIG_K3_ATF_LOAD_ADDR=0x701c0000
CONFIG_TARGET_AM642_A53_EVM=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x680000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-am642-evm"
CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_ARM=y
CONFIG_ARCH_K3=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x80000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x80000
CONFIG_SOC_K3_AM642=y
CONFIG_TARGET_AM642_R5_EVM=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x680000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-am642-r5-evm"
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_K3=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_AM6=y
CONFIG_TARGET_AM654_A53_EVM=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x680000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-am654-base-board"
CONFIG_ARM=y
CONFIG_ARCH_K3=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x55000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x55000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_AM6=y
CONFIG_K3_EARLY_CONS=y
CONFIG_TARGET_AM654_R5_EVM=y
CONFIG_ENV_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-am654-r5-base-board"
CONFIG_ARM=y
CONFIG_ARCH_K3=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x55000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x55000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_AM6=y
CONFIG_K3_EARLY_CONS=y
CONFIG_TARGET_AM654_R5_EVM=y
CONFIG_ENV_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="k3-am654-r5-base-board"
CONFIG_SPL_TEXT_BASE=0x41c00000
CONFIG_ARM=y
CONFIG_ARCH_K3=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x55000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x55000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_AM6=y
CONFIG_K3_EARLY_CONS=y
CONFIG_TARGET_AM654_R5_EVM=y
CONFIG_ENV_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="k3-am654-r5-base-board"
CONFIG_SPL_TEXT_BASE=0x41c00000
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_K3=y
CONFIG_TI_SECURE_DEVICE=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_AM6=y
CONFIG_TARGET_AM654_A53_EVM=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x680000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-am654-base-board"
CONFIG_ARM=y
CONFIG_ARCH_K3=y
CONFIG_TI_SECURE_DEVICE=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x55000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x55000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_AM6=y
CONFIG_K3_EARLY_CONS=y
CONFIG_TARGET_AM654_R5_EVM=y
CONFIG_ENV_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-am654-r5-base-board"
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFFC00000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_SECT_SIZE=0x1000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="amcore"
CONFIG_TARGET_AMCORE=y
CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_MCFUART=y
CONFIG_MIPS=y
CONFIG_SYS_TEXT_BASE=0x9F000000
+CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SYS_MEMTEST_START=0x80100000
CONFIG_SYS_MEMTEST_END=0x83f00000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x40000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_DEFAULT_DEVICE_TREE="ap121"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xb8020000
CONFIG_MIPS=y
CONFIG_SYS_TEXT_BASE=0x9F000000
+CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_SYS_MEMTEST_START=0x80100000
CONFIG_SYS_MEMTEST_END=0x83f00000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x40000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_DEFAULT_DEVICE_TREE="ap143"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xb8020000
CONFIG_MIPS=y
CONFIG_SYS_TEXT_BASE=0x9F000000
+CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_SYS_MEMTEST_START=0x80100000
CONFIG_SYS_MEMTEST_END=0x83f00000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x40000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_DEFAULT_DEVICE_TREE="ap152"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xb8020000
CONFIG_ARM=y
CONFIG_ARCH_IMX8=y
CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2800000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=3
CONFIG_SYS_MEMTEST_START=0x88000000
CONFIG_SYS_MEMTEST_END=0x89000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFDE00
-CONFIG_SYS_MALLOC_LEN=0x2800000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-apalis"
CONFIG_TARGET_APALIS_IMX8=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_LOG=y
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_CMD_CPU=y
# CONFIG_BOOTM_NETBSD is not set
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_IMX_LPI2C=y
CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_ARM=y
CONFIG_ARCH_IMX8=y
CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2800000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=3
CONFIG_SYS_MEMTEST_START=0x88000000
CONFIG_SYS_MEMTEST_END=0x89000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFDE00
-CONFIG_SYS_MALLOC_LEN=0x2800000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-apalis"
CONFIG_TARGET_APALIS_IMX8X=y
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFDE00
CONFIG_MX6Q=y
+CONFIG_MX6_DDRCAL=y
CONFIG_TARGET_APALIS_IMX6=y
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6-apalis"
CONFIG_SPL_TEXT_BASE=0x00908000
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_APPLE=y
+CONFIG_DEFAULT_DEVICE_TREE="t8103-j274"
+CONFIG_DEBUG_UART_BASE=0x235200000
+CONFIG_DEBUG_UART_CLOCK=240000
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x880000000
+CONFIG_USE_PREBOOT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_NET is not set
+# CONFIG_MMC is not set
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_VIDEO_SIMPLE=y
+# CONFIG_GENERATE_SMBIOS_TABLE is not set
# CONFIG_SYS_THUMB_BUILD is not set
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_TEXT_BASE=0xE80C0000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ARCH_RMOBILE_BOARD_STRING="Armadillo-800EVA Board"
CONFIG_R8A7740=y
CONFIG_TARGET_ARMADILLO_800EVA=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x43E00000
+CONFIG_SYS_MALLOC_LEN=0x5004000
CONFIG_ARCH_EXYNOS5=y
CONFIG_TARGET_ARNDALE=y
CONFIG_NR_DRAM_BANKS=8
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x86200
-CONFIG_SYS_MALLOC_LEN=0x5004000
CONFIG_DEFAULT_DEVICE_TREE="exynos5250-arndale"
CONFIG_SPL_TEXT_BASE=0x02023400
CONFIG_SPL=y
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_ENV_SIZE=0x8000
CONFIG_ENV_SECT_SIZE=0x8000
-CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_DEFAULT_DEVICE_TREE="astro_mcf5373l"
CONFIG_TARGET_ASTRO_MCF5373L=y
CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_MCFUART=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
-CONFIG_TARGET_AT91SAM9260EK=y
+CONFIG_SYS_MALLOC_LEN=0x2d000
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4200
CONFIG_ENV_OFFSET=0x4200
CONFIG_ENV_SECT_SIZE=0x210
-CONFIG_SYS_MALLOC_LEN=0x2d000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
-CONFIG_TARGET_AT91SAM9260EK=y
+CONFIG_SYS_MALLOC_LEN=0x2d000
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4200
CONFIG_ENV_OFFSET=0x4200
CONFIG_ENV_SECT_SIZE=0x210
-CONFIG_SYS_MALLOC_LEN=0x2d000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
-CONFIG_TARGET_AT91SAM9260EK=y
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
-CONFIG_TARGET_AT91SAM9261EK=y
+CONFIG_SYS_MALLOC_LEN=0x2d000
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_AT91SAM9261EK=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4200
CONFIG_ENV_OFFSET=0x4200
CONFIG_ENV_SECT_SIZE=0x210
-CONFIG_SYS_MALLOC_LEN=0x2d000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
-CONFIG_TARGET_AT91SAM9261EK=y
+CONFIG_SYS_MALLOC_LEN=0x2d000
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_AT91SAM9261EK=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4200
CONFIG_ENV_OFFSET=0x4200
CONFIG_ENV_SECT_SIZE=0x210
-CONFIG_SYS_MALLOC_LEN=0x2d000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
-CONFIG_TARGET_AT91SAM9261EK=y
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_AT91SAM9261EK=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21F00000
-CONFIG_TARGET_AT91SAM9263EK=y
+CONFIG_SYS_MALLOC_LEN=0x2d000
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_AT91SAM9263EK=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4200
CONFIG_ENV_OFFSET=0x4200
CONFIG_ENV_SECT_SIZE=0x210
-CONFIG_SYS_MALLOC_LEN=0x2d000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21F00000
-CONFIG_TARGET_AT91SAM9263EK=y
+CONFIG_SYS_MALLOC_LEN=0x2d000
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_AT91SAM9263EK=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4200
CONFIG_ENV_OFFSET=0x4200
CONFIG_ENV_SECT_SIZE=0x210
-CONFIG_SYS_MALLOC_LEN=0x2d000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21F00000
-CONFIG_TARGET_AT91SAM9263EK=y
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_AT91SAM9263EK=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x0000000
-CONFIG_TARGET_AT91SAM9263EK=y
+CONFIG_SYS_MALLOC_LEN=0x50000
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_AT91SAM9263EK=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x50000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21F00000
-CONFIG_TARGET_AT91SAM9263EK=y
+CONFIG_SYS_MALLOC_LEN=0x50000
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_AT91SAM9263EK=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x50000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
-CONFIG_TARGET_AT91SAM9261EK=y
+CONFIG_SYS_MALLOC_LEN=0x2d000
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_AT91SAM9261EK=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4200
CONFIG_ENV_OFFSET=0x4200
CONFIG_ENV_SECT_SIZE=0x210
-CONFIG_SYS_MALLOC_LEN=0x2d000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
-CONFIG_TARGET_AT91SAM9261EK=y
+CONFIG_SYS_MALLOC_LEN=0x2d000
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_AT91SAM9261EK=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4200
CONFIG_ENV_OFFSET=0x4200
CONFIG_ENV_SECT_SIZE=0x210
-CONFIG_SYS_MALLOC_LEN=0x2d000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
-CONFIG_TARGET_AT91SAM9261EK=y
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_AT91SAM9261EK=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
-CONFIG_TARGET_AT91SAM9260EK=y
+CONFIG_SYS_MALLOC_LEN=0x23000
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x2000
-CONFIG_SYS_MALLOC_LEN=0x23000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20ek_2mmc"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
-CONFIG_TARGET_AT91SAM9260EK=y
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20ek_2mmc"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
-CONFIG_TARGET_AT91SAM9260EK=y
+CONFIG_SYS_MALLOC_LEN=0x2d000
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4200
CONFIG_ENV_OFFSET=0x4200
CONFIG_ENV_SECT_SIZE=0x210
-CONFIG_SYS_MALLOC_LEN=0x2d000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
-CONFIG_TARGET_AT91SAM9260EK=y
+CONFIG_SYS_MALLOC_LEN=0x2d000
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4200
CONFIG_ENV_OFFSET=0x4200
CONFIG_ENV_SECT_SIZE=0x210
-CONFIG_SYS_MALLOC_LEN=0x2d000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
-CONFIG_TARGET_AT91SAM9260EK=y
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x73f00000
-CONFIG_TARGET_AT91SAM9M10G45EK=y
+CONFIG_SYS_MALLOC_LEN=0x2c000
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_AT91SAM9M10G45EK=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4000
-CONFIG_SYS_MALLOC_LEN=0x2c000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9m10g45ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x73f00000
-CONFIG_TARGET_AT91SAM9M10G45EK=y
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_AT91SAM9M10G45EK=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9m10g45ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
-CONFIG_TARGET_AT91SAM9N12EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_AT91SAM9N12EK=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4000
CONFIG_DM_GPIO=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
-CONFIG_TARGET_AT91SAM9N12EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_AT91SAM9N12EK=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9n12ek"
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
-CONFIG_TARGET_AT91SAM9N12EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_AT91SAM9N12EK=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x3000
CONFIG_ENV_OFFSET=0x5000
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21F00000
-CONFIG_TARGET_AT91SAM9RLEK=y
+CONFIG_SYS_MALLOC_LEN=0x2d000
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_AT91SAM9RLEK=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4200
CONFIG_ENV_OFFSET=0x4200
CONFIG_ENV_SECT_SIZE=0x210
-CONFIG_SYS_MALLOC_LEN=0x2d000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9rlek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21F00000
-CONFIG_TARGET_AT91SAM9RLEK=y
+CONFIG_SYS_MALLOC_LEN=0x2c000
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_AT91SAM9RLEK=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4000
-CONFIG_SYS_MALLOC_LEN=0x2c000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9rlek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21F00000
-CONFIG_TARGET_AT91SAM9RLEK=y
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_AT91SAM9RLEK=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9rlek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
-CONFIG_TARGET_AT91SAM9X5EK=y
+CONFIG_SYS_MALLOC_LEN=0x81000
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_AT91SAM9X5EK=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4200
CONFIG_ENV_OFFSET=0x4200
CONFIG_ENV_SECT_SIZE=0x210
-CONFIG_SYS_MALLOC_LEN=0x81000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
-CONFIG_TARGET_AT91SAM9X5EK=y
+CONFIG_SYS_MALLOC_LEN=0x81000
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_AT91SAM9X5EK=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4000
-CONFIG_SYS_MALLOC_LEN=0x81000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
-CONFIG_TARGET_AT91SAM9X5EK=y
+CONFIG_SYS_MALLOC_LEN=0x81000
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_AT91SAM9X5EK=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_MALLOC_LEN=0x81000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
-CONFIG_TARGET_AT91SAM9X5EK=y
+CONFIG_SYS_MALLOC_LEN=0x81000
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_AT91SAM9X5EK=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x3000
CONFIG_ENV_OFFSET=0x5000
CONFIG_ENV_SECT_SIZE=0x1000
-CONFIG_SYS_MALLOC_LEN=0x81000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
-CONFIG_TARGET_AT91SAM9260EK=y
+CONFIG_SYS_MALLOC_LEN=0x2d000
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4200
CONFIG_ENV_OFFSET=0x4200
CONFIG_ENV_SECT_SIZE=0x210
-CONFIG_SYS_MALLOC_LEN=0x2d000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
-CONFIG_TARGET_AT91SAM9260EK=y
+CONFIG_SYS_MALLOC_LEN=0x2d000
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4200
CONFIG_ENV_OFFSET=0x4200
CONFIG_ENV_SECT_SIZE=0x210
-CONFIG_SYS_MALLOC_LEN=0x2d000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
-CONFIG_TARGET_AT91SAM9260EK=y
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_ARM=y
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_SYS_MALLOC_LEN=0x4008000
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_MEMTEST_END=0x00001000
-CONFIG_SYS_MALLOC_LEN=0x4008000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0"
CONFIG_SPL=y
CONFIG_ARCH_AT91=y
CONFIG_SPL_LDSCRIPT="arch/arm/cpu/u-boot-spl.lds"
CONFIG_SYS_TEXT_BASE=0x21000000
+CONFIG_SYS_MALLOC_LEN=0x460000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_TAURUS=y
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0x100000
-CONFIG_SYS_MALLOC_LEN=0x460000
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20-taurus"
CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000
CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
+CONFIG_MACB=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_BCMSTB=y
CONFIG_SYS_TEXT_BASE=0x10100000
+CONFIG_SYS_MALLOC_LEN=0x2800000
CONFIG_TARGET_BCM7260=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x814800
-CONFIG_SYS_MALLOC_LEN=0x2800000
CONFIG_ENV_OFFSET_REDUND=0x824800
CONFIG_SYS_LOAD_ADDR=0x02000000
CONFIG_FIT=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_DOS_PARTITION=y
CONFIG_OF_BOARD=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_BCMSTB=y
CONFIG_SYS_TEXT_BASE=0x80100000
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_TARGET_BCM7445=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x1E0000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_ENV_OFFSET_REDUND=0x1F0000
CONFIG_SYS_LOAD_ADDR=0x02000000
CONFIG_FIT=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_DOS_PARTITION=y
CONFIG_OF_BOARD=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
# CONFIG_ARM64_SUPPORT_AARCH32 is not set
CONFIG_ARCH_BCM63158=y
CONFIG_SYS_TEXT_BASE=0x10000000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="bcm963158"
CONFIG_TARGET_BCM963158=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_BCM68360=y
CONFIG_SYS_TEXT_BASE=0x10000000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="bcm968360bg"
CONFIG_TARGET_BCM968360BG=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_BCM6858=y
CONFIG_SYS_TEXT_BASE=0x10000000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="bcm968580xref"
CONFIG_TARGET_BCM968580XREF=y
CONFIG_GIC_V3_ITS=y
CONFIG_TARGET_BCMNS3=y
CONFIG_SYS_TEXT_BASE=0xFF000000
+CONFIG_SYS_MALLOC_LEN=0xc00000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x80000
-CONFIG_SYS_MALLOC_LEN=0xc00000
CONFIG_DEFAULT_DEVICE_TREE="ns3-board"
CONFIG_SYS_LOAD_ADDR=0x80080000
CONFIG_FIT=y
CONFIG_DM=y
CONFIG_CLK=y
CONFIG_CLK_CCF=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_IPROC=y
CONFIG_ARM=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80110000
+CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFE000
-CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_DEFAULT_DEVICE_TREE="tegra30-beaver"
CONFIG_SPL_TEXT_BASE=0x80108000
CONFIG_TEGRA30=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_VF610=y
CONFIG_SYS_TEXT_BASE=0x3f401000
+CONFIG_SYS_MALLOC_LEN=0x402000
CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x80010000
CONFIG_SYS_MEMTEST_END=0x87c00000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x200000
-CONFIG_SYS_MALLOC_LEN=0x402000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="vf610-bk4r1"
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x40000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r8a7792-blanche-u-boot"
CONFIG_ARCH_RMOBILE_BOARD_STRING="Blanche"
CONFIG_MIPS=y
CONFIG_SYS_TEXT_BASE=0x9FC00000
+CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x90000000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_DEFAULT_DEVICE_TREE="img,boston"
CONFIG_TARGET_BOSTON=y
# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
CONFIG_MIPS=y
CONFIG_SYS_TEXT_BASE=0x9FC00000
+CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x90000000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_DEFAULT_DEVICE_TREE="img,boston"
CONFIG_TARGET_BOSTON=y
CONFIG_SYS_LITTLE_ENDIAN=y
CONFIG_MIPS=y
CONFIG_SYS_TEXT_BASE=0x9FC00000
+CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x90000000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_DEFAULT_DEVICE_TREE="img,boston"
CONFIG_TARGET_BOSTON=y
CONFIG_CPU_MIPS32_R6=y
CONFIG_MIPS=y
CONFIG_SYS_TEXT_BASE=0x9FC00000
+CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x90000000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_DEFAULT_DEVICE_TREE="img,boston"
CONFIG_TARGET_BOSTON=y
CONFIG_SYS_LITTLE_ENDIAN=y
CONFIG_MIPS=y
CONFIG_SYS_TEXT_BASE=0xFFFFFFFF9FC00000
+CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x90000000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_DEFAULT_DEVICE_TREE="img,boston"
CONFIG_TARGET_BOSTON=y
CONFIG_CPU_MIPS64_R2=y
CONFIG_MIPS=y
CONFIG_SYS_TEXT_BASE=0xFFFFFFFF9FC00000
+CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x90000000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_DEFAULT_DEVICE_TREE="img,boston"
CONFIG_TARGET_BOSTON=y
CONFIG_SYS_LITTLE_ENDIAN=y
CONFIG_MIPS=y
CONFIG_SYS_TEXT_BASE=0xFFFFFFFF9FC00000
+CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x90000000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_DEFAULT_DEVICE_TREE="img,boston"
CONFIG_TARGET_BOSTON=y
CONFIG_CPU_MIPS64_R6=y
CONFIG_MIPS=y
CONFIG_SYS_TEXT_BASE=0xFFFFFFFF9FC00000
+CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x90000000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_DEFAULT_DEVICE_TREE="img,boston"
CONFIG_TARGET_BOSTON=y
CONFIG_SYS_LITTLE_ENDIAN=y
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
+CONFIG_SYS_MALLOC_LEN=0x500000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x40000
-CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-brppt1-mmc"
CONFIG_AM33XX=y
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
+CONFIG_SYS_MALLOC_LEN=0x500000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x60000
-CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-brppt1-nand"
CONFIG_AM33XX=y
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
+CONFIG_SYS_MALLOC_LEN=0x500000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x20000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-brppt1-spi"
CONFIG_ARCH_MX6=y
CONFIG_SPL_LDSCRIPT="arch/arm/cpu/u-boot-spl.lds"
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_LEN=0xa00000
+CONFIG_SYS_MALLOC_F_LEN=0x1000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x1000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x20000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_MX6QDL=y
CONFIG_TARGET_BRPPT2=y
-CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-brppt2"
CONFIG_SPL_SERIAL=y
CONFIG_SYS_BOOTCOUNT_ADDR=0x020CC068
CONFIG_PHYLIB=y
CONFIG_PHY_FIXED=y
CONFIG_FEC_MXC=y
+CONFIG_MII=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
+CONFIG_SYS_MALLOC_LEN=0x500000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x20000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-brsmarc1"
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
+CONFIG_SYS_MALLOC_LEN=0x500000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x40000
-CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-brxre1"
CONFIG_AM33XX=y
CONFIG_ARM=y
CONFIG_ARCH_OWL=y
-CONFIG_ENV_SIZE=0x2000
CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="bubblegum_96"
CONFIG_MACH_S900=y
CONFIG_IDENT_STRING="\nBubblegum-96"
CONFIG_ARM=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80110000
+CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFE000
-CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_DEFAULT_DEVICE_TREE="tegra124-cei-tk1-som"
CONFIG_SPL_TEXT_BASE=0x80108000
CONFIG_TEGRA124=y
CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_IMX8=y
CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
-CONFIG_SYS_MALLOC_LEN=0x2400000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8qm-cgtqmx8"
CONFIG_TARGET_CONGA_QMX8=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
CONFIG_BOOTDELAY=3
CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SYS_MMCSD_FS_BOOT_PARTITION=0
CONFIG_CMD_CACHE=y
CONFIG_CMD_FAT=y
CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_MIPS=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_TEXT_BASE=0x80010000
+CONFIG_SYS_MALLOC_LEN=0x4000000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x8000
CONFIG_ENV_OFFSET=0x83800
-CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DEFAULT_DEVICE_TREE="ci20"
CONFIG_SPL_TEXT_BASE=0xf4000a00
CONFIG_SPL_MMC=y
CONFIG_BOOTARGS="console=ttyS4,115200 rw rootwait root=/dev/mmcblk0p1"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="ext4load mmc 0:1 0x88000000 /boot/uImage; bootm 0x88000000"
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_ARM=y
CONFIG_ARCH_MX7=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_OFFSET=0xC0000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb"
CONFIG_TARGET_CL_SOM_IMX7=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_POWER_LEGACY=y
CONFIG_DM_REGULATOR=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00800000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_CLEARFOG=y
CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
+CONFIG_E1000=y
CONFIG_MVPP2=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DEFAULT_DEVICE_TREE="imx6q-cm-fx6"
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_MMC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFFE00000
+CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x2000
-CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_DEFAULT_DEVICE_TREE="cobra5272"
CONFIG_TARGET_COBRA5272=y
CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_MCFFEC=y
CONFIG_MII=y
CONFIG_BAUDRATE=19200
+CONFIG_MCFUART=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xFFFFDE00
+CONFIG_MX6ULL=y
+CONFIG_TARGET_COLIBRI_IMX6ULL=y
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_COLIBRI_IMX6ULL_EMMC=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ull-colibri-emmc"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=1
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="setenv fdtfile imx6ull-colibri${variant}-${fdt_board}.dtb"
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SYS_PROMPT="Colibri iMX6ULL # "
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CRC32_VERIFY=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_SDP=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_BOOTCOUNT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_ISO_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_PART=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_IP_DEFRAG=y
+CONFIG_TFTP_BLOCKSIZE=16352
+CONFIG_TFTP_TSIZE=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_BOOTCOUNT_ENV=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_SERIAL=y
+CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Toradex"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
+CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_BMP_RLE8=y
+CONFIG_BMP_16BPP=y
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x88000000
CONFIG_ENV_OFFSET=0x380000
CONFIG_MX6ULL=y
CONFIG_TARGET_COLIBRI_IMX6ULL=y
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
+CONFIG_TARGET_COLIBRI_IMX6ULL_NAND=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ull-colibri"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
-CONFIG_NAND_MXS=y
CONFIG_NAND_MXS_DT=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_ARM=y
CONFIG_ARCH_IMX8=y
CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2800000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=3
CONFIG_SYS_MEMTEST_START=0x88000000
CONFIG_SYS_MEMTEST_END=0x89000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFDE00
-CONFIG_SYS_MALLOC_LEN=0x2800000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-colibri"
CONFIG_TARGET_COLIBRI_IMX8X=y
CONFIG_FIT=y
CONFIG_LOG=y
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_CMD_CPU=y
# CONFIG_BOOTM_NETBSD is not set
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_IMX_LPI2C=y
CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFDE00
CONFIG_MX6DL=y
+CONFIG_MX6_DDRCAL=y
CONFIG_TARGET_COLIBRI_IMX6=y
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6-colibri"
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_ARM=y
CONFIG_ARCH_MX7=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x8c000000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x380000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7-colibri-rawnand"
CONFIG_TARGET_COLIBRI_IMX7=y
CONFIG_ARM=y
CONFIG_ARCH_MX7=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x8c000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFDE00
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7-colibri-emmc"
CONFIG_TARGET_COLIBRI_IMX7=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_TARGET_COLIBRI_PXA270=y
CONFIG_SYS_TEXT_BASE=0x0
+CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_SYS_LOAD_ADDR=0xa0000000
CONFIG_USE_BOOTARGS=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_VF610=y
CONFIG_SYS_TEXT_BASE=0x3f401000
+CONFIG_SYS_MALLOC_LEN=0x0220000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x80010000
CONFIG_SYS_MEMTEST_END=0x87c00000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x180000
-CONFIG_SYS_MALLOC_LEN=0x0220000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="vf610-colibri"
CONFIG_TARGET_COLIBRI_VF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00800000
-CONFIG_SPL_GPIO=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_CONTROLCENTERDC=y
CONFIG_ENV_SIZE=0x10000
CONFIG_BOARD_LATE_INIT=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_I2C=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_GO is not set
# CONFIG_SYS_ARCH_TIMER is not set
CONFIG_TARGET_PRESIDIO_ASIC=y
CONFIG_SYS_TEXT_BASE=0x04000000
+CONFIG_SYS_MALLOC_LEN=0x820000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x820000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ca-presidio-engboard"
CONFIG_IDENT_STRING="Presidio-SoC"
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon=serial,0xf4329148 console=ttyS0,115200 root=/dev/ram0"
CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_SYS_PROMPT="G3#"
CONFIG_CMD_WDT=y
CONFIG_CMD_CACHE=y
# CONFIG_SYS_ARCH_TIMER is not set
CONFIG_TARGET_PRESIDIO_ASIC=y
CONFIG_SYS_TEXT_BASE=0x04000000
+CONFIG_SYS_MALLOC_LEN=0x820000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x820000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ca-presidio-engboard"
CONFIG_IDENT_STRING="Presidio-SoC"
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_SYS_PROMPT="G3#"
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
# CONFIG_SYS_ARCH_TIMER is not set
CONFIG_TARGET_PRESIDIO_ASIC=y
CONFIG_SYS_TEXT_BASE=0x04000000
+CONFIG_SYS_MALLOC_LEN=0x820000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x820000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ca-presidio-engboard"
CONFIG_IDENT_STRING="Presidio-SoC"
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon=serial,0xf4329148 console=ttyS0,115200 root=/dev/ram0"
CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_SYS_PROMPT="G3#"
CONFIG_CMD_MTD=y
CONFIG_CMD_WDT=y
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x72000000
+CONFIG_SYS_MALLOC_LEN=0x460000
+CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_TARGET_CORVUS=y
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0x100000
-CONFIG_SYS_MALLOC_LEN=0x460000
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g45-corvus"
CONFIG_SPL_TEXT_BASE=0x300000
CONFIG_SPL_SERIAL=y
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
-CONFIG_PHYLIB=y
+CONFIG_MACB=y
CONFIG_ATMEL_USART=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_DAVINCI=y
CONFIG_SYS_TEXT_BASE=0xc1080000
+CONFIG_SYS_MALLOC_LEN=0x110000
+CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_TARGET_DA850EVM=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x80000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x110000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="da850-evm"
CONFIG_SPL_TEXT_BASE=0x80000000
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_DAVINCI=y
CONFIG_SYS_TEXT_BASE=0x60000000
+CONFIG_SYS_MALLOC_LEN=0x110000
+CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_TARGET_DA850EVM=y
CONFIG_DA850_LOWLEVEL=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2800
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x110000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="da850-evm"
CONFIG_LTO=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_DAVINCI=y
CONFIG_SYS_TEXT_BASE=0xc1080000
+CONFIG_SYS_MALLOC_LEN=0x110000
+CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_TARGET_DA850EVM=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x0
-CONFIG_SYS_MALLOC_LEN=0x110000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="da850-evm"
CONFIG_SPL_TEXT_BASE=0x80000000
CONFIG_ARM=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80110000
+CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFE000
-CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_DEFAULT_DEVICE_TREE="tegra114-dalmore"
CONFIG_SPL_TEXT_BASE=0x80108000
CONFIG_TEGRA114=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00800000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_DB_88F6720=y
CONFIG_ENV_SIZE=0x10000
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00800000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_DB_88F6820_AMC=y
CONFIG_ENV_SIZE=0x10000
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00800000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_DB_88F6820_GP=y
CONFIG_ENV_SIZE=0x10000
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00800000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_DB_MV784MP_GP=y
CONFIG_ENV_SIZE=0x10000
CONFIG_ARM=y
CONFIG_ARCH_IMX8=y
CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2800000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x0
-CONFIG_SYS_MALLOC_LEN=0x2800000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8-deneb"
CONFIG_SPL_TEXT_BASE=0x100000
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_LPC32XX=y
CONFIG_SYS_TEXT_BASE=0x83F00000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xA0000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_TEXT_BASE=0x00000000
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80100000
-CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MALLOC_LEN=0x40000
+CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_TARGET_DEVKIT8000=y
CONFIG_SPL=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_F_LEN=0x1000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x1000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x10000000
CONFIG_SYS_MEMTEST_END=0x20000000
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_SYS_MALLOC_F_LEN=0x1000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x1000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x120000
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DEFAULT_DEVICE_TREE="imx6q-display5"
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_MMC=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_SYS_MALLOC_F_LEN=0x1000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x1000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x120000
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DEFAULT_DEVICE_TREE="imx6q-display5"
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_MMC=y
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SYS_MALLOC_F_LEN=0x18000
+CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_SECURE_DEVICE=y
-CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SYS_MALLOC_F_LEN=0x18000
+CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_ISW_ENTRY_ADDR=0x40306d50
-CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SYS_MALLOC_F_LEN=0x18000
+CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80100000
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
-CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
CONFIG_AM33XX=y
CONFIG_ARM=y
CONFIG_ARCH_SNAPDRAGON=y
CONFIG_SYS_TEXT_BASE=0x8f600000
+CONFIG_SYS_MALLOC_LEN=0x802000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x0
-CONFIG_SYS_MALLOC_LEN=0x802000
CONFIG_DEFAULT_DEVICE_TREE="dragonboard410c"
CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 410C"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ARM=y
CONFIG_ARCH_SNAPDRAGON=y
CONFIG_SYS_TEXT_BASE=0x80080000
+CONFIG_SYS_MALLOC_LEN=0x804000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x4000
-CONFIG_SYS_MALLOC_LEN=0x804000
CONFIG_DEFAULT_DEVICE_TREE="dragonboard820c"
CONFIG_TARGET_DRAGONBOARD820C=y
CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 820C"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SYS_PROMPT="dragonboard820c => "
-CONFIG_CMD_BOOTEFI_HELLO=y
CONFIG_CMD_MD5SUM=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_GPIO=y
CONFIG_STATIC_MACH_TYPE=y
CONFIG_MACH_TYPE=3036
CONFIG_SYS_TEXT_BASE=0x00800000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_DS414=y
CONFIG_DDR_32BIT=y
CONFIG_ARM_SMCCC=y
CONFIG_TARGET_DURIAN=y
CONFIG_SYS_TEXT_BASE=0x500000
+CONFIG_SYS_MALLOC_LEN=0x101000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x1000
-CONFIG_SYS_MALLOC_LEN=0x101000
CONFIG_DEFAULT_DEVICE_TREE="phytium-durian"
# CONFIG_PSCI_RESET is not set
CONFIG_AHCI=y
CONFIG_DM_ETH=y
CONFIG_MCFFEC=y
CONFIG_MII=y
+CONFIG_MCFUART=y
CONFIG_SPLASH_SCREEN=y
CONFIG_VIDEO_VCXK=y
CONFIG_DM_ETH=y
CONFIG_MCFFEC=y
CONFIG_MII=y
+CONFIG_MCFUART=y
CONFIG_SPLASH_SCREEN=y
CONFIG_VIDEO_VCXK=y
CONFIG_X86=y
CONFIG_SYS_TEXT_BASE=0x1101000
+CONFIG_SYS_MALLOC_LEN=0x8000000
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x300000
-CONFIG_SYS_MALLOC_LEN=0x8000000
CONFIG_DEFAULT_DEVICE_TREE="edison"
CONFIG_ENV_OFFSET_REDUND=0x600000
CONFIG_VENDOR_INTEL=y
CONFIG_ARCH_ORION5X=y
CONFIG_SPL_LDSCRIPT="arch/arm/mach-orion5x/u-boot-spl.lds"
CONFIG_SYS_TEXT_BASE=0x00800000
+CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x2000
-CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_SPL_TEXT_BASE=0xffff0000
CONFIG_TARGET_EDMINIV2=y
CONFIG_SPL_SERIAL=y
CONFIG_DEBUG_UART_BASE=0
CONFIG_DEBUG_UART_CLOCK=0
CONFIG_VENDOR_EFI=y
-CONFIG_TARGET_EFI_APP=y
+CONFIG_TARGET_EFI_APP32=y
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
-# CONFIG_DM_ETH is not set
# CONFIG_REGEX is not set
# CONFIG_GZIP is not set
CONFIG_EFI=y
-# CONFIG_EFI_LOADER is not set
--- /dev/null
+CONFIG_X86=y
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_ENV_SIZE=0x1000
+CONFIG_DEFAULT_DEVICE_TREE="efi-x86_app"
+CONFIG_DEBUG_UART_BASE=0
+CONFIG_DEBUG_UART_CLOCK=0
+CONFIG_VENDOR_EFI=y
+CONFIG_TARGET_EFI_APP64=y
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_SHOW_BOOT_PROGRESS=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_LAST_STAGE_INIT=y
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_BOOTM is not set
+CONFIG_CMD_PART=y
+# CONFIG_CMD_NET is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
+CONFIG_OF_EMBED=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+# CONFIG_REGEX is not set
+# CONFIG_GZIP is not set
+CONFIG_EFI=y
+CONFIG_EFI_APP_64BIT=y
CONFIG_CPU_ARCEM6=y
CONFIG_TARGET_EMSDP=y
CONFIG_SYS_TEXT_BASE=0x00000000
-CONFIG_ENV_SIZE=0x1000
CONFIG_SYS_MALLOC_LEN=0x10000
+CONFIG_ENV_SIZE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="emsdp"
CONFIG_SYS_CLK_FREQ=40000000
CONFIG_SYS_LOAD_ADDR=0x10000000
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x43E00000
-CONFIG_ARCH_EXYNOS7=y
+CONFIG_SYS_MALLOC_LEN=0x5004000
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ARCH_EXYNOS7=y
CONFIG_NR_DRAM_BANKS=8
CONFIG_ENV_SIZE=0x4000
-CONFIG_SYS_MALLOC_LEN=0x5004000
CONFIG_DEFAULT_DEVICE_TREE="exynos7420-espresso7420"
CONFIG_IDENT_STRING=" for ESPRESSO7420"
CONFIG_SYS_LOAD_ADDR=0x43e00000
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80100000
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x980000
-CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
CONFIG_AM33XX=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x27000000
-CONFIG_TARGET_ETHERNUT5=y
+CONFIG_SYS_MALLOC_LEN=0x121000
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_ETHERNUT5=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x21000
CONFIG_ENV_OFFSET=0x3DE000
CONFIG_ENV_SECT_SIZE=0x21000
-CONFIG_SYS_MALLOC_LEN=0x121000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ethernut5"
CONFIG_SYS_LOAD_ADDR=0x020000000
CONFIG_CMD_DHCP=y
CONFIG_CMD_RARP=y
CONFIG_CMD_MII=y
+# CONFIG_CMD_MDIO is not set
CONFIG_CMD_PING=y
CONFIG_CMD_CDP=y
CONFIG_CMD_SNTP=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_DATAFLASH=y
+CONFIG_MACB=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_RTC_PCF8563=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_MX6ULL=y
CONFIG_TARGET_O4_IMX6ULL_NANO=y
-CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DM_GPIO=y
CONFIG_EV_IMX280_NANO_X_MB=y
CONFIG_IMX_MODULE_FUSE=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_ASPEED=y
CONFIG_SYS_TEXT_BASE=0x0
-CONFIG_TARGET_EVB_AST2500=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_EVB_AST2500=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="ast2500-evb"
CONFIG_PRE_CON_BUF_ADDR=0x1e720000
CONFIG_SYS_LOAD_ADDR=0x83000000
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_ASPEED=y
CONFIG_SYS_TEXT_BASE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_ASPEED_AST2600=y
CONFIG_TARGET_EVB_AST2600=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="ast2600-evb"
CONFIG_SPL_SERIAL=y
CONFIG_SPL_SIZE_LIMIT=0x10000
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEFAULT_DEVICE_TREE="px30-evb"
CONFIG_SPL_TEXT_BASE=0x00000000
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00600000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rk3308-evb"
CONFIG_ROCKCHIP_RK3308=y
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEFAULT_DEVICE_TREE="px30-firefly"
CONFIG_SPL_TEXT_BASE=0x00000000
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x22900000
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_GARDENA_SMART_GATEWAY_AT91SAM=y
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x0
CONFIG_ENV_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g25-gardena-smart-gateway"
CONFIG_SPL_TEXT_BASE=0x300000
CONFIG_MIPS=y
CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0xA0000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DEFAULT_DEVICE_TREE="gardena-smart-gateway-mt7688"
CONFIG_SPL_SERIAL=y
CONFIG_SYS_BOOTCOUNT_ADDR=0xb000006c
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_SYS_MALLOC_F_LEN=0x600
CONFIG_SYS_MEMTEST_START=0x00001000
CONFIG_SYS_MEMTEST_END=0x07e00000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="gazerbeam"
CONFIG_IDENT_STRING=" gazerbeam 0.01"
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_LEN=0xa00000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
# CONFIG_GE_RTC is not set
CONFIG_MX6QDL=y
CONFIG_TARGET_GE_B1X5V2=y
-CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-b1x5v2"
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_SERIAL=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_MX6Q=y
CONFIG_TARGET_GE_BX50V3=y
-CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-bx50v3"
CONFIG_BOOTCOUNT_BOOTLIMIT=10
CONFIG_ARM=y
CONFIG_ARCH_IMX8=y
CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2800000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x0
-CONFIG_SYS_MALLOC_LEN=0x2800000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8-giedi"
CONFIG_SPL_TEXT_BASE=0x100000
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_TEXT_BASE=0x50000000
+CONFIG_SYS_MALLOC_LEN=0x100000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r8a7793-gose-u-boot"
CONFIG_SPL_TEXT_BASE=0xe6300000
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_TEXT_BASE=0x18000000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x80000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r7s72100-gr-peach-u-boot"
CONFIG_RZA1=y
CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x73f00000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_TARGET_GURNARD=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x80000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g45-gurnard"
CONFIG_SYS_LOAD_ADDR=0x23000000
CONFIG_FIT=y
# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_ATMEL_NAND_HWECC=y
-CONFIG_PHYLIB=y
+CONFIG_MACB=y
CONFIG_ATMEL_USART=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_CMD_EECONFIG=y
CONFIG_CMD_GSC=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-gw54xx"
CONFIG_SPL_I2C=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_POWER=y
-CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Ventana > "
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_WDT=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MXC_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_LAN75XX=y
+CONFIG_USB_ETHER_LAN78XX=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Gateworks"
# CONFIG_VIDEO_ANSI is not set
CONFIG_SYS_WHITE_ON_BLACK=y
# CONFIG_PANEL is not set
+CONFIG_I2C_EDID=y
CONFIG_VIDEO_IPUV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_WATCHDOG_TIMEOUT_MSECS=60000
+CONFIG_IMX_WATCHDOG=y
CONFIG_FDT_FIXUP_PARTITIONS=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_CMD_EECONFIG=y
CONFIG_CMD_GSC=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-gw54xx"
CONFIG_SPL_I2C=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_POWER=y
-CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Ventana > "
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_WDT=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MXC_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_LAN75XX=y
+CONFIG_USB_ETHER_LAN78XX=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Gateworks"
# CONFIG_VIDEO_ANSI is not set
CONFIG_SYS_WHITE_ON_BLACK=y
# CONFIG_PANEL is not set
+CONFIG_I2C_EDID=y
CONFIG_VIDEO_IPUV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_WATCHDOG_TIMEOUT_MSECS=60000
+CONFIG_IMX_WATCHDOG=y
CONFIG_FDT_FIXUP_PARTITIONS=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_CMD_EECONFIG=y
CONFIG_CMD_GSC=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-gw54xx"
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_POWER=y
-CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Ventana > "
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_PART=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_WDT=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MXC_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_LAN75XX=y
+CONFIG_USB_ETHER_LAN78XX=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Gateworks"
# CONFIG_VIDEO_ANSI is not set
CONFIG_SYS_WHITE_ON_BLACK=y
# CONFIG_PANEL is not set
+CONFIG_I2C_EDID=y
CONFIG_VIDEO_IPUV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_WATCHDOG_TIMEOUT_MSECS=60000
+CONFIG_IMX_WATCHDOG=y
CONFIG_FDT_FIXUP_PARTITIONS=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00800000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_HELIOS4=y
CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_HIGHBANK=y
CONFIG_SYS_TEXT_BASE=0x00008000
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
-CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_SYS_BOOTCOUNT_ADDR=0xfff3cf0c
CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_TEXT_BASE=0x50000000
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xFFFE0000
-CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r8a774a1-hihope-rzg2m-u-boot"
CONFIG_RCAR_GEN3=y
CONFIG_ARM=y
CONFIG_TARGET_HIKEY960=y
CONFIG_SYS_TEXT_BASE=0x1ac98000
+CONFIG_SYS_MALLOC_LEN=0x801000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x1000
-CONFIG_SYS_MALLOC_LEN=0x801000
CONFIG_DEFAULT_DEVICE_TREE="hi3660-hikey960"
CONFIG_IDENT_STRING="\nHikey960"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ARM=y
CONFIG_SYS_TEXT_BASE=0x35000000
+CONFIG_SYS_MALLOC_LEN=0x801000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=6
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x0
-CONFIG_SYS_MALLOC_LEN=0x801000
CONFIG_DEFAULT_DEVICE_TREE="hi6220-hikey"
CONFIG_IDENT_STRING="hikey"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFF00000
+CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_SYS_BOOTCOUNT_ADDR=0x9
CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
CONFIG_MIPS=y
CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_SYS_MALLOC_F_LEN=0x600
CONFIG_ENV_SIZE=0x4000
-CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_DEFAULT_DEVICE_TREE="nexys4ddr"
CONFIG_TARGET_XILFPGA=y
CONFIG_MIPS_CACHE_SETUP=y
CONFIG_SPL_SYS_THUMB_BUILD=y
CONFIG_ARCH_MX28=y
CONFIG_SYS_TEXT_BASE=0x40002000
+CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_NR_DRAM_BANKS=1
CONFIG_IMX_CONFIG=""
CONFIG_DM_GPIO=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_OFFSET=0x400000
CONFIG_MX6QDL=y
CONFIG_TARGET_MX6Q_ENGICAM=y
-CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-icore"
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_SERIAL=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_BOOTDELAY=3
CONFIG_SPL_DMA=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="icorem6qdl> "
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_LEN=0x2300000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x88000000
CONFIG_ENV_OFFSET=0x100000
CONFIG_MX6QDL=y
CONFIG_TARGET_MX6DL_MAMOJ=y
-CONFIG_SYS_MALLOC_LEN=0x2300000
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-mamoj"
CONFIG_SPL_TEXT_BASE=0x00908000
+CONFIG_SPL_DRIVERS_MISC=y
CONFIG_IMX_HAB=y
# CONFIG_CMD_BMODE is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_OFFSET=0x400000
CONFIG_MX6QDL=y
CONFIG_TARGET_MX6Q_ENGICAM=y
-CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore"
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_SERIAL=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=3
CONFIG_SPL_DMA=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="icorem6qdl> "
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_MX6Q=y
CONFIG_MX6_OCRAM_256KB=y
CONFIG_TARGET_MX6LOGICPD=y
-CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DEFAULT_DEVICE_TREE="imx6q-logicpd"
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_MMC=y
CONFIG_PCF8575_GPIO=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x0
+CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_OFFSET=0x100000
CONFIG_MX6QDL=y
CONFIG_TARGET_MX6Q_ENGICAM=y
-CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore-mipi"
CONFIG_SPL_TEXT_BASE=0x00908000
+CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0x021f0000
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=3
+CONFIG_SPL_RAW_IMAGE_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_OFFSET=0x100000
CONFIG_MX6QDL=y
CONFIG_TARGET_MX6Q_ENGICAM=y
-CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore"
CONFIG_SPL_TEXT_BASE=0x00908000
+CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_BOOTCOUNT_ADDR=0x020D8024
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=3
+CONFIG_SPL_RAW_IMAGE_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_OFFSET=0x400000
CONFIG_MX6QDL=y
CONFIG_TARGET_MX6Q_ENGICAM=y
-CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore"
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_SERIAL=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=3
CONFIG_SPL_DMA=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="icorem6qdl> "
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_OFFSET=0x100000
CONFIG_MX6QDL=y
CONFIG_TARGET_MX6Q_ENGICAM=y
-CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore-rqs"
CONFIG_SPL_TEXT_BASE=0x00908000
+CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=3
+CONFIG_SPL_RAW_IMAGE_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_OFFSET=0x100000
CONFIG_MX6UL=y
CONFIG_TARGET_MX6UL_ENGICAM=y
-CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-geam"
CONFIG_SPL_TEXT_BASE=0x00908000
+CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=3
+CONFIG_SPL_RAW_IMAGE_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="geam6ul> "
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_OFFSET=0x400000
CONFIG_MX6UL=y
CONFIG_TARGET_MX6UL_ENGICAM=y
-CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-geam"
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_SERIAL=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=3
CONFIG_SPL_DMA=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="geam6ul> "
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_OFFSET=0x100000
CONFIG_MX6UL=y
CONFIG_TARGET_MX6UL_ENGICAM=y
-CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-isiot-emmc"
CONFIG_SPL_TEXT_BASE=0x00908000
+CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=3
+CONFIG_SPL_RAW_IMAGE_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="isiotmx6ul> "
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_OFFSET=0x400000
CONFIG_MX6UL=y
CONFIG_TARGET_MX6UL_ENGICAM=y
-CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-isiot-nand"
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_SERIAL=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=3
CONFIG_SPL_DMA=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="isiotmx6ul> "
CONFIG_ARM=y
CONFIG_ARCH_MX7=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7-cm"
CONFIG_TARGET_IMX7_CM=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x4400
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-cl-iot-gate-optee"
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_TARGET_IMX8MM_CL_IOT_GATE_OPTEE=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_PROMPT="u-boot=> "
+CONFIG_CMD_BOOTEFI_SELFTEST=y
+CONFIG_CMD_NVEDIT_EFI=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_SHA1SUM=y
+CONFIG_CMD_BIND=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_TPM=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MM=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x44000000
+CONFIG_FASTBOOT_BUF_SIZE=0x5000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=2
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_KEYBOARD=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PCI_ENDPOINT=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_BD71837=y
+CONFIG_SPL_DM_PMIC_BD71837=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_BD71837=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_ABX80X=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+CONFIG_DM_THERMAL=y
+CONFIG_TPM2_TIS_SPI=y
+CONFIG_TPM2_FTPM_TEE=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_SDP_LOADADDR=0x40400000
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_TPM=y
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y
+CONFIG_EFI_SECURE_BOOT=y
CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x4400
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mm-cl-iot-gate"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_DM_KEYBOARD=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC_IMX=y
+CONFIG_FSL_USDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
CONFIG_ARM=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mm-icore-mx8mm-ctouch2"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_ARM=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mm-icore-mx8mm-edimm2.2"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_ARM=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mm-beacon-kit"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_ARM=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
-CONFIG_FSL_ESDHC_IMX=y
+CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
CONFIG_DM_ETH=y
CONFIG_ARM=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_SYS_MEMTEST_START=0x40000000
CONFIG_SYS_MEMTEST_END=0x80000000
CONFIG_ENV_SIZE=0x8000
CONFIG_ENV_OFFSET=0xff0000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mm-venice"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_ARM=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x40000000
CONFIG_SYS_MEMTEST_END=0x44000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFDE00
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mn-beacon-kit"
CONFIG_SPL_TEXT_BASE=0x912000
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent interrupts"
+CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=2
CONFIG_ARM=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x40000000
CONFIG_SYS_MEMTEST_END=0x44000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFDE00
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mn-beacon-kit"
CONFIG_SPL_TEXT_BASE=0x912000
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent interrupts"
+CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=2
CONFIG_ARM=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mn-ddr4-evk"
CONFIG_SPL_TEXT_BASE=0x912000
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
-CONFIG_FSL_ESDHC_IMX=y
+CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_DM_ETH=y
CONFIG_PINCTRL=y
CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mn-evk"
CONFIG_SPL_TEXT_BASE=0x912000
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
-CONFIG_FSL_ESDHC_IMX=y
+CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_DM_ETH=y
CONFIG_PINCTRL=y
CONFIG_ARM=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mp-evk"
CONFIG_SPL_TEXT_BASE=0x920000
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
-CONFIG_FSL_ESDHC_IMX=y
+CONFIG_FSL_USDHC=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
CONFIG_PHY_GIGE=y
CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_ARM=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x600000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0x600000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mq-cm"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
+CONFIG_IMX_BOOTAUX=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y
CONFIG_ARM=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x600000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0x600000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mq-evk"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_TARGET_IMX8MQ_EVK=y
+CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
+CONFIG_IMX_BOOTAUX=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_PROMPT="u-boot=> "
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
CONFIG_PHY=y
CONFIG_PHY_IMX8MQ_USB=y
CONFIG_PINCTRL=y
CONFIG_ARM=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x600000
CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0x600000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mq-phanbell"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_TARGET_IMX8MQ_PHANBELL=y
+CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
+CONFIG_IMX_BOOTAUX=y
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SD_BOOT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
CONFIG_HUSH_PARSER=y
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_CMD_EXPORTENV is not set
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
CONFIG_SPL_POWER_LEGACY=y
CONFIG_ARM=y
CONFIG_ARCH_IMX8=y
CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
-CONFIG_SYS_MALLOC_LEN=0x2400000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek"
CONFIG_SPL_TEXT_BASE=0x100000
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_ARM=y
CONFIG_ARCH_IMX8=y
CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2800000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x400000
-CONFIG_SYS_MALLOC_LEN=0x2800000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8qm-rom7720-a1"
CONFIG_TARGET_IMX8QM_ROM7720_A1=y
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_MISC=y
-CONFIG_FSL_ESDHC_IMX=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_ATHEROS=y
CONFIG_ARM=y
CONFIG_ARCH_IMX8=y
CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
-CONFIG_SYS_MALLOC_LEN=0x2400000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek"
CONFIG_SPL_TEXT_BASE=0x100000
CONFIG_ARM=y
CONFIG_ARCH_IMX8ULP=y
CONFIG_SYS_TEXT_BASE=0x80200000
+CONFIG_SYS_MALLOC_LEN=0x1002000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x400000
CONFIG_IMX_CONFIG=""
-CONFIG_SYS_MALLOC_LEN=0x1002000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8ulp-evk"
CONFIG_SPL_TEXT_BASE=0x22020000
CONFIG_BOOTDELAY=0
CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx8ulp-evk"
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_ARM=y
CONFIG_ARCH_IMXRT=y
CONFIG_SYS_TEXT_BASE=0x80002000
+CONFIG_SYS_MALLOC_LEN=0x100000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0x80000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imxrt1020-evk"
CONFIG_SPL_TEXT_BASE=0x20209000
# CONFIG_SPL_SYS_DCACHE_OFF is not set
CONFIG_ARCH_IMXRT=y
CONFIG_SYS_TEXT_BASE=0x80002000
+CONFIG_SYS_MALLOC_LEN=0x100000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0x80000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imxrt1050-evk"
CONFIG_SPL_TEXT_BASE=0x20209000
CONFIG_ARM=y
CONFIG_ARCH_INTEGRATOR=y
CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_SYS_MALLOC_LEN=0x28000
CONFIG_ARCH_INTEGRATOR_AP=y
CONFIG_CM720T=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x8000
-CONFIG_SYS_MALLOC_LEN=0x28000
CONFIG_SYS_LOAD_ADDR=0x7fc0
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAM0 console=tty"
CONFIG_ARM=y
CONFIG_ARCH_INTEGRATOR=y
CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_SYS_MALLOC_LEN=0x28000
CONFIG_ARCH_INTEGRATOR_AP=y
CONFIG_CM920T=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x8000
-CONFIG_SYS_MALLOC_LEN=0x28000
CONFIG_SYS_LOAD_ADDR=0x7fc0
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAM0 console=tty"
CONFIG_ARM=y
CONFIG_ARCH_INTEGRATOR=y
CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_SYS_MALLOC_LEN=0x28000
CONFIG_ARCH_INTEGRATOR_AP=y
CONFIG_CM926EJ_S=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x8000
-CONFIG_SYS_MALLOC_LEN=0x28000
CONFIG_SYS_LOAD_ADDR=0x7fc0
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAM0 console=tty"
CONFIG_ARM=y
CONFIG_ARCH_INTEGRATOR=y
CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_SYS_MALLOC_LEN=0x28000
CONFIG_ARCH_INTEGRATOR_AP=y
CONFIG_CM946ES=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x8000
-CONFIG_SYS_MALLOC_LEN=0x28000
CONFIG_SYS_LOAD_ADDR=0x7fc0
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAM0 console=tty"
CONFIG_ARM=y
CONFIG_ARCH_INTEGRATOR=y
CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_SYS_MALLOC_LEN=0x22000
CONFIG_ARCH_INTEGRATOR_CP=y
CONFIG_CM1136=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_SYS_MALLOC_LEN=0x22000
CONFIG_SYS_LOAD_ADDR=0x7fc0
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0"
CONFIG_ARM=y
CONFIG_ARCH_INTEGRATOR=y
CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_SYS_MALLOC_LEN=0x22000
CONFIG_ARCH_INTEGRATOR_CP=y
CONFIG_CM920T=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_SYS_MALLOC_LEN=0x22000
CONFIG_SYS_LOAD_ADDR=0x7fc0
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0"
CONFIG_ARM=y
CONFIG_ARCH_INTEGRATOR=y
CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_SYS_MALLOC_LEN=0x22000
CONFIG_ARCH_INTEGRATOR_CP=y
CONFIG_CM926EJ_S=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_SYS_MALLOC_LEN=0x22000
CONFIG_SYS_LOAD_ADDR=0x7fc0
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0"
CONFIG_ARM=y
CONFIG_ARCH_INTEGRATOR=y
CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_SYS_MALLOC_LEN=0x22000
CONFIG_ARCH_INTEGRATOR_CP=y
CONFIG_CM946ES=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_SYS_MALLOC_LEN=0x22000
CONFIG_SYS_LOAD_ADDR=0x7fc0
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0"
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_K3=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_AM6=y
CONFIG_TARGET_IOT2050_A53=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x680000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-am6528-iot2050-basic"
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTSTAGE=y
+CONFIG_SHOW_BOOT_PROGRESS=y
+CONFIG_SPL_SHOW_BOOT_PROGRESS=y
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_TARGET_IOT_DEVKIT=y
CONFIG_SYS_TEXT_BASE=0x00000000
-CONFIG_ENV_SIZE=0x1000
CONFIG_SYS_MALLOC_LEN=0x10000
+CONFIG_ENV_SIZE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="iot_devkit"
CONFIG_SYS_CLK_FREQ=16000000
CONFIG_LOCALVERSION="-iotdk-1.0"
CONFIG_ARM=y
CONFIG_ARCH_K3=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_J721E=y
CONFIG_TARGET_J7200_A72_EVM=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x680000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-j7200-common-proc-board"
CONFIG_ARM=y
CONFIG_ARCH_K3=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x70000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x70000
CONFIG_SOC_K3_J721E=y
CONFIG_K3_EARLY_CONS=y
CONFIG_TARGET_J7200_R5_EVM=y
CONFIG_ENV_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-j7200-r5-common-proc-board"
CONFIG_ARM=y
CONFIG_ARCH_K3=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_J721E=y
CONFIG_TARGET_J721E_A72_EVM=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x680000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-common-proc-board"
CONFIG_ARM=y
CONFIG_ARCH_K3=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x70000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x70000
CONFIG_SOC_K3_J721E=y
CONFIG_K3_EARLY_CONS=y
CONFIG_TARGET_J721E_R5_EVM=y
CONFIG_ENV_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-r5-common-proc-board"
CONFIG_ARM=y
CONFIG_ARCH_K3=y
CONFIG_TI_SECURE_DEVICE=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_J721E=y
CONFIG_TARGET_J721E_A72_EVM=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x680000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-common-proc-board"
CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_ARM=y
CONFIG_ARCH_K3=y
CONFIG_TI_SECURE_DEVICE=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x55000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x55000
CONFIG_SOC_K3_J721E=y
CONFIG_TARGET_J721E_R5_EVM=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x680000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-r5-common-proc-board"
CONFIG_ARM=y
+CONFIG_SYS_BOARD="jethub-j100"
CONFIG_SYS_CONFIG_NAME="jethub"
CONFIG_ARCH_MESON=y
CONFIG_SYS_TEXT_BASE=0x01000000
CONFIG_ARM=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80110000
+CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFE000
-CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_DEFAULT_DEVICE_TREE="tegra124-jetson-tk1"
CONFIG_SPL_TEXT_BASE=0x80108000
CONFIG_TEGRA124=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_ISW_ENTRY_ADDR=0xC100000
CONFIG_SYS_TEXT_BASE=0xC000000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_K2E_EVM=y
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x100000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="keystone-k2e-evm"
CONFIG_SPL_SERIAL=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_ISW_ENTRY_ADDR=0xC100000
CONFIG_SYS_TEXT_BASE=0xC000060
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_K2E_EVM=y
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x100000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="keystone-k2e-evm"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_IMAGE_POST_PROCESS=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_ISW_ENTRY_ADDR=0xC0A0000
CONFIG_SYS_TEXT_BASE=0xC000000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_K2G_EVM=y
CONFIG_ENV_SIZE=0x40000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="keystone-k2g-evm"
CONFIG_SPL_SERIAL=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_ISW_ENTRY_ADDR=0xC0A0000
CONFIG_SYS_TEXT_BASE=0xC000060
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_K2G_EVM=y
CONFIG_ENV_SIZE=0x40000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="keystone-k2g-evm"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_IMAGE_POST_PROCESS=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_ISW_ENTRY_ADDR=0xC200000
CONFIG_SYS_TEXT_BASE=0xC000000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_K2HK_EVM=y
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x100000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="keystone-k2hk-evm"
CONFIG_SPL_SERIAL=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_ISW_ENTRY_ADDR=0xC200000
CONFIG_SYS_TEXT_BASE=0xC000060
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_K2HK_EVM=y
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x100000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="keystone-k2hk-evm"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_IMAGE_POST_PROCESS=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_ISW_ENTRY_ADDR=0xC100000
CONFIG_SYS_TEXT_BASE=0xC000000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_K2L_EVM=y
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x100000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="keystone-k2l-evm"
CONFIG_SPL_SERIAL=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_ISW_ENTRY_ADDR=0xC100000
CONFIG_SYS_TEXT_BASE=0xC000060
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_K2L_EVM=y
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x100000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="keystone-k2l-evm"
CONFIG_FIT_IMAGE_POST_PROCESS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_LAST_STAGE_INIT=y
+CONFIG_MISC_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0xE8020000
CONFIG_RGMII=y
CONFIG_MII=y
CONFIG_PCI_REGION_MULTI_ENTRY=y
CONFIG_PCIE_FSL=y
CONFIG_U_QE=y
+CONFIG_SYS_QE_FW_ADDR=0xE8040000
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
# CONFIG_PCI is not set
# CONFIG_PINCTRL_FULL is not set
CONFIG_QE=y
+CONFIG_SYS_QE_FW_ADDR=0xF00C0000
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_BCH=y
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_TEXT_BASE=0x50000000
+CONFIG_SYS_MALLOC_LEN=0x100000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r8a7791-koelsch-u-boot"
CONFIG_SPL_TEXT_BASE=0xe6300000
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_SYS_MALLOC_LEN=0x4000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x90000000
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0xF0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_MX6UL=y
+CONFIG_TARGET_KONTRON_MX6UL=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ul-kontron-n631x-s"
+CONFIG_SPL_TEXT_BASE=0x00908000
+CONFIG_BOOTCOUNT_BOOTLIMIT=3
+CONFIG_SPL=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_TYPES=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y
+CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8A
+CONFIG_SPL_USB_HOST=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_SDP=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FS_UUID=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nor0=spi1.0,spi-nand0=spi4.0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=spi1.0:128k(spl),832k(u-boot),64k(env);spi4.0:-(UBI)"
+CONFIG_CMD_UBI=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIST="imx6ul-kontron-n631x-s imx6ull-kontron-n641x-s"
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_USE_ENV_SPI_BUS=y
+CONFIG_ENV_SPI_BUS=2
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_BOOTCOUNT_ENV=y
+CONFIG_DM_I2C=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SF_DEFAULT_SPEED=10000000
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_CONS_INDEX=4
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_MXC_SPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x4000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x1f0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_IMX_CONFIG="board/kontron/sl-mx8mm/imximage.cfg"
+CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-kontron-n801x-s"
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_TARGET_KONTRON_MX8MM=y
+CONFIG_BOOTCOUNT_BOOTLIMIT=3
+CONFIG_SPL=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOARD_TYPES=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+# CONFIG_SPL_FIT_IMAGE_TINY is not set
+CONFIG_SPL_I2C=y
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SPL_ATF=y
+CONFIG_CMD_NVEDIT_EFI=y
+# CONFIG_CMD_LZMADEC is not set
+# CONFIG_CMD_UNZIP is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_WDT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIST="imx8mm-kontron-n801x-s imx8mm-kontron-n801x-s-lvds"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_USE_ENV_SPI_BUS=y
+CONFIG_ENV_SPI_BUS=0
+CONFIG_USE_ENV_SPI_MAX_HZ=y
+CONFIG_ENV_SPI_MAX_HZ=80000000
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_BOOTCOUNT_ENV=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MM=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_DFU_SF=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=80000000
+CONFIG_SPI_FLASH_MACRONIX=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MSCC=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PCA9450=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_RV8803=y
+CONFIG_CONS_INDEX=2
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MXC_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+# CONFIG_WATCHDOG_AUTOSTART is not set
+CONFIG_IMX_WATCHDOG=y
+# CONFIG_HEXDUMP is not set
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_IGNORE_OSINDICATIONS=y
+CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y
CONFIG_ARM=y
CONFIG_TARGET_SL28=y
+CONFIG_SYS_MALLOC_LEN=0x202000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x3e0000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-kontron-sl28"
CONFIG_SPL_TEXT_BASE=0x18010000
CONFIG_SYS_FSL_SDHC_CLK_DIV=1
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_NVEDIT_EFI=y
+CONFIG_CMD_DFU=y
CONFIG_CMD_DM=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_RNG=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_SF=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_MUX=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_NXP_FSPI=y
CONFIG_USB=y
# CONFIG_SPL_DM_USB is not set
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
+# CONFIG_USB_XHCI_FSL is not set
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_LAYERSCAPE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_OF_LIBFDT_ASSUME_MASK=0x0
CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_IGNORE_OSINDICATIONS=y
+CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y
CONFIG_ARM=y
CONFIG_ARCH_MX5=y
CONFIG_SYS_TEXT_BASE=0x77800000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_TARGET_KP_IMX53=y
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="imx53-kp"
CONFIG_ENV_OFFSET_REDUND=0x102000
# CONFIG_CMD_BMODE is not set
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_F_LEN=0x2200
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2200
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
# CONFIG_SYS_THUMB_BUILD is not set
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_SYS_MALLOC_LEN=0x60000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_SYS_MALLOC_LEN=0x60000
CONFIG_ARCH_RMOBILE_BOARD_STRING="KMC KZM-A9-GT"
CONFIG_TARGET_KZM9G=y
CONFIG_SYS_LOAD_ADDR=0x43000000
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_TEXT_BASE=0x50000000
+CONFIG_SYS_MALLOC_LEN=0x100000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r8a7790-lager-u-boot"
CONFIG_SPL_TEXT_BASE=0xe6300000
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_DAVINCI=y
CONFIG_SYS_TEXT_BASE=0xc1080000
+CONFIG_SYS_MALLOC_LEN=0x110000
CONFIG_TARGET_LEGOEV3=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4000
-CONFIG_SYS_MALLOC_LEN=0x110000
CONFIG_DEFAULT_DEVICE_TREE="da850-lego-ev3"
CONFIG_SYS_LOAD_ADDR=0xc0700000
CONFIG_BOOTDELAY=0
CONFIG_MIPS=y
CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x80000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="linkit-smart-7688"
CONFIG_SPL_SERIAL=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_OFFSET=0x80000
CONFIG_MX6UL=y
CONFIG_TARGET_LITEBOARD=y
-CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-liteboard"
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_PHYLIB=y
CONFIG_PHY_SMSC=y
CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_ARM=y
CONFIG_TARGET_LS1012A2G5RDB=y
CONFIG_SYS_TEXT_BASE=0x40100000
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-2g5rdb"
CONFIG_FSL_LS_PPA=y
CONFIG_TARGET_LS1012A2G5RDB=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-2g5rdb"
CONFIG_QSPI_AHB_INIT=y
CONFIG_ARM=y
CONFIG_TARGET_LS1012AFRDM=y
CONFIG_SYS_TEXT_BASE=0x40100000
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm"
CONFIG_FSL_LS_PPA=y
CONFIG_TARGET_LS1012AFRDM=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm"
CONFIG_QSPI_AHB_INIT=y
CONFIG_ARM=y
CONFIG_TARGET_LS1012AFRWY=y
CONFIG_SYS_TEXT_BASE=0x40100000
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
-CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy"
CONFIG_FSL_LS_PPA=y
CONFIG_ARM=y
CONFIG_TARGET_LS1012AFRWY=y
CONFIG_SYS_TEXT_BASE=0x40100000
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x1D0000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy"
CONFIG_FSL_LS_PPA=y
CONFIG_TARGET_LS1012AFRWY=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
-CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy"
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_TARGET_LS1012AFRWY=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x1D0000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy"
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_ARM=y
CONFIG_TARGET_LS1012AQDS=y
CONFIG_SYS_TEXT_BASE=0x40100000
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds"
CONFIG_FSL_LS_PPA=y
CONFIG_TARGET_LS1012AQDS=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
-CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds"
CONFIG_QSPI_AHB_INIT=y
CONFIG_TARGET_LS1012AQDS=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds"
CONFIG_QSPI_AHB_INIT=y
CONFIG_ARM=y
CONFIG_TARGET_LS1012ARDB=y
CONFIG_SYS_TEXT_BASE=0x40100000
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
-CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
CONFIG_FSL_LS_PPA=y
CONFIG_ARM=y
CONFIG_TARGET_LS1012ARDB=y
CONFIG_SYS_TEXT_BASE=0x40100000
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
CONFIG_FSL_LS_PPA=y
CONFIG_TARGET_LS1012ARDB=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
-CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
CONFIG_QSPI_AHB_INIT=y
CONFIG_TARGET_LS1012ARDB=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
CONFIG_QSPI_AHB_INIT=y
CONFIG_ARM=y
CONFIG_TARGET_LS1021AIOT=y
CONFIG_SYS_TEXT_BASE=0x40010000
+CONFIG_SYS_MALLOC_LEN=0x1002000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0x1002000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart"
CONFIG_AHCI=y
CONFIG_ARM=y
CONFIG_TARGET_LS1021AIOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x1002000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0x1002000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart"
CONFIG_SPL_TEXT_BASE=0x10000000
+CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_AHCI=y
CONFIG_SPL_FSL_PBL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y
+CONFIG_SPL_WATCHDOG=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GREPENV=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_SYS_QE_FW_ADDR=0xf40000
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_TARGET_LS1021AQDS=y
CONFIG_SYS_TEXT_BASE=0x60100000
+CONFIG_SYS_MALLOC_LEN=0x1002000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0x1002000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_SYS_QE_FW_ADDR=0x60940000
CONFIG_DM_SCSI=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_TARGET_LS1021AQDS=y
CONFIG_SYS_TEXT_BASE=0x60100000
+CONFIG_SYS_MALLOC_LEN=0x1002000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0x1002000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_SYS_QE_FW_ADDR=0x60940000
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_TARGET_LS1021AQDS=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x1002000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0x1002000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x1c000
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_TARGET_LS1021AQDS=y
CONFIG_SYS_TEXT_BASE=0x60100000
+CONFIG_SYS_MALLOC_LEN=0x1002000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0x1002000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_SYS_QE_FW_ADDR=0x60940000
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_TARGET_LS1021AQDS=y
CONFIG_SYS_TEXT_BASE=0x60100000
+CONFIG_SYS_MALLOC_LEN=0x1002000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0x1002000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_SYS_QE_FW_ADDR=0x60940000
CONFIG_DM_SCSI=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_TARGET_LS1021AQDS=y
CONFIG_SYS_TEXT_BASE=0x60100000
+CONFIG_SYS_MALLOC_LEN=0x1002000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0x1002000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_SYS_QE_FW_ADDR=0x60940000
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_TARGET_LS1021AQDS=y
CONFIG_SYS_TEXT_BASE=0x40100000
+CONFIG_SYS_MALLOC_LEN=0x1002000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0x1002000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_TARGET_LS1021AQDS=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x1002000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0x1002000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_TARGET_LS1021AQDS=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x1002000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0x1002000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_ARM=y
CONFIG_TARGET_LS1021ATSN=y
CONFIG_SYS_TEXT_BASE=0x40100000
+CONFIG_SYS_MALLOC_LEN=0x1002000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0x1002000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-tsn"
CONFIG_AHCI=y
CONFIG_ARM=y
CONFIG_TARGET_LS1021ATSN=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x1020000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0x1020000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-tsn"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_TARGET_LS1021ATWR=y
CONFIG_SYS_TEXT_BASE=0x60100000
+CONFIG_SYS_MALLOC_LEN=0x1020000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0x1020000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
CONFIG_AHCI=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_SYS_QE_FW_ADDR=0x60940000
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_TARGET_LS1021ATWR=y
CONFIG_SYS_TEXT_BASE=0x60100000
+CONFIG_SYS_MALLOC_LEN=0x1020000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0x1020000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
CONFIG_AHCI=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_SYS_QE_FW_ADDR=0x60940000
CONFIG_DM_SCSI=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_TARGET_LS1021ATWR=y
CONFIG_SYS_TEXT_BASE=0x60100000
+CONFIG_SYS_MALLOC_LEN=0x1020000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0x1020000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-lpuart"
CONFIG_AHCI=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_SYS_QE_FW_ADDR=0x60940000
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_TARGET_LS1021ATWR=y
CONFIG_SYS_TEXT_BASE=0x40100000
+CONFIG_SYS_MALLOC_LEN=0x1002000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0x1002000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
CONFIG_AHCI=y
CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_TARGET_LS1021ATWR=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x1020000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0x1020000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_SYS_QE_FW_ADDR=0x940000
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_TARGET_LS1021ATWR=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x1020000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0x1020000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_TARGET_LS1021ATWR=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x1020000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0x1020000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_GIC_V3_ITS=y
CONFIG_TARGET_LS1028AQDS=y
CONFIG_TFABOOT=y
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_SYS_MALLOC_F_LEN=0x6000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
-CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds-duart"
CONFIG_FSPI_AHB_EN_4BYTE=y
CONFIG_GIC_V3_ITS=y
CONFIG_TARGET_LS1028AQDS=y
CONFIG_TFABOOT=y
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_SYS_MALLOC_F_LEN=0x6000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds-duart"
CONFIG_FSPI_AHB_EN_4BYTE=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_TARGET_LS1028AQDS=y
CONFIG_TFABOOT=y
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_SYS_MALLOC_F_LEN=0x6000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds-lpuart"
CONFIG_FSPI_AHB_EN_4BYTE=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_VITESSE=y
+CONFIG_PHY_FIXED=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
CONFIG_GIC_V3_ITS=y
CONFIG_TARGET_LS1028ARDB=y
CONFIG_TFABOOT=y
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_SYS_MALLOC_F_LEN=0x6000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
-CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-rdb"
CONFIG_FSPI_AHB_EN_4BYTE=y
CONFIG_GIC_V3_ITS=y
CONFIG_TARGET_LS1028ARDB=y
CONFIG_TFABOOT=y
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_SYS_MALLOC_F_LEN=0x6000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-rdb"
CONFIG_FSPI_AHB_EN_4BYTE=y
CONFIG_ARM=y
CONFIG_TARGET_LS1043AQDS=y
CONFIG_SYS_TEXT_BASE=0x60100000
+CONFIG_SYS_MALLOC_LEN=0x120000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_SYS_MALLOC_LEN=0x120000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x60900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_SYS_QE_FW_ADDR=0x60940000
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_ARM=y
CONFIG_TARGET_LS1043AQDS=y
CONFIG_SYS_TEXT_BASE=0x60100000
+CONFIG_SYS_MALLOC_LEN=0x120000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_SYS_MALLOC_LEN=0x120000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-lpuart"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x60900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_SYS_QE_FW_ADDR=0x60940000
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_ARM=y
CONFIG_TARGET_LS1043AQDS=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_ARM=y
CONFIG_TARGET_LS1043AQDS=y
CONFIG_SYS_TEXT_BASE=0x60100000
+CONFIG_SYS_MALLOC_LEN=0x120000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_SYS_MALLOC_LEN=0x120000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x60900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_SYS_QE_FW_ADDR=0x60940000
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_ARM=y
CONFIG_TARGET_LS1043AQDS=y
CONFIG_SYS_TEXT_BASE=0x40100000
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x40900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_ARM=y
CONFIG_TARGET_LS1043AQDS=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_SYS_QE_FW_ADDR=0x940000
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_ARM=y
CONFIG_TARGET_LS1043AQDS=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_SYS_QE_FW_ADDR=0x940000
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_TARGET_LS1043AQDS=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_SYS_QE_FW_ADDR=0x940000
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_TARGET_LS1043AQDS=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_SYS_QE_FW_ADDR=0x940000
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_ARM=y
CONFIG_TARGET_LS1043ARDB=y
CONFIG_SYS_TEXT_BASE=0x60100000
+CONFIG_SYS_MALLOC_LEN=0x120000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x20000
CONFIG_NXP_ESBC=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_SYS_MALLOC_LEN=0x120000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
CONFIG_FSL_LS_PPA=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x60900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_SYS_QE_FW_ADDR=0x60940000
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_ARM=y
CONFIG_TARGET_LS1043ARDB=y
CONFIG_SYS_TEXT_BASE=0x60100000
+CONFIG_SYS_MALLOC_LEN=0x120000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_SYS_MALLOC_LEN=0x120000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
CONFIG_FSL_LS_PPA=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x60900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_SYS_QE_FW_ADDR=0x60940000
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_ARM=y
CONFIG_TARGET_LS1043ARDB=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
-CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_ARM=y
CONFIG_TARGET_LS1043ARDB=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_ARM=y
CONFIG_TARGET_LS1043ARDB=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
-CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_SYS_QE_FW_ADDR=0x940000
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_ARM=y
CONFIG_TARGET_LS1043ARDB=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_SYS_QE_FW_ADDR=0x940000
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_TARGET_LS1043ARDB=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_SYS_QE_FW_ADDR=0x940000
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TARGET_LS1043ARDB=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x500000
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_SYS_QE_FW_ADDR=0x940000
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TARGET_LS1046AFRWY=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
-CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-frwy"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_TARGET_LS1046AFRWY=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-frwy"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_ARM=y
CONFIG_TARGET_LS1046AQDS=y
CONFIG_SYS_TEXT_BASE=0x60100000
+CONFIG_SYS_MALLOC_LEN=0x120000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_SYS_MALLOC_LEN=0x120000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x60900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_RSA=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_ARM=y
CONFIG_TARGET_LS1046AQDS=y
CONFIG_SYS_TEXT_BASE=0x60100000
+CONFIG_SYS_MALLOC_LEN=0x120000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_SYS_MALLOC_LEN=0x120000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x60900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_ARM=y
CONFIG_TARGET_LS1046AQDS=y
CONFIG_SYS_TEXT_BASE=0x60100000
+CONFIG_SYS_MALLOC_LEN=0x120000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_SYS_MALLOC_LEN=0x120000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-lpuart"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x60900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_ARM=y
CONFIG_TARGET_LS1046AQDS=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x102000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_WATCHDOG=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_ARM=y
CONFIG_TARGET_LS1046AQDS=y
CONFIG_SYS_TEXT_BASE=0x40100000
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x40900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_ARM=y
CONFIG_TARGET_LS1046AQDS=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_ARM=y
CONFIG_TARGET_LS1046AQDS=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_TARGET_LS1046AQDS=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_RSA=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_TARGET_LS1046AQDS=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x500000
-CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USE_ENV_SPI_BUS=y
CONFIG_ENV_SPI_BUS=0
-CONFIG_ENV_ADDR=0x40500000
+CONFIG_ENV_ADDR=0x60500000
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_ARM=y
CONFIG_TARGET_LS1046ARDB=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_ARM=y
CONFIG_TARGET_LS1046ARDB=y
CONFIG_SYS_TEXT_BASE=0x40100000
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_FSL_LS_PPA=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x40900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_ARM=y
CONFIG_TARGET_LS1046ARDB=y
CONFIG_SYS_TEXT_BASE=0x40100000
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_FSL_LS_PPA=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x40900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_ARM=y
CONFIG_TARGET_LS1046ARDB=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x40900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_ARM=y
CONFIG_TARGET_LS1046ARDB=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_ARM=y
CONFIG_TARGET_LS1046ARDB=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_TARGET_LS1046ARDB=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_QSPI_AHB_INIT=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_TARGET_LS1046ARDB=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x500000
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_QSPI_AHB_INIT=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_GIC_V3_ITS=y
CONFIG_TARGET_LS1088AQDS=y
CONFIG_SYS_TEXT_BASE=0x30100000
+CONFIG_SYS_MALLOC_LEN=0x0220000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x0220000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
+CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_NVME=y
CONFIG_GIC_V3_ITS=y
CONFIG_TARGET_LS1088AQDS=y
CONFIG_SYS_TEXT_BASE=0x20100000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
-CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
+CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_NVME=y
CONFIG_USB_GADGET=y
CONFIG_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_GIC_V3_ITS=y
CONFIG_TARGET_LS1088AQDS=y
CONFIG_SYS_TEXT_BASE=0x20100000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
+CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_NVME=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_GADGET=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_GIC_V3_ITS=y
CONFIG_TARGET_LS1088AQDS=y
CONFIG_SYS_TEXT_BASE=0x80400000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
-CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
CONFIG_SPL_TEXT_BASE=0x1800a000
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
+CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_NVME=y
CONFIG_GIC_V3_ITS=y
CONFIG_TARGET_LS1088AQDS=y
CONFIG_SYS_TEXT_BASE=0x80400000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
-CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
CONFIG_SPL_TEXT_BASE=0x1800a000
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
+CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_NVME=y
CONFIG_TARGET_LS1088AQDS=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x0220000
CONFIG_SYS_MALLOC_F_LEN=0x6000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_SYS_MALLOC_LEN=0x0220000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
CONFIG_FSL_USE_PCA9547_MUX=y
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_MISC_INIT_R=y
CONFIG_CMD_GREPENV=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
+CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_MDIO_MUX_I2CREG=y
CONFIG_GIC_V3_ITS=y
CONFIG_TARGET_LS1088ARDB=y
CONFIG_SYS_TEXT_BASE=0x20100000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
-CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
+CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_FSL_LS_MDIO=y
CONFIG_GIC_V3_ITS=y
CONFIG_TARGET_LS1088ARDB=y
CONFIG_SYS_TEXT_BASE=0x20100000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
+CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_FSL_LS_MDIO=y
CONFIG_GIC_V3_ITS=y
CONFIG_TARGET_LS1088ARDB=y
CONFIG_SYS_TEXT_BASE=0x80400000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
-CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
CONFIG_SPL_TEXT_BASE=0x1800a000
CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
+CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_FSL_LS_MDIO=y
CONFIG_GIC_V3_ITS=y
CONFIG_TARGET_LS1088ARDB=y
CONFIG_SYS_TEXT_BASE=0x80400000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
-CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
CONFIG_SPL_TEXT_BASE=0x1800a000
CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
+CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_FSL_LS_MDIO=y
CONFIG_TARGET_LS1088ARDB=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_SYS_MALLOC_F_LEN=0x6000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
-CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
+CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_FSL_LS_MDIO=y
CONFIG_TARGET_LS1088ARDB=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_SYS_MALLOC_F_LEN=0x6000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
+CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_FSL_LS_MDIO=y
CONFIG_GIC_V3_ITS=y
CONFIG_TARGET_LS2080AQDS=y
CONFIG_SYS_TEXT_BASE=0x30100000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
-CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FSL_LS_PPA=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_GIC_V3_ITS=y
CONFIG_TARGET_LS2080AQDS=y
CONFIG_SYS_TEXT_BASE=0x30100000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FSL_LS_PPA=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_GIC_V3_ITS=y
CONFIG_TARGET_LS2080AQDS=y
CONFIG_SYS_TEXT_BASE=0x80400000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xE0000
-CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
CONFIG_SPL_TEXT_BASE=0x1800a000
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_GIC_V3_ITS=y
CONFIG_TARGET_LS2080AQDS=y
CONFIG_SYS_TEXT_BASE=0x20100000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_AHCI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_GIC_V3_ITS=y
CONFIG_TARGET_LS2080AQDS=y
CONFIG_SYS_TEXT_BASE=0x80400000
+CONFIG_SYS_MALLOC_LEN=0x0220000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x300000
-CONFIG_SYS_MALLOC_LEN=0x0220000
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
CONFIG_SPL_TEXT_BASE=0x1800a000
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_GIC_V3_ITS=y
CONFIG_TARGET_LS2080ARDB=y
CONFIG_SYS_TEXT_BASE=0x30100000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
-CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FSL_LS_PPA=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_GIC_V3_ITS=y
CONFIG_TARGET_LS2080ARDB=y
CONFIG_SYS_TEXT_BASE=0x30100000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FSL_LS_PPA=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_GIC_V3_ITS=y
CONFIG_TARGET_LS2080ARDB=y
CONFIG_SYS_TEXT_BASE=0x80400000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x200000
-CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
CONFIG_SPL_TEXT_BASE=0x1800a000
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x100000
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_GIC_V3_ITS=y
CONFIG_TARGET_LS2081ARDB=y
CONFIG_SYS_TEXT_BASE=0x20100000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2081a-rdb"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FSL_LS_PPA=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_TARGET_LS2080AQDS=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x0220000
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x0220000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_GIC_V3_ITS=y
CONFIG_TARGET_LS2080ARDB=y
CONFIG_SYS_TEXT_BASE=0x20100000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
-CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_GIC_V3_ITS=y
CONFIG_TARGET_LS2080ARDB=y
CONFIG_SYS_TEXT_BASE=0x20100000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_TARGET_LS2080ARDB=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_SYS_MALLOC_F_LEN=0x6000
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
-CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_TARGET_LS2080ARDB=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_SYS_MALLOC_F_LEN=0x6000
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_TARGET_LX2160AQDS=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_SYS_MALLOC_F_LEN=0x6000
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
-CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-qds"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
CONFIG_E1000=y
+CONFIG_MII=y
CONFIG_MDIO_MUX_I2CREG=y
CONFIG_FSL_LS_MDIO=y
CONFIG_NVME=y
CONFIG_RTC_PCF2127=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
+CONFIG_PL01X_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_TARGET_LX2160AQDS=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_SYS_MALLOC_F_LEN=0x6000
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-qds"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
CONFIG_E1000=y
+CONFIG_MII=y
CONFIG_MDIO_MUX_I2CREG=y
CONFIG_FSL_LS_MDIO=y
CONFIG_NVME=y
CONFIG_RTC_PCF2127=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
+CONFIG_PL01X_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_TARGET_LX2160ARDB=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_SYS_MALLOC_F_LEN=0x6000
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
-CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-rdb"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
+CONFIG_MII=y
CONFIG_FSL_LS_MDIO=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_RTC_PCF2127=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
+CONFIG_PL01X_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_NXP_FSPI=y
CONFIG_TARGET_LX2160ARDB=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_SYS_MALLOC_F_LEN=0x6000
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-rdb"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
+CONFIG_MII=y
CONFIG_FSL_LS_MDIO=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_RTC_PCF2127=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
+CONFIG_PL01X_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_NXP_FSPI=y
CONFIG_TARGET_LX2160ARDB=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_SYS_MALLOC_F_LEN=0x6000
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-rdb"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
+CONFIG_MII=y
CONFIG_FSL_LS_MDIO=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_RTC_PCF2127=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
+CONFIG_PL01X_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_NXP_FSPI=y
CONFIG_TARGET_LX2162AQDS=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_SYS_MALLOC_F_LEN=0x6000
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
-CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2162a-qds"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MT35XU=y
CONFIG_SPI_FLASH_SST=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
CONFIG_E1000=y
+CONFIG_MII=y
CONFIG_MDIO_MUX_I2CREG=y
CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_RTC_PCF2127=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
+CONFIG_PL01X_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_TARGET_LX2162AQDS=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_SYS_MALLOC_F_LEN=0x6000
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2162a-qds"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MT35XU=y
CONFIG_SPI_FLASH_SST=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
CONFIG_E1000=y
+CONFIG_MII=y
CONFIG_MDIO_MUX_I2CREG=y
CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_RTC_PCF2127=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
+CONFIG_PL01X_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_TARGET_LX2162AQDS=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_SYS_MALLOC_F_LEN=0x6000
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2162a-qds"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MT35XU=y
CONFIG_SPI_FLASH_SST=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
CONFIG_E1000=y
+CONFIG_MII=y
CONFIG_MDIO_MUX_I2CREG=y
CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_RTC_PCF2127=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
+CONFIG_PL01X_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_ARM=y
+CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_MX5=y
CONFIG_SYS_TEXT_BASE=0x71000000
+CONFIG_SYS_MALLOC_LEN=0xa00000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x100000
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx53-m53menlo"
CONFIG_SPL_TEXT_BASE=0x70008000
CONFIG_SPL=y
CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
CONFIG_ENV_OFFSET_REDUND=0x180000
-# CONFIG_CMD_BMODE is not set
CONFIG_SYS_LOAD_ADDR=0x70800000
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_DM_ETH_PHY=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX5=y
CONFIG_DM_REGULATOR=y
CONFIG_MIPS=y
CONFIG_SYS_TEXT_BASE=0xFFFFFFFFBE000000
+CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_DEFAULT_DEVICE_TREE="mti,malta"
CONFIG_TARGET_MALTA=y
CONFIG_CPU_MIPS64_R2=y
CONFIG_MIPS=y
CONFIG_SYS_TEXT_BASE=0xFFFFFFFFBE000000
+CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_DEFAULT_DEVICE_TREE="mti,malta"
CONFIG_TARGET_MALTA=y
CONFIG_BUILD_TARGET="u-boot-swap.bin"
CONFIG_MIPS=y
CONFIG_SYS_TEXT_BASE=0xBE000000
+CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_DEFAULT_DEVICE_TREE="mti,malta"
CONFIG_TARGET_MALTA=y
CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_MIPS=y
CONFIG_SYS_TEXT_BASE=0xBE000000
+CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_DEFAULT_DEVICE_TREE="mti,malta"
CONFIG_TARGET_MALTA=y
CONFIG_BUILD_TARGET="u-boot-swap.bin"
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-marsboard"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00800000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_MAXBCM=y
CONFIG_ENV_SIZE=0x10000
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
CONFIG_IMX_CONFIG="board/liebherr/mccmon6/mon6_imximage_nor.cfg"
CONFIG_MX6QDL=y
CONFIG_TARGET_MCCMON6=y
-CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DEFAULT_DEVICE_TREE="imx6q-mccmon6"
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_SERIAL=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
CONFIG_IMX_CONFIG="board/liebherr/mccmon6/mon6_imximage_sd.cfg"
CONFIG_MX6QDL=y
CONFIG_TARGET_MCCMON6=y
-CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DEFAULT_DEVICE_TREE="imx6q-mccmon6"
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_MMC=y
CONFIG_ARM=y
CONFIG_ARCH_MX7=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0xa0000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x80000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7d-meerkat96"
CONFIG_TARGET_MEERKAT96=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21F00000
-CONFIG_TARGET_MEESC=y
+CONFIG_SYS_MALLOC_LEN=0x2d000
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_MEESC=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4200
CONFIG_ENV_OFFSET=0x4200
CONFIG_ENV_SECT_SIZE=0x210
-CONFIG_SYS_MALLOC_LEN=0x2d000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek"
CONFIG_SYS_LOAD_ADDR=0x20100000
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_DATAFLASH=y
+CONFIG_MACB=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21F00000
-CONFIG_TARGET_MEESC=y
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_MEESC=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0xC0000
-CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek"
CONFIG_SYS_LOAD_ADDR=0x20100000
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_DATAFLASH=y
+CONFIG_MACB=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
CONFIG_MICROBLAZE=y
CONFIG_SYS_TEXT_BASE=0x29000000
+CONFIG_SYS_MALLOC_LEN=0xc0000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0xc0000
CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic"
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_RISCV=y
+CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x2000
-CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_DEFAULT_DEVICE_TREE="microchip-mpfs-icicle-kit"
CONFIG_TARGET_MICROCHIP_ICICLE=y
CONFIG_ARCH_RV64I=y
CONFIG_MIPS=y
CONFIG_SYS_TEXT_BASE=0x40000000
+CONFIG_SYS_MALLOC_LEN=0x1f0000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fc00000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_SYS_MALLOC_LEN=0x1f0000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="jr2_pcb110"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_MIPS=y
CONFIG_SYS_TEXT_BASE=0x40000000
+CONFIG_SYS_MALLOC_LEN=0x1f0000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x87c00000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_SYS_MALLOC_LEN=0x1f0000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="luton_pcb091"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_MIPS=y
CONFIG_SYS_TEXT_BASE=0x40000000
+CONFIG_SYS_MALLOC_LEN=0x1f0000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fc00000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_SYS_MALLOC_LEN=0x1f0000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ocelot_pcb123"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_MIPS=y
CONFIG_SYS_TEXT_BASE=0x40000000
+CONFIG_SYS_MALLOC_LEN=0x1f0000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x87c00000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_SYS_MALLOC_LEN=0x1f0000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="serval_pcb106"
CONFIG_ENV_OFFSET_REDUND=0x140000
CONFIG_MIPS=y
CONFIG_SYS_TEXT_BASE=0x40000000
+CONFIG_SYS_MALLOC_LEN=0x1f0000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fc00000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_SYS_MALLOC_LEN=0x1f0000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="servalt_pcb116"
CONFIG_ENV_OFFSET_REDUND=0x140000
CONFIG_MIPS=y
CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x30000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="mediatek,mt7620-mt7530-rfb"
CONFIG_SPL_SERIAL=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000
CONFIG_MIPS=y
CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x30000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="mediatek,mt7620-rfb"
CONFIG_SPL_SERIAL=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MTK_SNOR=y
-CONFIG_SYSRESET_WATCHDOG=y
-CONFIG_WDT_MTK=y
CONFIG_LZO=y
CONFIG_HEXDUMP=y
CONFIG_MIPS=y
CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x30000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="mediatek,mt7628-rfb"
CONFIG_SPL_SERIAL=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000
CONFIG_POSITION_INDEPENDENT=y
CONFIG_ARCH_MEDIATEK=y
CONFIG_SYS_TEXT_BASE=0x44e00000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x1000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="mt8512-bm1-emmc"
CONFIG_TARGET_MT8512=y
CONFIG_WDT=y
CONFIG_WDT_MTK=y
# CONFIG_SHA256 is not set
-# CONFIG_EFI_LOADER is not set
CONFIG_POSITION_INDEPENDENT=y
CONFIG_ARCH_MEDIATEK=y
CONFIG_SYS_TEXT_BASE=0x40008000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x1000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="mt8518-ap1-emmc"
CONFIG_TARGET_MT8518=y
CONFIG_SYS_LOAD_ADDR=0x41000000
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
+CONFIG_E1000=y
CONFIG_MVPP2=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_CLK_MVEBU=y
# CONFIG_MVEBU_GPIO is not set
CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MV=y
CONFIG_MISC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
+CONFIG_E1000=y
CONFIG_MVPP2=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
+CONFIG_E1000=y
CONFIG_MVPP2=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_CLK=y
CONFIG_CLK_MVEBU=y
CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MV=y
CONFIG_MISC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
+CONFIG_E1000=y
CONFIG_MVPP2=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
+CONFIG_E1000=y
CONFIG_MVPP2=y
CONFIG_NVME=y
CONFIG_PCI=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
# CONFIG_SPL_FRAMEWORK is not set
+CONFIG_SPL_NO_CPU_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
# CONFIG_SPL_FRAMEWORK is not set
+CONFIG_SPL_NO_CPU_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_DM=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
# CONFIG_SPL_FRAMEWORK is not set
+CONFIG_SPL_NO_CPU_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
# CONFIG_SPL_FRAMEWORK is not set
+CONFIG_SPL_NO_CPU_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_DM=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
# CONFIG_SPL_FRAMEWORK is not set
+CONFIG_SPL_NO_CPU_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
# CONFIG_SPL_FRAMEWORK is not set
+CONFIG_SPL_NO_CPU_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
CONFIG_ARM=y
CONFIG_ARCH_MX5=y
CONFIG_SYS_TEXT_BASE=0x97800000
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_TARGET_MX51EVK=y
-CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx51-babbage"
# CONFIG_CMD_BMODE is not set
CONFIG_ARM=y
CONFIG_ARCH_MX5=y
CONFIG_SYS_TEXT_BASE=0x77800000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x60000
CONFIG_TARGET_MX53CX9020=y
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx53-cx9020"
# CONFIG_CMD_BMODE is not set
CONFIG_ARM=y
CONFIG_ARCH_MX5=y
CONFIG_SYS_TEXT_BASE=0x77800000
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx53-qsb"
# CONFIG_CMD_BMODE is not set
CONFIG_ARM=y
CONFIG_ARCH_MX5=y
CONFIG_SYS_TEXT_BASE=0x77800000
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2800
CONFIG_TARGET_MX53PPD=y
-CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx53-ppd"
CONFIG_BOOTCOUNT_BOOTLIMIT=10
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_OFFSET=0xFE000
CONFIG_MX6QDL=y
CONFIG_TARGET_MX6CUBOXI=y
-CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-hummingboard2-emmc-som-v15"
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_MX6QDL=y
CONFIG_MX6_DDRCAL=y
CONFIG_TARGET_MX6MEMCAL=y
-CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x10000000
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DDR_MB=1024
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabrelite"
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_USB_ETH_CDC=y
CONFIG_DM_VIDEO=y
CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_I2C_EDID=y
CONFIG_VIDEO_IPUV3=y
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_LEN=0xa00000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabreauto"
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_LEN=0xa00000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabresd"
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_SYS_MALLOC_LEN=0x300000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x80000
CONFIG_MX6SL=y
CONFIG_TARGET_MX6SLEVK=y
-CONFIG_SYS_MALLOC_LEN=0x300000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6sl-evk"
# CONFIG_CMD_BMODE is not set
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_SYS_MALLOC_LEN=0x300000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_MX6SL=y
CONFIG_TARGET_MX6SLEVK=y
-CONFIG_SYS_MALLOC_LEN=0x300000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6sl-evk"
# CONFIG_CMD_BMODE is not set
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_SYS_MALLOC_LEN=0x300000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0x300000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6sl-evk"
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x88000000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_MX6SLL=y
CONFIG_TARGET_MX6SLLEVK=y
-CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6sll-evk"
# CONFIG_CMD_BMODE is not set
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x88000000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_MX6SLL=y
CONFIG_TARGET_MX6SLLEVK=y
-CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6sll-evk"
CONFIG_USE_IMXIMG_PLUGIN=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_SYS_MALLOC_LEN=0x300000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x80000
CONFIG_MX6SX=y
CONFIG_TARGET_MX6SXSABREAUTO=y
-CONFIG_SYS_MALLOC_LEN=0x300000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sabreauto"
# CONFIG_CMD_BMODE is not set
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_SYS_MALLOC_LEN=0x300000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xE0000
CONFIG_MX6SX=y
CONFIG_TARGET_MX6SXSABRESD=y
-CONFIG_SYS_MALLOC_LEN=0x300000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sdb"
# CONFIG_CMD_BMODE is not set
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PCI=y
CONFIG_PINCTRL=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_MX6UL_14X14_EVK=y
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-evk"
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_MX6UL_9X9_EVK=y
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-9x9-evk"
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x88000000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_MX6ULL=y
CONFIG_TARGET_MX6ULL_14X14_EVK=y
-CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-evk"
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x88000000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_MX6ULL=y
CONFIG_TARGET_MX6ULL_14X14_EVK=y
-CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-evk"
CONFIG_USE_IMXIMG_PLUGIN=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x88000000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_MX6ULL=y
CONFIG_TARGET_MX6ULL_14X14_EVK=y
-CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ulz-14x14-evk"
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_ARM=y
CONFIG_ARCH_MX7=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0xa0000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb"
CONFIG_TARGET_MX7DSABRESD=y
CONFIG_ARM=y
CONFIG_ARCH_MX7=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0xa0000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb-qspi"
CONFIG_TARGET_MX7DSABRESD=y
CONFIG_ARM=y
CONFIG_ARCH_MX7ULP=y
CONFIG_SYS_TEXT_BASE=0x67800000
+CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
-CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-com"
CONFIG_LDO_ENABLED_MODE=y
CONFIG_TARGET_MX7ULP_COM=y
CONFIG_SYS_LOAD_ADDR=0x60800000
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="if run loadimage; then run mmcboot; fi"
CONFIG_DEFAULT_FDT_FILE="imx7ulp-com"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_ARM=y
CONFIG_ARCH_MX7ULP=y
CONFIG_SYS_TEXT_BASE=0x67800000
+CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x60000000
CONFIG_SYS_MEMTEST_END=0x9e000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
-CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk"
CONFIG_TARGET_MX7ULP_EVK=y
CONFIG_ARM=y
CONFIG_ARCH_MX7ULP=y
CONFIG_SYS_TEXT_BASE=0x67800000
+CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x60000000
CONFIG_SYS_MEMTEST_END=0x9e000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
-CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk"
CONFIG_TARGET_MX7ULP_EVK=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=8
CONFIG_ENV_SIZE=0x4000
CONFIG_MX6ULL=y
CONFIG_TARGET_MYS_6ULX=y
-CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DEFAULT_DEVICE_TREE="imx6ull-myir-mys-6ulx-eval"
CONFIG_SPL_TEXT_BASE=0x908000
CONFIG_SPL_MMC=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x10000000
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DDR_MB=2048
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-nitrogen6x"
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_USB_ETH_CDC=y
CONFIG_DM_VIDEO=y
CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_I2C_EDID=y
CONFIG_VIDEO_IPUV3=y
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x10000000
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DDR_MB=1024
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-nitrogen6x"
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_USB_ETH_CDC=y
CONFIG_DM_VIDEO=y
CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_I2C_EDID=y
CONFIG_VIDEO_IPUV3=y
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x10000000
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DDR_MB=2048
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-nitrogen6x"
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_USB_ETH_CDC=y
CONFIG_DM_VIDEO=y
CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_I2C_EDID=y
CONFIG_VIDEO_IPUV3=y
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x10000000
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DDR_MB=1024
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-nitrogen6x"
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_USB_ETH_CDC=y
CONFIG_DM_VIDEO=y
CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_I2C_EDID=y
CONFIG_VIDEO_IPUV3=y
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x10000000
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DDR_MB=1024
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-nitrogen6x"
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_USB_ETH_CDC=y
CONFIG_DM_VIDEO=y
CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_I2C_EDID=y
CONFIG_VIDEO_IPUV3=y
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x10000000
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DDR_MB=512
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-nitrogen6x"
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_USB_ETH_CDC=y
CONFIG_DM_VIDEO=y
CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_I2C_EDID=y
CONFIG_VIDEO_IPUV3=y
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_STATIC_MACH_TYPE=y
CONFIG_MACH_TYPE=1955
CONFIG_SYS_TEXT_BASE=0x80008000
-CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MALLOC_LEN=0xc0000
+CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_NOKIA_RX51=y
CONFIG_OPTIMIZE_INLINING=y
CONFIG_LTO=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DEFAULT_DEVICE_TREE="imx6q-novena"
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_MMC=y
CONFIG_ARM=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x81000100
+CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFE000
-CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_DEFAULT_DEVICE_TREE="tegra124-nyan-big"
CONFIG_SPL_TEXT_BASE=0x80108000
CONFIG_BOOTSTAGE_STASH_ADDR=0x83000000
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_MX6ULL=y
CONFIG_TARGET_O4_IMX6ULL_NANO=y
-CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DM_GPIO=y
CONFIG_MT41K256M16HA_125E=y
CONFIG_IMX_MODULE_FUSE=y
CONFIG_MIPS=y
CONFIG_SYS_TEXT_BASE=0xffffffff80000000
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x2000
-CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DEBUG_UART_BASE=0x8001180000000800
CONFIG_DEBUG_UART_CLOCK=1200000000
CONFIG_ARCH_OCTEON=y
CONFIG_MIPS=y
CONFIG_SYS_TEXT_BASE=0xffffffff80000000
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xe000
CONFIG_ENV_SECT_SIZE=0x100
-CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DEBUG_UART_BASE=0x8001180000000800
CONFIG_DEBUG_UART_CLOCK=800000000
CONFIG_ARCH_OCTEON=y
# CONFIG_ARM64_SUPPORT_AARCH32 is not set
CONFIG_ARCH_OCTEONTX2=y
CONFIG_SYS_TEXT_BASE=0x04000000
+CONFIG_SYS_MALLOC_LEN=0x4008000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x04000000
CONFIG_ENV_OFFSET=0xF00000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_TARGET_OCTEONTX2_95XX=y
-CONFIG_SYS_MALLOC_LEN=0x4008000
CONFIG_DM_GPIO=y
CONFIG_DEBUG_UART_BASE=0x87e028000000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_BOOTARGS="console=ttyAMA0,115200n8 earlycon=pl011,0x87e028000000 maxcpus=6 rootwait rw root=/dev/mmcblk0p2 coherent_pool=16M"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Marvell> "
# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set
CONFIG_EFI_PARTITION=y
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_OF_BOARD=y
+CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USE_ENV_SPI_BUS=y
CONFIG_ENV_SPI_BUS=0
CONFIG_TFTP_TSIZE=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_OCTEONTX=y
CONFIG_MTD=y
# CONFIG_ARM64_SUPPORT_AARCH32 is not set
CONFIG_ARCH_OCTEONTX2=y
CONFIG_SYS_TEXT_BASE=0x04000000
+CONFIG_SYS_MALLOC_LEN=0x4008000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x8000
CONFIG_ENV_OFFSET=0xF00000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_TARGET_OCTEONTX2_96XX=y
-CONFIG_SYS_MALLOC_LEN=0x4008000
CONFIG_DM_GPIO=y
CONFIG_DEBUG_UART_BASE=0x87e028000000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_BOOTARGS="console=ttyAMA0,115200n8 earlycon=pl011,0x87e028000000 maxcpus=24 rootwait rw root=/dev/mmcblk0p2 coherent_pool=16M"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Marvell> "
# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set
CONFIG_EFI_PARTITION=y
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_OF_BOARD=y
+CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USE_ENV_SPI_BUS=y
CONFIG_ENV_SPI_BUS=0
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_OCTEONTX=y
CONFIG_MTD=y
# CONFIG_ARM64_SUPPORT_AARCH32 is not set
CONFIG_ARCH_OCTEONTX=y
CONFIG_SYS_TEXT_BASE=0x2800000
+CONFIG_SYS_MALLOC_LEN=0x4008000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x2800000
CONFIG_ENV_OFFSET=0xF00000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_TARGET_OCTEONTX_81XX=y
-CONFIG_SYS_MALLOC_LEN=0x4008000
CONFIG_DM_GPIO=y
CONFIG_DEBUG_UART_BASE=0x87e028000000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_EFI_PARTITION=y
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_OF_BOARD=y
+CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USE_ENV_SPI_BUS=y
CONFIG_ENV_SPI_BUS=0
CONFIG_AHCI_PCI=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_OCTEONTX=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_ARM64_SUPPORT_AARCH32 is not set
CONFIG_ARCH_OCTEONTX=y
CONFIG_SYS_TEXT_BASE=0x2800000
+CONFIG_SYS_MALLOC_LEN=0x4008000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x8000
CONFIG_ENV_OFFSET=0xF00000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_TARGET_OCTEONTX_83XX=y
-CONFIG_SYS_MALLOC_LEN=0x4008000
CONFIG_DM_GPIO=y
CONFIG_DEBUG_UART_BASE=0x87e028000000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_EFI_PARTITION=y
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_OF_BOARD=y
+CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USE_ENV_SPI_BUS=y
CONFIG_ENV_SPI_BUS=0
CONFIG_AHCI_PCI=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_OCTEONTX=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x4000
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x43E00000
+CONFIG_SYS_MALLOC_LEN=0x5004000
CONFIG_ARCH_EXYNOS5=y
CONFIG_NR_DRAM_BANKS=8
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x310000
-CONFIG_SYS_MALLOC_LEN=0x5004000
CONFIG_DEFAULT_DEVICE_TREE="exynos5422-odroidxu3"
CONFIG_IDENT_STRING=" for ODROID-XU3/XU4/HC1/HC2"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x43e00000
+CONFIG_SYS_MALLOC_LEN=0x5004000
CONFIG_ARCH_EXYNOS4=y
CONFIG_TARGET_ODROID=y
CONFIG_NR_DRAM_BANKS=8
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x140000
-CONFIG_SYS_MALLOC_LEN=0x5004000
CONFIG_DEFAULT_DEVICE_TREE="exynos4412-odroid"
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80100000
+CONFIG_SYS_MALLOC_F_LEN=0x3000
CONFIG_TI_COMMON_CMD_OPTIONS=y
# CONFIG_SPL_GPIO is not set
-CONFIG_SYS_MALLOC_F_LEN=0x3000
CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="logicpd-torpedo-35xx-devkit"
CONFIG_SPL_TEXT_BASE=0x40200000
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80100000
+CONFIG_SYS_MALLOC_F_LEN=0x3000
CONFIG_TI_COMMON_CMD_OPTIONS=y
# CONFIG_SPL_GPIO is not set
-CONFIG_SYS_MALLOC_F_LEN=0x3000
CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="logicpd-som-lv-35xx-devkit"
CONFIG_SPL_TEXT_BASE=0x40200000
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80100000
+CONFIG_SYS_MALLOC_F_LEN=0x3000
CONFIG_TI_COMMON_CMD_OPTIONS=y
# CONFIG_SPL_GPIO is not set
-CONFIG_SYS_MALLOC_F_LEN=0x3000
CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="logicpd-torpedo-37xx-devkit"
CONFIG_SPL_TEXT_BASE=0x40200000
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80100000
+CONFIG_SYS_MALLOC_F_LEN=0x3000
CONFIG_TI_COMMON_CMD_OPTIONS=y
# CONFIG_SPL_GPIO is not set
-CONFIG_SYS_MALLOC_F_LEN=0x3000
CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="logicpd-som-lv-37xx-devkit"
CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_DAVINCI=y
CONFIG_SYS_TEXT_BASE=0xc1080000
+CONFIG_SYS_MALLOC_LEN=0x110000
+CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_TARGET_OMAPL138_LCDK=y
CONFIG_SYS_DA850_PLL0_POSTDIV=0
CONFIG_SYS_DA850_PLL1_PLLDIV3=0x8003
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x0
-CONFIG_SYS_MALLOC_LEN=0x110000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="da850-lcdk"
CONFIG_SPL_TEXT_BASE=0x80000000
CONFIG_RISCV=y
CONFIG_SYS_TEXT_BASE=0x80200000
-CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MALLOC_LEN=0x10000000
+CONFIG_NR_DRAM_BANKS=1
CONFIG_DEFAULT_DEVICE_TREE="openpiton-riscv64"
CONFIG_TARGET_OPENPITON_RISCV64=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV=y
CONFIG_SYS_TEXT_BASE=0x80000000
-CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MALLOC_LEN=0x10000000
+CONFIG_NR_DRAM_BANKS=1
CONFIG_DEFAULT_DEVICE_TREE="openpiton-riscv64"
CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
CONFIG_SPL=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_OFFSET=0x100000
CONFIG_MX6UL=y
CONFIG_TARGET_OPOS6ULDEV=y
-CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-opos6uldev"
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_MMC=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x43E00000
+CONFIG_SYS_MALLOC_LEN=0x5004000
CONFIG_ARCH_EXYNOS4=y
CONFIG_TARGET_ORIGEN=y
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x4200
-CONFIG_SYS_MALLOC_LEN=0x5004000
CONFIG_DEFAULT_DEVICE_TREE="exynos4210-origen"
CONFIG_SPL_TEXT_BASE=0x02021410
CONFIG_SPL=y
CONFIG_ARM=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80080000
+CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFE000
-CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_DEFAULT_DEVICE_TREE="tegra210-p2371-0000"
CONFIG_TEGRA210=y
CONFIG_SYS_LOAD_ADDR=0x80080000
CONFIG_ARM=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80080000
+CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFE000
-CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_DEFAULT_DEVICE_TREE="tegra210-p2371-2180"
CONFIG_TEGRA210=y
CONFIG_TARGET_P2371_2180=y
CONFIG_ARM=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80080000
+CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFE000
-CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_DEFAULT_DEVICE_TREE="tegra210-p2571"
CONFIG_TEGRA210=y
CONFIG_TARGET_P2571=y
CONFIG_ARM=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80080000
+CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFE000
CONFIG_ENV_SECT_SIZE=0x1000
-CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_DEFAULT_DEVICE_TREE="tegra210-p3450-0000"
CONFIG_TEGRA210=y
CONFIG_TARGET_P3450_0000=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_VF610=y
CONFIG_SYS_TEXT_BASE=0x3f401000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x80010000
CONFIG_SYS_MEMTEST_END=0x87c00000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xA0000
-CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="vf610-pcm052"
CONFIG_ENV_OFFSET_REDUND=0xC0000
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_MX6Q=y
CONFIG_MX6_OCRAM_256KB=y
CONFIG_TARGET_PCM058=y
-CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-phytec-mira-rdk-nand"
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x23E00000
+CONFIG_SYS_MALLOC_LEN=0x5004000
CONFIG_ARCH_EXYNOS5=y
CONFIG_TARGET_PEACH_PI=y
CONFIG_NR_DRAM_BANKS=7
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x3FC000
CONFIG_ENV_SECT_SIZE=0x4000
-CONFIG_SYS_MALLOC_LEN=0x5004000
CONFIG_DEFAULT_DEVICE_TREE="exynos5800-peach-pi"
CONFIG_SPL_TEXT_BASE=0x02024410
CONFIG_SPL=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x23E00000
+CONFIG_SYS_MALLOC_LEN=0x5004000
CONFIG_ARCH_EXYNOS5=y
CONFIG_TARGET_PEACH_PIT=y
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x3FC000
CONFIG_ENV_SECT_SIZE=0x4000
-CONFIG_SYS_MALLOC_LEN=0x5004000
CONFIG_DEFAULT_DEVICE_TREE="exynos5420-peach-pit"
CONFIG_SPL_TEXT_BASE=0x02024410
CONFIG_SPL=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_TARGET_PG_WCOM_EXPU1=y
CONFIG_SYS_TEXT_BASE=0x60100000
+CONFIG_SYS_MALLOC_LEN=0x1004000
CONFIG_NR_DRAM_BANKS=1
CONFIG_KM_DEF_NETDEV="eth2"
CONFIG_KM_COMMON_ETH_INIT=y
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0x1004000
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-pg-wcom-expu1"
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_BOOTCOUNT_ADDR=0x70000020
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_SYS_QE_FW_ADDR=0x60020000
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_TARGET_PG_WCOM_SELI8=y
CONFIG_SYS_TEXT_BASE=0x60100000
+CONFIG_SYS_MALLOC_LEN=0x1004000
CONFIG_NR_DRAM_BANKS=1
CONFIG_KM_DEF_NETDEV="eth2"
CONFIG_KM_COMMON_ETH_INIT=y
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0x1004000
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-pg-wcom-seli8"
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_BOOTCOUNT_ADDR=0x70000020
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_SYS_QE_FW_ADDR=0x60020000
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_ARM=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x3C0000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="phycore-imx8mm"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
-CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DEFAULT_FDT_FILE="oftree"
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
+CONFIG_SPL_SPI_FLASH_MTD=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_SYS_EEPROM_SIZE=4096
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
+CONFIG_CMD_CLK=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_SF_TEST=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
-CONFIG_FSL_ESDHC_IMX=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=3
+CONFIG_SF_DEFAULT_MODE=0x0
+CONFIG_SF_DEFAULT_SPEED=80000000
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_MTD=y
CONFIG_PHYLIB=y
CONFIG_PHY_TI_DP83867=y
CONFIG_DM_ETH=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_PSCI=y
CONFIG_ARM=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x3C0000
CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mp-phyboard-pollux-rdk"
CONFIG_SPL_TEXT_BASE=0x920000
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
-CONFIG_FSL_ESDHC_IMX=y
+CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_TI_DP83867=y
CONFIG_DM_ETH=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=8
CONFIG_ENV_SIZE=0x4000
CONFIG_MX6UL=y
CONFIG_TARGET_PCL063=y
-CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-phytec-segin-ff-rdk-nand"
CONFIG_SPL_TEXT_BASE=0x00909000
CONFIG_SPL_MMC=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=8
CONFIG_ENV_SIZE=0x4000
CONFIG_MX6ULL=y
CONFIG_TARGET_PCL063_ULL=y
-CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DEFAULT_DEVICE_TREE="imx6ull-phytec-segin-ff-rdk-emmc"
CONFIG_SPL_TEXT_BASE=0x908000
CONFIG_SPL_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_I2C_GPIO=y
CONFIG_SYS_I2C_MXC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_PHYLIB=y
CONFIG_MIPS=y
CONFIG_SYS_TEXT_BASE=0x9D004000
+CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_SYS_MALLOC_F_LEN=0x600
CONFIG_SYS_MEMTEST_START=0x88000000
CONFIG_SYS_MEMTEST_END=0x88080000
CONFIG_ENV_SIZE=0x4000
-CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="pic32mzda_sk"
CONFIG_MACH_PIC32=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_SYS_MALLOC_LEN=0x2300000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_OFFSET=0xC0000
CONFIG_MX6UL=y
CONFIG_TARGET_PICO_IMX6UL=y
-CONFIG_SYS_MALLOC_LEN=0x2300000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-pico-pi"
CONFIG_SPL_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_ARM=y
CONFIG_ARCH_MX7=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi"
CONFIG_TARGET_PICO_IMX7D=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_SYS_MALLOC_LEN=0x2300000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_OFFSET=0xC0000
CONFIG_MX6UL=y
CONFIG_TARGET_PICO_IMX6UL=y
-CONFIG_SYS_MALLOC_LEN=0x2300000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-pico-hobbit"
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_ARM=y
CONFIG_ARCH_MX7=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi"
CONFIG_TARGET_PICO_IMX7D=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_LEN=0x2300000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_OFFSET=0xC0000
CONFIG_MX6QDL=y
CONFIG_TARGET_PICO_IMX6=y
-CONFIG_SYS_MALLOC_LEN=0x2300000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-pico"
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_FASTBOOT_BUF_SIZE=0x10000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
CONFIG_RGMII=y
+CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_MXC_UART=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_SYS_MALLOC_LEN=0x2300000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_OFFSET=0xC0000
CONFIG_MX6UL=y
CONFIG_TARGET_PICO_IMX6UL=y
-CONFIG_SYS_MALLOC_LEN=0x2300000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-pico-hobbit"
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_ARM=y
CONFIG_ARCH_MX7=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi"
CONFIG_TARGET_PICO_IMX7D=y
CONFIG_ARM=y
CONFIG_ARCH_MX7=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi"
CONFIG_TARGET_PICO_IMX7D=y
CONFIG_ARM=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x600000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0x600000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mq-pico-pi"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_TARGET_PICO_IMX8MQ=y
+CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
+CONFIG_IMX_BOOTAUX=y
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_CMD_EXPORTENV is not set
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
CONFIG_SPL_POWER_LEGACY=y
CONFIG_ARM=y
CONFIG_ARCH_MX7=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi"
CONFIG_TARGET_PICO_IMX7D=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_SYS_MALLOC_LEN=0x2300000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_OFFSET=0xC0000
CONFIG_MX6UL=y
CONFIG_TARGET_PICO_IMX6UL=y
-CONFIG_SYS_MALLOC_LEN=0x2300000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-pico-pi"
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_ARM=y
CONFIG_ARCH_MX7=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_SYS_I2C_MXC_I2C4=y
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi"
CONFIG_TARGET_PICO_IMX7D=y
CONFIG_R_I2C_ENABLE=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
-CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_PWM=y
CONFIG_PWM_SUNXI=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0
-CONFIG_TARGET_PM9261=y
+CONFIG_SYS_MALLOC_LEN=0x50000
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_PM9261=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x50000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek"
CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0
-CONFIG_TARGET_PM9263=y
+CONFIG_SYS_MALLOC_LEN=0x50000
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_PM9263=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x50000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek"
CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x73f00000
-CONFIG_TARGET_PM9G45=y
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_PM9G45=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9m10g45ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_ARM=y
CONFIG_TARGET_POPLAR=y
CONFIG_SYS_TEXT_BASE=0x37000000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x1F0000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="hi3798cv200-poplar"
CONFIG_IDENT_STRING="poplar"
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_TEXT_BASE=0x50000000
+CONFIG_SYS_MALLOC_LEN=0x100000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r8a7791-porter-u-boot"
CONFIG_SPL_TEXT_BASE=0xe6300000
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEFAULT_DEVICE_TREE="px30-px30-core-ctouch2"
CONFIG_SPL_TEXT_BASE=0x00000000
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEFAULT_DEVICE_TREE="px30-px30-core-edimm2.2"
CONFIG_SPL_TEXT_BASE=0x00000000
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80100000
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
-CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-pxm50"
CONFIG_AM33XX=y
CONFIG_RISCV=y
+CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_RISCV=y
+CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_RISCV_SMODE=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_RISCV=y
+CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_DEFAULT_DEVICE_TREE="qemu-virt"
CONFIG_SPL=y
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_RISCV=y
+CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_ARCH_RV64I=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_RISCV=y
+CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
CONFIG_RISCV=y
+CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_DEFAULT_DEVICE_TREE="qemu-virt"
CONFIG_SPL=y
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_ARM=y
CONFIG_POSITION_INDEPENDENT=y
CONFIG_ARCH_QEMU=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x40200000
CONFIG_SCSI_AHCI=y
CONFIG_AHCI_PCI=y
CONFIG_DFU_TFTP=y
-CONFIG_DFU_RAM=y
CONFIG_DFU_MTD=y
+CONFIG_DFU_RAM=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_DM_SCSI=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_PSCI=y
+CONFIG_TPM2_MMIO=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_PCI=y
+CONFIG_TPM=y
CONFIG_ARM=y
CONFIG_ARM_SMCCC=y
CONFIG_ARCH_QEMU=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_TARGET_QEMU_ARM_32BIT=y
CONFIG_ARMV7_LPAE=y
CONFIG_AHCI=y
CONFIG_SCSI_AHCI=y
CONFIG_AHCI_PCI=y
CONFIG_DFU_TFTP=y
-CONFIG_DFU_RAM=y
CONFIG_DFU_MTD=y
+CONFIG_DFU_RAM=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_DM_SCSI=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_PSCI=y
+CONFIG_TPM2_MMIO=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_PCI=y
+CONFIG_TPM=y
CONFIG_SH=y
CONFIG_SYS_TEXT_BASE=0x8FE00000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="sh7751-r2dplus"
CONFIG_TARGET_R2DPLUS=y
CONFIG_SYS_LOAD_ADDR=0x8e000000
CONFIG_BOOTARGS="console=ttySC0,115200"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="pci enum"
+CONFIG_DISPLAY_BOARDINFO=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_DM=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_RMOBILE=y
-CONFIG_SYS_TEXT_BASE=0x50000000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_ENV_OFFSET=0x0
-CONFIG_SYS_MALLOC_LEN=0x4000000
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="r8a774b1-beacon-rzg2n-kit"
-CONFIG_RCAR_GEN3=y
-CONFIG_TARGET_BEACON_RZG2N=y
-# CONFIG_SPL is not set
-CONFIG_LTO=y
-CONFIG_SYS_LOAD_ADDR=0x58000000
-CONFIG_FIT=y
-CONFIG_SUPPORT_RAW_INITRD=y
-# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
-CONFIG_DEFAULT_FDT_FILE="r8a774b1-beacon-rzg2n-kit.dtb"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_MTD=y
-CONFIG_CMD_PART=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_MMC_ENV_DEV=1
-CONFIG_SYS_MMC_ENV_PART=2
-CONFIG_VERSION_VARIABLE=y
-CONFIG_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_CLK=y
-CONFIG_CLK_RENESAS=y
-CONFIG_RCAR_GPIO=y
-CONFIG_DM_PCA953X=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_RCAR_I2C=y
-CONFIG_SYS_I2C_RCAR_IIC=y
-CONFIG_MMC_IO_VOLTAGE=y
-CONFIG_MMC_UHS_SUPPORT=y
-CONFIG_MMC_HS200_SUPPORT=y
-CONFIG_RENESAS_SDHI=y
-CONFIG_MTD=y
-CONFIG_DM_MTD=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_BITBANGMII=y
-CONFIG_PHY_REALTEK=y
-CONFIG_DM_ETH=y
-CONFIG_RENESAS_RAVB=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SPECIFY_CONSOLE_INDEX=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_RENESAS_RPC_SPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_GENERIC=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT_OVERLAY=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_RMOBILE=y
-CONFIG_SYS_TEXT_BASE=0x50000000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_ENV_OFFSET=0x0
-CONFIG_SYS_MALLOC_LEN=0x4000000
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="r8a774e1-beacon-rzg2h-kit"
-CONFIG_RCAR_GEN3=y
-CONFIG_TARGET_BEACON_RZG2H=y
-# CONFIG_SPL is not set
-CONFIG_LTO=y
-CONFIG_SYS_LOAD_ADDR=0x58000000
-CONFIG_FIT=y
-CONFIG_SUPPORT_RAW_INITRD=y
-# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
-CONFIG_DEFAULT_FDT_FILE="r8a774e1-beacon-rzg2h-kit.dtb"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_MTD=y
-CONFIG_CMD_PART=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_MMC_ENV_DEV=1
-CONFIG_SYS_MMC_ENV_PART=2
-CONFIG_VERSION_VARIABLE=y
-CONFIG_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_CLK=y
-CONFIG_CLK_RENESAS=y
-CONFIG_RCAR_GPIO=y
-CONFIG_DM_PCA953X=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_RCAR_I2C=y
-CONFIG_SYS_I2C_RCAR_IIC=y
-CONFIG_MMC_IO_VOLTAGE=y
-CONFIG_MMC_UHS_SUPPORT=y
-CONFIG_MMC_HS200_SUPPORT=y
-CONFIG_RENESAS_SDHI=y
-CONFIG_MTD=y
-CONFIG_DM_MTD=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_BITBANGMII=y
-CONFIG_PHY_REALTEK=y
-CONFIG_DM_ETH=y
-CONFIG_RENESAS_RAVB=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SPECIFY_CONSOLE_INDEX=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_RENESAS_RPC_SPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_GENERIC=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_TEXT_BASE=0x50000000
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x700000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r8a77970-eagle-u-boot"
CONFIG_SPL_TEXT_BASE=0xe6318000
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_TEXT_BASE=0x50000000
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x700000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r8a77980-condor-u-boot"
CONFIG_SPL_TEXT_BASE=0xe6318000
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_TEXT_BASE=0x50000000
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xFFFE0000
-CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r8a77990-ebisu-u-boot"
CONFIG_SPL_TEXT_BASE=0xe6318000
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_TEXT_BASE=0x50000000
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xFFFE0000
-CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r8a77995-draak-u-boot"
CONFIG_SPL_TEXT_BASE=0xe6318000
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_TEXT_BASE=0x50000000
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0xC00000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r8a779a0-falcon-u-boot"
CONFIG_SPL_TEXT_BASE=0xe6338000
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_BITBANGMII=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80100000
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
-CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
CONFIG_AM33XX=y
CONFIG_ARM=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_RMOBILE=y
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xFFFE0000
-CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r8a77950-salvator-x-u-boot"
CONFIG_SPL_TEXT_BASE=0xe6338000
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT_OVERLAY=y
+# CONFIG_EFI_UNICODE_CAPITALIZATION is not set
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_TEXT_BASE=0x50000000
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xFFFE0000
-CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r8a77950-ulcb-u-boot"
CONFIG_SPL_TEXT_BASE=0xe6338000
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-riotboard"
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00600000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rk3308-roc-cc"
CONFIG_ROCKCHIP_RK3308=y
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_BCM283X=y
CONFIG_SYS_TEXT_BASE=0x00008000
-CONFIG_TARGET_RPI_3_32B=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_RPI_3_32B=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4000
CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b"
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_BCM283X=y
CONFIG_SYS_TEXT_BASE=0x00080000
-CONFIG_TARGET_RPI_3=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_RPI_3=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4000
CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b-plus"
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_BCM283X=y
CONFIG_SYS_TEXT_BASE=0x00080000
-CONFIG_TARGET_RPI_3=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_RPI_3=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4000
CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b"
CONFIG_ARM=y
CONFIG_ARCH_BCM283X=y
CONFIG_SYS_TEXT_BASE=0x00008000
-CONFIG_TARGET_RPI_4_32B=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_RPI_4_32B=y
CONFIG_ENV_SIZE=0x4000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_ARM=y
CONFIG_ARCH_BCM283X=y
CONFIG_SYS_TEXT_BASE=0x00080000
-CONFIG_TARGET_RPI_4=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_RPI_4=y
CONFIG_ENV_SIZE=0x4000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_ARM=y
CONFIG_ARCH_BCM283X=y
CONFIG_SYS_TEXT_BASE=0x00080000
-CONFIG_TARGET_RPI_ARM64=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_RPI_ARM64=y
CONFIG_ENV_SIZE=0x4000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80100000
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
-CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-rut"
CONFIG_AM33XX=y
CONFIG_ARM=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_TEXT_BASE=0x50000000
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_OFFSET=0x0
-CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r8a774a1-beacon-rzg2m-kit"
CONFIG_RCAR_GEN3=y
CONFIG_SUPPORT_RAW_INITRD=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_DEFAULT_FDT_FILE="r8a774a1-beacon-rzg2m-kit.dtb"
+# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
+CONFIG_OF_LIST="r8a774a1-beacon-rzg2m-kit r8a774b1-beacon-rzg2n-kit r8a774e1-beacon-rzg2h-kit"
+CONFIG_MULTI_DTB_FIT_LZO=y
+CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_NEXELL=y
CONFIG_SYS_TEXT_BASE=0x74C00000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x71000000
CONFIG_SYS_MEMTEST_END=0xb0000000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x2E0200
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="s5p4418-nanopi2"
CONFIG_TARGET_NANOPI2=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="nanopi2# "
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_S5PC1XX=y
CONFIG_SYS_TEXT_BASE=0x34800000
+CONFIG_SYS_MALLOC_LEN=0x5001000
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x7000
-CONFIG_SYS_MALLOC_LEN=0x5001000
CONFIG_DEFAULT_DEVICE_TREE="s5pc1xx-goni"
CONFIG_TARGET_S5P_GONI=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x44800000
+CONFIG_SYS_MALLOC_LEN=0x5001000
CONFIG_ARCH_EXYNOS4=y
CONFIG_TARGET_S5PC210_UNIVERSAL=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x7000
-CONFIG_SYS_MALLOC_LEN=0x5001000
CONFIG_DEFAULT_DEVICE_TREE="exynos4210-universal_c210"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x44800000
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x23f00000
-CONFIG_TARGET_SAM9X60EK=y
+CONFIG_SYS_MALLOC_LEN=0x81000
CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_TARGET_SAM9X60EK=y
CONFIG_NR_DRAM_BANKS=8
CONFIG_ENV_SIZE=0x4000
-CONFIG_SYS_MALLOC_LEN=0x81000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="sam9x60ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x23f00000
-CONFIG_TARGET_SAM9X60EK=y
+CONFIG_SYS_MALLOC_LEN=0x81000
CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_TARGET_SAM9X60EK=y
CONFIG_NR_DRAM_BANKS=8
-CONFIG_SYS_MALLOC_LEN=0x81000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="sam9x60ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x23f00000
-CONFIG_TARGET_SAM9X60EK=y
+CONFIG_SYS_MALLOC_LEN=0x81000
CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_TARGET_SAM9X60EK=y
CONFIG_NR_DRAM_BANKS=8
CONFIG_ENV_SECT_SIZE=0x1000
-CONFIG_SYS_MALLOC_LEN=0x81000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="sam9x60ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x23f00000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SAMA5D27_SOM1_EK=y
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4000
CONFIG_DM_GPIO=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x23f00000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SAMA5D27_SOM1_EK=y
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x4000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_som1_ek"
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x23f00000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SAMA5D27_SOM1_EK=y
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4000
CONFIG_DM_GPIO=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x23f00000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SAMA5D27_SOM1_EK=y
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_DM_GPIO=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SAMA5D27_WLSOM1_EK=y
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x4000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_wlsom1_ek"
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SAMA5D27_WLSOM1_EK=y
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SAMA5D2_ICP=y
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x4000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_icp"
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_MISC_INIT_R=y
CONFIG_SPL_DISPLAY_PRINT=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
-CONFIG_TARGET_SAMA5D2_ICP=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_SAMA5D2_ICP=y
CONFIG_SYS_MEMTEST_START=0x20000000
CONFIG_SYS_MEMTEST_END=0x40000000
CONFIG_ENV_SIZE=0x4000
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlycon earlyprintk=serial,ttyS0, ignore_loglevel root=/dev/mmcblk0p2 memtest=0 rootfstype=ext4 rw rootwait"
CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CONFIG=y
CONFIG_CMD_BOOTZ=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
-CONFIG_TARGET_SAMA5D2_PTC_EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_SAMA5D2_PTC_EK=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4000
CONFIG_DM_GPIO=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
-CONFIG_TARGET_SAMA5D2_PTC_EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_SAMA5D2_PTC_EK=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_ptc_ek"
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SAMA5D2_XPLAINED=y
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x4000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_xplained"
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SAMA5D2_XPLAINED=y
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4000
CONFIG_DM_GPIO=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SAMA5D2_XPLAINED=y
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_DM_GPIO=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SAMA5D2_XPLAINED=y
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x6000
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
-CONFIG_TARGET_SAMA5D3XEK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_SAMA5D3XEK=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4000
CONFIG_DM_GPIO=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
-CONFIG_TARGET_SAMA5D3XEK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_SAMA5D3XEK=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek_cmp"
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
-CONFIG_TARGET_SAMA5D3XEK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_SAMA5D3XEK=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x6000
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SAMA5D3_XPLAINED=y
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4000
CONFIG_DM_GPIO=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SAMA5D3_XPLAINED=y
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d3_xplained"
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SAMA5D3XEK=y
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4000
CONFIG_DM_GPIO=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SAMA5D3XEK=y
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek"
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SAMA5D3XEK=y
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x6000
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SAMA5D4_XPLAINED=y
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4000
CONFIG_DM_GPIO=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SAMA5D4_XPLAINED=y
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4_xplained"
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SAMA5D4_XPLAINED=y
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x6000
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SAMA5D4EK=y
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4000
CONFIG_DM_GPIO=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SAMA5D4EK=y
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4ek"
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SAMA5D4EK=y
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x6000
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x66f00000
-CONFIG_TARGET_SAMA7G5EK=y
CONFIG_SYS_MALLOC_F_LEN=0x11000
+CONFIG_TARGET_SAMA7G5EK=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x60000000
CONFIG_SYS_MEMTEST_END=0x70000000
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x66f00000
-CONFIG_TARGET_SAMA7G5EK=y
CONFIG_SYS_MALLOC_F_LEN=0x11000
+CONFIG_TARGET_SAMA7G5EK=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x60000000
CONFIG_SYS_MEMTEST_END=0x70000000
CONFIG_SYS_TEXT_BASE=0
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x00100000
CONFIG_SYS_MEMTEST_END=0x00101000
CONFIG_ENV_SIZE=0x2000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="sandbox64"
CONFIG_PRE_CON_BUF_ADDR=0x100000
CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_AMIGA_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_OF_LIVE=y
-CONFIG_OF_HOSTFILE=y
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_EXT4=y
CONFIG_ENV_EXT4_INTERFACE="host"
CONFIG_I2C_ARB_GPIO_CHALLENGE=y
CONFIG_CROS_EC_KEYB=y
CONFIG_I8042_KEYB=y
+CONFIG_IOMMU=y
CONFIG_LED=y
CONFIG_LED_BLINK=y
CONFIG_LED_GPIO=y
CONFIG_CONSOLE_ROTATION=y
CONFIG_CONSOLE_TRUETYPE=y
CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y
+CONFIG_I2C_EDID=y
CONFIG_VIDEO_SANDBOX_SDL=y
CONFIG_OSD=y
CONFIG_SANDBOX_OSD=y
CONFIG_SYS_TEXT_BASE=0
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x00100000
CONFIG_SYS_MEMTEST_END=0x00101000
CONFIG_ENV_SIZE=0x2000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="sandbox"
CONFIG_PRE_CON_BUF_ADDR=0xf0000
CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_AMIGA_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_OF_LIVE=y
-CONFIG_OF_HOSTFILE=y
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_EXT4=y
CONFIG_ENV_EXT4_INTERFACE="host"
CONFIG_I2C_ARB_GPIO_CHALLENGE=y
CONFIG_CROS_EC_KEYB=y
CONFIG_I8042_KEYB=y
+CONFIG_IOMMU=y
CONFIG_LED=y
CONFIG_LED_BLINK=y
CONFIG_LED_GPIO=y
CONFIG_CONSOLE_ROTATION=y
CONFIG_CONSOLE_TRUETYPE=y
CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y
+CONFIG_I2C_EDID=y
CONFIG_VIDEO_SANDBOX_SDL=y
CONFIG_VIDEO_DSI_HOST_SANDBOX=y
CONFIG_OSD=y
CONFIG_SYS_TEXT_BASE=0
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x00100000
CONFIG_SYS_MEMTEST_END=0x00101000
CONFIG_ENV_SIZE=0x2000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="sandbox"
CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_DEBUG_UART=y
CONFIG_MAC_PARTITION=y
CONFIG_AMIGA_PARTITION=y
CONFIG_OF_CONTROL=y
-CONFIG_OF_HOSTFILE=y
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_EXT4=y
CONFIG_ENV_EXT4_INTERFACE="host"
CONFIG_I2C_ARB_GPIO_CHALLENGE=y
CONFIG_CROS_EC_KEYB=y
CONFIG_I8042_KEYB=y
+CONFIG_IOMMU=y
CONFIG_LED=y
CONFIG_LED_BLINK=y
CONFIG_LED_GPIO=y
CONFIG_CONSOLE_ROTATION=y
CONFIG_CONSOLE_TRUETYPE=y
CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y
+CONFIG_I2C_EDID=y
CONFIG_VIDEO_SANDBOX_SDL=y
CONFIG_OSD=y
CONFIG_SANDBOX_OSD=y
CONFIG_SYS_TEXT_BASE=0x200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MEMTEST_START=0x00100000
CONFIG_SYS_MEMTEST_END=0x00101000
CONFIG_ENV_SIZE=0x2000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="sandbox"
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_AMIGA_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_HOSTFILE=y
CONFIG_SPL_OF_PLATDATA=y
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_EXT4=y
CONFIG_I2C_ARB_GPIO_CHALLENGE=y
CONFIG_CROS_EC_KEYB=y
CONFIG_I8042_KEYB=y
+CONFIG_IOMMU=y
CONFIG_LED=y
CONFIG_LED_BLINK=y
CONFIG_LED_GPIO=y
CONFIG_CONSOLE_ROTATION=y
CONFIG_CONSOLE_TRUETYPE=y
CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y
+CONFIG_I2C_EDID=y
CONFIG_VIDEO_SANDBOX_SDL=y
CONFIG_OSD=y
CONFIG_SANDBOX_OSD=y
CONFIG_SYS_TEXT_BASE=0x200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MEMTEST_START=0x00100000
CONFIG_SYS_MEMTEST_END=0x00101000
CONFIG_ENV_SIZE=0x2000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="sandbox"
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_AMIGA_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_HOSTFILE=y
CONFIG_SPL_OF_PLATDATA=y
CONFIG_SPL_OF_PLATDATA_INST=y
CONFIG_ENV_IS_NOWHERE=y
CONFIG_I2C_ARB_GPIO_CHALLENGE=y
CONFIG_CROS_EC_KEYB=y
CONFIG_I8042_KEYB=y
+CONFIG_IOMMU=y
CONFIG_LED=y
CONFIG_LED_BLINK=y
CONFIG_LED_GPIO=y
CONFIG_CONSOLE_ROTATION=y
CONFIG_CONSOLE_TRUETYPE=y
CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y
+CONFIG_I2C_EDID=y
CONFIG_VIDEO_SANDBOX_SDL=y
CONFIG_OSD=y
CONFIG_SANDBOX_OSD=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_SYS_MALLOC_LEN=0x0200000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=8
CONFIG_ENV_OFFSET=0x3c00000
CONFIG_MX6ULL=y
CONFIG_TARGET_NPI_IMX6ULL=y
-CONFIG_SYS_MALLOC_LEN=0x0200000
CONFIG_DEFAULT_DEVICE_TREE="imx6ull-seeed-npi-imx6ull-dev-board"
CONFIG_SPL_TEXT_BASE=0x908000
CONFIG_SPL_MMC=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
CONFIG_SYS_CONFIG_NAME="sei510"
CONFIG_ARCH_MESON=y
CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_SYS_MALLOC_LEN=0x8000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0xFFFF0000
-CONFIG_SYS_MALLOC_LEN=0x8000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="meson-g12a-sei510"
CONFIG_MESON_G12A=y
CONFIG_SYS_CONFIG_NAME="sei610"
CONFIG_ARCH_MESON=y
CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_SYS_MALLOC_LEN=0x8000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0xFFFF0000
-CONFIG_SYS_MALLOC_LEN=0x8000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-sei610"
CONFIG_MESON_G12A=y
CONFIG_RISCV=y
-CONFIG_SPL_GPIO=y
+CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_SYS_MALLOC_F_LEN=0x3000
+CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="hifive-unleashed-a00"
CONFIG_SPL_MMC=y
CONFIG_RISCV=y
# CONFIG_SPL_USE_ARCH_MEMMOVE is not set
-CONFIG_SPL_GPIO=y
+CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_SYS_MALLOC_F_LEN=0x3000
+CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="hifive-unmatched-a00"
CONFIG_SPL_MMC=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_TEXT_BASE=0x50000000
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x3F0000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r8a774c0-ek874-u-boot"
CONFIG_SPL_TEXT_BASE=0xe6318000
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_TEXT_BASE=0x50000000
+CONFIG_SYS_MALLOC_LEN=0x100000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r8a7794-silk-u-boot"
CONFIG_SPL_TEXT_BASE=0xe6300000
CONFIG_RISCV=y
+CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0xfff000
CONFIG_ENV_SECT_SIZE=0x1000
-CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_TARGET_SIPEED_MAIX=y
CONFIG_ARCH_RV64I=y
CONFIG_SYS_LOAD_ADDR=0x80000000
CONFIG_RISCV=y
CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0xfff000
CONFIG_ENV_SECT_SIZE=0x1000
-CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_TARGET_SIPEED_MAIX=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x23000000
+CONFIG_SYS_MALLOC_LEN=0x460000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SMARTWEB=y
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0x100000
-CONFIG_SYS_MALLOC_LEN=0x460000
CONFIG_DEFAULT_DEVICE_TREE="at91sam9260-smartweb"
CONFIG_SPL_SYS_MALLOC_F_LEN=0x400
CONFIG_SPL=y
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
-CONFIG_PHYLIB=y
+CONFIG_MACB=y
CONFIG_ATMEL_USART=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x43E00000
+CONFIG_SYS_MALLOC_LEN=0x5004000
CONFIG_ARCH_EXYNOS5=y
CONFIG_TARGET_SMDK5250=y
CONFIG_NR_DRAM_BANKS=8
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x3FC000
CONFIG_ENV_SECT_SIZE=0x4000
-CONFIG_SYS_MALLOC_LEN=0x5004000
CONFIG_DEFAULT_DEVICE_TREE="exynos5250-smdk5250"
CONFIG_SPL_TEXT_BASE=0x02023400
CONFIG_SPL=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x23E00000
+CONFIG_SYS_MALLOC_LEN=0x5004000
CONFIG_ARCH_EXYNOS5=y
CONFIG_TARGET_SMDK5420=y
CONFIG_NR_DRAM_BANKS=7
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x3FC000
CONFIG_ENV_SECT_SIZE=0x4000
-CONFIG_SYS_MALLOC_LEN=0x5004000
CONFIG_DEFAULT_DEVICE_TREE="exynos5420-smdk5420"
CONFIG_SPL_TEXT_BASE=0x02024410
CONFIG_SPL=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_S5PC1XX=y
CONFIG_SYS_TEXT_BASE=0x34800000
+CONFIG_SYS_MALLOC_LEN=0x120000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x120000
CONFIG_DEFAULT_DEVICE_TREE="s5pc1xx-smdkc100"
CONFIG_TARGET_SMDKC100=y
CONFIG_IDENT_STRING=" for SMDKC100"
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x43E00000
+CONFIG_SYS_MALLOC_LEN=0x5004000
CONFIG_ARCH_EXYNOS4=y
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x4200
-CONFIG_SYS_MALLOC_LEN=0x5004000
CONFIG_DEFAULT_DEVICE_TREE="exynos4210-smdkv310"
CONFIG_SPL_TEXT_BASE=0x02021410
CONFIG_SPL=y
CONFIG_ARM=y
CONFIG_ARCH_MX7=y
+CONFIG_SYS_MALLOC_LEN=0x2300000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0xa0000000
CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0xC0000
-CONFIG_SYS_MALLOC_LEN=0x2300000
+CONFIG_ENV_OFFSET=0x100000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7d-smegw01"
CONFIG_TARGET_SMEGW01=y
+CONFIG_ENV_OFFSET_REDUND=0x110000
CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
# CONFIG_ARMV7_VIRT is not set
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
+CONFIG_IMX_HAB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_TARGET_SNAPPER9260=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x80000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SYS_LOAD_ADDR=0x23000000
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260"
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
+# CONFIG_CMD_MDIO is not set
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
CONFIG_ENV_OVERWRITE=y
CONFIG_MTD_RAW_NAND=y
# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
+CONFIG_MACB=y
CONFIG_ATMEL_USART=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_TARGET_SNAPPER9260=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x80000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SYS_LOAD_ADDR=0x23000000
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20"
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
+# CONFIG_CMD_MDIO is not set
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
CONFIG_ENV_OVERWRITE=y
CONFIG_MTD_RAW_NAND=y
# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
+CONFIG_MACB=y
CONFIG_ATMEL_USART=y
# CONFIG_SYS_THUMB_BUILD is not set
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80100000
-CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MALLOC_LEN=0x120000
+CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_TARGET_SNIPER=y
CONFIG_SPL=y
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x43E00000
+CONFIG_SYS_MALLOC_LEN=0x5004000
CONFIG_ARCH_EXYNOS5=y
CONFIG_TARGET_SNOW=y
CONFIG_NR_DRAM_BANKS=8
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x3FC000
CONFIG_ENV_SECT_SIZE=0x4000
-CONFIG_SYS_MALLOC_LEN=0x5004000
CONFIG_DEFAULT_DEVICE_TREE="exynos5250-snow"
CONFIG_SPL_TEXT_BASE=0x02023400
CONFIG_SPL=y
CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds"
CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_TEXT_BASE=0x200000
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x200
-CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk"
CONFIG_SPL_TEXT_BASE=0xFFE00000
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_TEXT_BASE=0x1000
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_MEMTEST_END=0x3fe00000
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x200
-CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk"
CONFIG_SPL_TEXT_BASE=0xFFE00000
CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds"
CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_TEXT_BASE=0x200000
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x200
-CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk"
CONFIG_SPL_TEXT_BASE=0xFFE00000
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x4400
-CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
CONFIG_SPL_TEXT_BASE=0xFFE00000
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x4400
-CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk"
CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x4400
-CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk"
CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x4400
-CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_dbm_soc1"
CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x4400
-CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de0_nano_soc"
CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x4400
-CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de10_nano"
CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x4400
-CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de1_soc"
CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_is1"
CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x4400
-CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_mcvevk"
CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds"
CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_TEXT_BASE=0x200000
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x200
-CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_n5x_socdk"
CONFIG_SPL_TEXT_BASE=0xFFE00000
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_TEXT_BASE=0x1000
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x200
-CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_n5x_socdk"
CONFIG_SPL_TEXT_BASE=0xFFE00000
CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds"
CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_TEXT_BASE=0x200000
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x200
-CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_n5x_socdk"
CONFIG_SPL_TEXT_BASE=0xFFE00000
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x100000
-CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_secu1"
CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_MISC_INIT_R=y
CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION is not set
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x4400
-CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sockit"
CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x4400
-CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates"
CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_MEMTEST_END=0x40000000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0xE0000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500"
CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds"
CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_TEXT_BASE=0x200000
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x200
-CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
CONFIG_SPL_TEXT_BASE=0xFFE00000
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_TEXT_BASE=0x1000
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_MEMTEST_END=0x3fe00000
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x200
-CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
CONFIG_SPL_TEXT_BASE=0xFFE00000
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_vining_fpga"
CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x88000000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_MX6ULL=y
CONFIG_TARGET_SOMLABS_VISIONSOM_6ULL=y
-CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DEFAULT_DEVICE_TREE="imx6ull-somlabs-visionsom"
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x43E00000
+CONFIG_SYS_MALLOC_LEN=0x5004000
CONFIG_ARCH_EXYNOS5=y
CONFIG_TARGET_SPRING=y
CONFIG_NR_DRAM_BANKS=8
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x3FC000
CONFIG_ENV_SECT_SIZE=0x4000
-CONFIG_SYS_MALLOC_LEN=0x5004000
CONFIG_DEFAULT_DEVICE_TREE="exynos5250-spring"
CONFIG_SPL_TEXT_BASE=0x02023400
CONFIG_SPL=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_ARCH_SNAPDRAGON=y
+CONFIG_SYS_TEXT_BASE=0x80000000
+CONFIG_SYS_MALLOC_LEN=0x81f000
+CONFIG_DEFAULT_DEVICE_TREE="starqltechn"
+CONFIG_TARGET_STARQLTECHN=y
+CONFIG_IDENT_STRING="\nSamsung S9 SM-G9600"
+CONFIG_SYS_LOAD_ADDR=0x80000000
+CONFIG_USE_PREBOOT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GPIO=y
+# CONFIG_NET is not set
+# CONFIG_DM_STDIO is not set
+CONFIG_CLK=y
+CONFIG_MSM_GPIO=y
+CONFIG_PM8916_GPIO=y
+CONFIG_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_PM8916=y
+CONFIG_MSM_GENI_SERIAL=y
+CONFIG_SPMI_MSM=y
# CONFIG_SETUP_MEMORY_TAGS is not set
CONFIG_INITRD_TAG=y
CONFIG_SYS_TEXT_BASE=0x100000
-CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MALLOC_LEN=0x0200000
+CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="ste-ux500-samsung-stemmy"
CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_USE_BOOTCOMMAND=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_STI=y
CONFIG_SYS_TEXT_BASE=0x7D600000
+CONFIG_SYS_MALLOC_LEN=0x1800000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4000
-CONFIG_SYS_MALLOC_LEN=0x1800000
CONFIG_DEFAULT_DEVICE_TREE="stih410-b2260"
CONFIG_IDENT_STRING="STMicroelectronics STiH410-B2260"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ARM=y
CONFIG_ARCH_STM32=y
CONFIG_SYS_TEXT_BASE=0x08000000
+CONFIG_SYS_MALLOC_LEN=0x0200000
CONFIG_SYS_MALLOC_F_LEN=0xF00
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x0200000
CONFIG_DEFAULT_DEVICE_TREE="stm32f429-disco"
CONFIG_STM32F4=y
CONFIG_TARGET_STM32F429_DISCOVERY=y
CONFIG_ARM=y
CONFIG_ARCH_STM32=y
CONFIG_SYS_TEXT_BASE=0x08000000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SYS_MALLOC_F_LEN=0xF00
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="stm32429i-eval"
CONFIG_STM32F4=y
CONFIG_TARGET_STM32F429_EVALUATION=y
CONFIG_ARM=y
CONFIG_ARCH_STM32=y
CONFIG_SYS_TEXT_BASE=0x08000000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SYS_MALLOC_F_LEN=0xF00
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="stm32f469-disco"
CONFIG_STM32F4=y
CONFIG_TARGET_STM32F469_DISCOVERY=y
CONFIG_ARM=y
CONFIG_ARCH_STM32=y
CONFIG_SYS_TEXT_BASE=0x08008000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SYS_MALLOC_F_LEN=0xE00
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="stm32f746-disco"
CONFIG_SPL_TEXT_BASE=0x8000000
CONFIG_STM32F7=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_LATE_INIT=y
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_CMD_GPT=y
CONFIG_ARM=y
CONFIG_ARCH_STM32=y
CONFIG_SYS_TEXT_BASE=0x08008000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SYS_MALLOC_F_LEN=0xE00
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="stm32f769-disco"
CONFIG_SPL_TEXT_BASE=0x8000000
CONFIG_STM32F7=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_CMD_GPT=y
# CONFIG_RANDOM_UUID is not set
CONFIG_ARM=y
CONFIG_ARCH_STM32=y
CONFIG_SYS_TEXT_BASE=0x08000000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SYS_MALLOC_F_LEN=0xF00
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="stm32h743i-disco"
CONFIG_STM32H7=y
CONFIG_TARGET_STM32H743_DISCO=y
CONFIG_ARM=y
CONFIG_ARCH_STM32=y
CONFIG_SYS_TEXT_BASE=0x08000000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SYS_MALLOC_F_LEN=0xF00
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="stm32h743i-eval"
CONFIG_STM32H7=y
CONFIG_TARGET_STM32H743_EVAL=y
CONFIG_ARM=y
CONFIG_ARCH_STM32=y
CONFIG_SYS_TEXT_BASE=0x90000000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SYS_MALLOC_F_LEN=0xF00
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="stm32h750i-art-pi"
CONFIG_STM32H7=y
CONFIG_TARGET_STM32H750_ART_PI=y
CONFIG_DM_RTC=y
CONFIG_RTC_STM32=y
CONFIG_SERIAL_RX_BUFFER=y
+CONFIG_SYSRESET_SYSCON=y
CONFIG_WDT=y
CONFIG_WDT_STM32MP=y
+# CONFIG_BINMAN_FDT is not set
CONFIG_LZO=y
CONFIG_ERRNO_STR=y
CONFIG_DM_RTC=y
CONFIG_RTC_STM32=y
CONFIG_SERIAL_RX_BUFFER=y
+CONFIG_SYSRESET_SYSCON=y
CONFIG_WDT=y
CONFIG_WDT_STM32MP=y
+# CONFIG_BINMAN_FDT is not set
CONFIG_LZO=y
CONFIG_ERRNO_STR=y
CONFIG_DM_RTC=y
CONFIG_RTC_STM32=y
CONFIG_SERIAL_RX_BUFFER=y
+CONFIG_SYSRESET_SYSCON=y
CONFIG_WDT=y
CONFIG_WDT_STM32MP=y
+# CONFIG_BINMAN_FDT is not set
CONFIG_LZO=y
CONFIG_ERRNO_STR=y
CONFIG_DM_RTC=y
CONFIG_RTC_STM32=y
CONFIG_SERIAL_RX_BUFFER=y
+CONFIG_SYSRESET_SYSCON=y
CONFIG_WDT=y
CONFIG_WDT_STM32MP=y
+# CONFIG_BINMAN_FDT is not set
CONFIG_LZO=y
CONFIG_ERRNO_STR=y
CONFIG_DM_SPI=y
CONFIG_STM32_QSPI=y
CONFIG_STM32_SPI=y
+CONFIG_SYSRESET_SYSCON=y
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_USB_EHCI_HCD=y
CONFIG_BMP_32BPP=y
CONFIG_WDT=y
CONFIG_WDT_STM32MP=y
+# CONFIG_BINMAN_FDT is not set
CONFIG_ERRNO_STR=y
CONFIG_FDT_FIXUP_PARTITIONS=y
# CONFIG_LMB_USE_MAX_REGIONS is not set
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1"
CONFIG_TARGET_ST_STM32MP15x=y
+CONFIG_DDR_CACHEABLE_SIZE=0x10000000
CONFIG_CMD_STM32KEY=y
CONFIG_CMD_STM32PROG=y
CONFIG_ENV_OFFSET_REDUND=0x4C0000
CONFIG_TYPEC_STUSB160X=y
+# CONFIG_ARMV7_NONSEC is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0xc2000000
CONFIG_FIT=y
CONFIG_DM_SPI=y
CONFIG_STM32_QSPI=y
CONFIG_STM32_SPI=y
+CONFIG_SYSRESET_PSCI=y
CONFIG_TEE=y
CONFIG_OPTEE=y
# CONFIG_OPTEE_TA_AVB is not set
CONFIG_BMP_32BPP=y
CONFIG_WDT=y
CONFIG_WDT_STM32MP=y
+# CONFIG_BINMAN_FDT is not set
CONFIG_ERRNO_STR=y
CONFIG_FDT_FIXUP_PARTITIONS=y
# CONFIG_LMB_USE_MAX_REGIONS is not set
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_BOOTDELAY=1
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
+CONFIG_CONSOLE_MUX=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nor0=nor0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=nor0:256k(fsbl1),256k(fsbl2),1408k(uboot),64k(env1),64k(env2)"
# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_OF_LIST="stm32mp15xx-dhcom-pdk2 stm32mp15xx-dhcom-drc02 stm32mp15xx-dhcom-picoitx"
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USE_ENV_SPI_CS=y
CONFIG_ENV_SPI_CS=0
CONFIG_USE_ENV_SPI_MAX_HZ=y
-CONFIG_ENV_SPI_MAX_HZ=10000000
+CONFIG_ENV_SPI_MAX_HZ=50000000
CONFIG_USE_ENV_SPI_MODE=y
CONFIG_ENV_SPI_MODE=0x0
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_STM32_ADC=y
CONFIG_SPL_BLOCK_CACHE=y
CONFIG_DFU_MMC=y
+CONFIG_DFU_MTD=y
CONFIG_DFU_RAM=y
CONFIG_DFU_VIRT=y
CONFIG_SET_DFU_ALT_INFO=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_STM32_SDMMC2=y
CONFIG_MTD=y
-CONFIG_SYS_MTDPARTS_RUNTIME=y
+CONFIG_DM_MTD=y
CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=50000000
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_DM_SPI=y
CONFIG_STM32_QSPI=y
CONFIG_STM32_SPI=y
+CONFIG_SYSRESET_SYSCON=y
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_GADGET_PRODUCT_NUM=0x5720
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_DM_VIDEO=y
-CONFIG_BACKLIGHT_GPIO=y
-CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y
-CONFIG_VIDEO_LCD_RAYDIUM_RM68200=y
-CONFIG_VIDEO_STM32=y
-CONFIG_VIDEO_STM32_DSI=y
-CONFIG_VIDEO_STM32_MAX_XRES=1280
-CONFIG_VIDEO_STM32_MAX_YRES=800
-CONFIG_VIDEO_BMP_RLE8=y
-CONFIG_BMP_16BPP=y
-CONFIG_BMP_24BPP=y
-CONFIG_BMP_32BPP=y
+CONFIG_FAT_WRITE=y
+# CONFIG_BINMAN_FDT is not set
CONFIG_LZO=y
CONFIG_FDT_FIXUP_PARTITIONS=y
+# CONFIG_EFI_LOADER is not set
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_BOOTDELAY=1
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
+CONFIG_CONSOLE_MUX=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nor0=nor0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=nor0:256k(fsbl1),256k(fsbl2),1408k(uboot),64k(env1),64k(env2)"
# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USE_ENV_SPI_BUS=y
CONFIG_USE_ENV_SPI_CS=y
CONFIG_ENV_SPI_CS=0
CONFIG_USE_ENV_SPI_MAX_HZ=y
-CONFIG_ENV_SPI_MAX_HZ=10000000
+CONFIG_ENV_SPI_MAX_HZ=50000000
CONFIG_USE_ENV_SPI_MODE=y
CONFIG_ENV_SPI_MODE=0x0
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_STM32_ADC=y
CONFIG_SPL_BLOCK_CACHE=y
CONFIG_DFU_MMC=y
+CONFIG_DFU_MTD=y
CONFIG_DFU_RAM=y
CONFIG_DFU_VIRT=y
CONFIG_GPIO_HOG=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_STM32_SDMMC2=y
CONFIG_MTD=y
+CONFIG_DM_MTD=y
CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=50000000
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_DM_SPI=y
CONFIG_STM32_QSPI=y
CONFIG_STM32_SPI=y
+CONFIG_SYSRESET_SYSCON=y
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_GADGET_PRODUCT_NUM=0x5720
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_DM_VIDEO=y
-CONFIG_BACKLIGHT_GPIO=y
-CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y
-CONFIG_VIDEO_LCD_RAYDIUM_RM68200=y
-CONFIG_VIDEO_STM32=y
-CONFIG_VIDEO_STM32_DSI=y
-CONFIG_VIDEO_STM32_MAX_XRES=1280
-CONFIG_VIDEO_STM32_MAX_YRES=800
-CONFIG_VIDEO_BMP_RLE8=y
-CONFIG_BMP_16BPP=y
-CONFIG_BMP_24BPP=y
-CONFIG_BMP_32BPP=y
+CONFIG_FAT_WRITE=y
+# CONFIG_BINMAN_FDT is not set
CONFIG_LZO=y
CONFIG_FDT_FIXUP_PARTITIONS=y
+# CONFIG_EFI_LOADER is not set
CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1"
CONFIG_STM32MP15x_STM32IMAGE=y
CONFIG_TARGET_ST_STM32MP15x=y
+CONFIG_DDR_CACHEABLE_SIZE=0x10000000
CONFIG_CMD_STM32KEY=y
CONFIG_CMD_STM32PROG=y
CONFIG_ENV_OFFSET_REDUND=0x2C0000
CONFIG_TYPEC_STUSB160X=y
+# CONFIG_ARMV7_NONSEC is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0xc2000000
CONFIG_FIT=y
CONFIG_DM_SPI=y
CONFIG_STM32_QSPI=y
CONFIG_STM32_SPI=y
+CONFIG_SYSRESET_PSCI=y
CONFIG_TEE=y
CONFIG_OPTEE=y
# CONFIG_OPTEE_TA_AVB is not set
CONFIG_BMP_32BPP=y
CONFIG_WDT=y
CONFIG_WDT_STM32MP=y
+# CONFIG_BINMAN_FDT is not set
CONFIG_ERRNO_STR=y
CONFIG_FDT_FIXUP_PARTITIONS=y
# CONFIG_LMB_USE_MAX_REGIONS is not set
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x47E00000
+CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x40000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_DEFAULT_DEVICE_TREE="stmark2"
CONFIG_TARGET_STMARK2=y
CONFIG_SYS_LOAD_ADDR=0x40010000
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MTD=y
+CONFIG_MCFUART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_TEXT_BASE=0x50000000
+CONFIG_SYS_MALLOC_LEN=0x100000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r8a7790-stout-u-boot"
CONFIG_SPL_TEXT_BASE=0xe6300000
CONFIG_SYS_DCACHE_OFF=y
CONFIG_TARGET_STV0991=y
CONFIG_SYS_TEXT_BASE=0x00010000
+CONFIG_SYS_MALLOC_LEN=0x14000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x30000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x14000
CONFIG_DEFAULT_DEVICE_TREE="stv0991"
CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_BOOTDELAY=3
CONFIG_ARM=y
CONFIG_ARCH_SYNQUACER=y
CONFIG_SYS_TEXT_BASE=0x08200000
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_ENV_SIZE=0x30000
CONFIG_ENV_OFFSET=0x300000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="synquacer-sc2a11-developerbox"
CONFIG_TARGET_DEVELOPERBOX=y
CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_LOG=y
CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USE_ENV_SPI_BUS=y
CONFIG_ENV_SPI_BUS=0
CONFIG_SCSI_AHCI=y
CONFIG_AHCI_PCI=y
CONFIG_DFU_TFTP=y
+CONFIG_DFU_MTD=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
-CONFIG_DFU_MTD=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_SYNQUACER=y
CONFIG_MMC_SDHCI=y
CONFIG_ARCH_AT91=y
CONFIG_SPL_LDSCRIPT="arch/arm/cpu/u-boot-spl.lds"
CONFIG_SYS_TEXT_BASE=0x21000000
+CONFIG_SYS_MALLOC_LEN=0x460000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_TAURUS=y
CONFIG_BOARD_TAURUS=y
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0x100000
-CONFIG_SYS_MALLOC_LEN=0x460000
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20-taurus"
CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000
CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
+CONFIG_MACB=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_ARC=y
CONFIG_TARGET_TB100=y
CONFIG_SYS_TEXT_BASE=0x84000000
-CONFIG_ENV_SIZE=0x800
CONFIG_SYS_MALLOC_LEN=0x20000
+CONFIG_ENV_SIZE=0x800
CONFIG_DEFAULT_DEVICE_TREE="abilis_tb100"
CONFIG_SYS_CLK_FREQ=500000000
CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_LEN=0x8000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x10000000
CONFIG_SYS_MEMTEST_END=0x2f400000
CONFIG_ENV_OFFSET=0x60000
CONFIG_MX6Q=y
CONFIG_TARGET_TBS2910=y
-CONFIG_SYS_MALLOC_LEN=0x8000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-tbs2910"
CONFIG_PRE_CON_BUF_ADDR=0x7c000000
CONFIG_PREBOOT="setenv usb_pgood_delay 2000; usb start"
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
-CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_PWM=y
CONFIG_PWM_SUNXI=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00800000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_THEADORABLE=y
CONFIG_ENV_SIZE=0x10000
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80100000
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
-CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
CONFIG_AM33XX=y
CONFIG_ARM=y
CONFIG_TARGET_THUNDERX_88XX=y
CONFIG_SYS_TEXT_BASE=0x00500000
+CONFIG_SYS_MALLOC_LEN=0x101000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x1000
-CONFIG_SYS_MALLOC_LEN=0x101000
CONFIG_DEFAULT_DEVICE_TREE="thunderx-88xx"
CONFIG_DEBUG_UART_BASE=0x87e024000000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x01000000
-CONFIG_SPL_GPIO=y
CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEFAULT_DEVICE_TREE="rk3288-tinker-s"
CONFIG_ROCKCHIP_RK3288=y
CONFIG_SYS_TEXT_BASE=0
-CONFIG_ENV_SIZE=0x2000
CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="sandbox"
CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_BOOTP_DNS2=y
# CONFIG_CMD_DATE is not set
CONFIG_OF_CONTROL=y
-CONFIG_OF_HOSTFILE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_IP_DEFRAG=y
CONFIG_DM_RTC=y
CONFIG_SOUND=y
CONFIG_SYSRESET=y
+CONFIG_I2C_EDID=y
# CONFIG_VIRTIO_MMIO is not set
# CONFIG_VIRTIO_PCI is not set
# CONFIG_VIRTIO_SANDBOX is not set
-# CONFIG_EFI_LOADER is not set
CONFIG_ARM=y
CONFIG_TARGET_TOTAL_COMPUTE=y
CONFIG_SYS_TEXT_BASE=0xe0000000
+CONFIG_SYS_MALLOC_LEN=0x3200000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0xff000000
CONFIG_ENV_SIZE=0x2a00000
-CONFIG_SYS_MALLOC_LEN=0x3200000
CONFIG_DEFAULT_DEVICE_TREE="total_compute"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x90000000
CONFIG_MIPS=y
CONFIG_SYS_TEXT_BASE=0xA1000000
+CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SYS_MEMTEST_START=0x80100000
CONFIG_SYS_MEMTEST_END=0x83f00000
CONFIG_ENV_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_DEFAULT_DEVICE_TREE="tplink_wdr4300"
CONFIG_ARCH_ATH79=y
CONFIG_BOARD_TPLINK_WDR4300=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_MX6DL=y
CONFIG_TARGET_TQMA6=y
-CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-mba6b"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x80000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_MX6DL=y
CONFIG_TARGET_TQMA6=y
-CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_TQMA6X_SPI_BOOT=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-mba6b"
CONFIG_ENV_OFFSET_REDUND=0x90000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_MX6Q=y
CONFIG_TARGET_TQMA6=y
-CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DEFAULT_DEVICE_TREE="imx6q-mba6b"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x80000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_MX6Q=y
CONFIG_TARGET_TQMA6=y
-CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_TQMA6X_SPI_BOOT=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-mba6b"
CONFIG_ENV_OFFSET_REDUND=0x90000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_MX6S=y
CONFIG_TARGET_TQMA6=y
-CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-mba6b"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x80000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_MX6S=y
CONFIG_TARGET_TQMA6=y
-CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_TQMA6X_SPI_BOOT=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-mba6b"
CONFIG_ENV_OFFSET_REDUND=0x90000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x43e00000
+CONFIG_SYS_MALLOC_LEN=0x5001000
CONFIG_ARCH_EXYNOS4=y
CONFIG_TARGET_TRATS2=y
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x7000
-CONFIG_SYS_MALLOC_LEN=0x5001000
CONFIG_DEFAULT_DEVICE_TREE="exynos4412-trats2"
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x63300000
+CONFIG_SYS_MALLOC_LEN=0x5001000
CONFIG_ARCH_EXYNOS4=y
CONFIG_TARGET_TRATS=y
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x7000
-CONFIG_SYS_MALLOC_LEN=0x5001000
CONFIG_DEFAULT_DEVICE_TREE="exynos4210-trats"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x44800000
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_ARCH_EARLY_INIT_R=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_CMD_SHA1SUM=y
CONFIG_CMD_CLK=y
CONFIG_CLK_MVEBU=y
# CONFIG_MVEBU_GPIO is not set
CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MV=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_MISC=y
CONFIG_SPL_SYS_THUMB_BUILD=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00800000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x00800000
CONFIG_SYS_MEMTEST_END=0x00ffffff
CONFIG_CLK_MVEBU=y
CONFIG_DM_I2C=y
CONFIG_DM_I2C_GPIO=y
+CONFIG_SYS_I2C_MV=y
CONFIG_MISC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_LEN=0x0200000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_OFFSET=0x60000
CONFIG_MX6QDL=y
CONFIG_TARGET_UDOO=y
-CONFIG_SYS_MALLOC_LEN=0x0200000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-udoo"
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_SYS_MALLOC_LEN=0x300000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_MX6SX=y
CONFIG_TARGET_UDOO_NEO=y
CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_MALLOC_LEN=0x300000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6sx-udoo-neo-basic"
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x23f00000
-CONFIG_TARGET_USB_A9263=y
+CONFIG_SYS_MALLOC_LEN=0x26000
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_USB_A9263=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x2000
CONFIG_ENV_SECT_SIZE=0x2000
-CONFIG_SYS_MALLOC_LEN=0x26000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="usb_a9263"
CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_DATAFLASH=y
+CONFIG_MACB=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
CONFIG_ARM=y
CONFIG_ARCH_MX5=y
CONFIG_SYS_TEXT_BASE=0x77800000
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x70000000
CONFIG_SYS_MEMTEST_END=0x90000000
CONFIG_TARGET_USBARMORY=y
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx53-usbarmory"
# CONFIG_CMD_BMODE is not set
CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
+CONFIG_DM_ETH=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX5=y
CONFIG_DM_REGULATOR=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x86000000
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=8
CONFIG_ENV_SIZE=0x2000
CONFIG_MX6ULL=y
CONFIG_TARGET_DART_6UL=y
-CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DEFAULT_DEVICE_TREE="imx6ull-dart-6ul"
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_MMC=y
CONFIG_SYS_I2C_MXC=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_PHYLIB=y
CONFIG_ARM=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80110000
+CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFE000
-CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_DEFAULT_DEVICE_TREE="tegra124-venice2"
CONFIG_SPL_TEXT_BASE=0x80108000
CONFIG_TEGRA124=y
CONFIG_ARM=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_SYS_MEMTEST_START=0x40000000
CONFIG_SYS_MEMTEST_END=0x80000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFDE00
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mm-verdin"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
-CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_SYSTEM_SETUP=y
# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_DEFAULT_FDT_FILE="fsl-imx8mm-verdin-dev.dtb"
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="setenv fdtfile imx8mm-verdin-${variant}-${fdt_board}.dtb"
CONFIG_LOG=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_IMX8MM=y
CONFIG_CLK_IMX8MM=y
+CONFIG_GPIO_HOG=y
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC_IMX=y
+CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_MICREL=y
CONFIG_ARM=y
CONFIG_TARGET_VEXPRESS64_JUNO=y
CONFIG_SYS_TEXT_BASE=0xe0000000
+CONFIG_SYS_MALLOC_LEN=0x810000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0xff000000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_MALLOC_LEN=0x810000
CONFIG_IDENT_STRING=" vexpress_aemv8a"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x90000000
CONFIG_ARM=y
CONFIG_TARGET_VEXPRESS64_BASE_FVP=y
CONFIG_SYS_TEXT_BASE=0x88000000
+CONFIG_SYS_MALLOC_LEN=0x840000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0xff000000
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_SYS_MALLOC_LEN=0x840000
CONFIG_IDENT_STRING=" vexpress_aemv8a"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x90000000
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_VF610=y
CONFIG_SYS_TEXT_BASE=0x3f401000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x80010000
CONFIG_SYS_MEMTEST_END=0x87c00000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="vf610-twr"
CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
-# CONFIG_EFI_LOADER is not set
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_VF610=y
CONFIG_SYS_TEXT_BASE=0x3f401000
+CONFIG_SYS_MALLOC_LEN=0x0220000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x80010000
CONFIG_SYS_MEMTEST_END=0x87c00000
CONFIG_ENV_OFFSET=0x180000
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_MALLOC_LEN=0x0220000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="vf610-twr"
CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
-# CONFIG_EFI_LOADER is not set
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_PHY_SMSC=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_MACB=y
CONFIG_ATMEL_USART=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_SYS_MALLOC_LEN=0x300000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x80000
CONFIG_TARGET_SOFTING_VINING_2000=y
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0x300000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6sx-softing-vining-2000"
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_MIPS=y
CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x04e000
CONFIG_ENV_SECT_SIZE=0x1000
-CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DEFAULT_DEVICE_TREE="vocore_vocore2"
CONFIG_SYS_BOOTCOUNT_ADDR=0xb000006c
CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
+CONFIG_SPL_OS_BOOT=y
CONFIG_CMD_SPL=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-wandboard-revd1"
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_ARM=y
CONFIG_ARCH_MX7=y
+CONFIG_SYS_MALLOC_LEN=0x2300000
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0xa0000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x80000
-CONFIG_SYS_MALLOC_LEN=0x2300000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7s-warp"
CONFIG_TARGET_WARP7=y
CONFIG_ARM=y
CONFIG_ARCH_MX7=y
+CONFIG_SYS_MALLOC_LEN=0x2300000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0xa0000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
-CONFIG_SYS_MALLOC_LEN=0x2300000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7s-warp"
CONFIG_OPTEE_TZDRAM_SIZE=0x3000000
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_SYS_MALLOC_LEN=0x2300000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x60000
CONFIG_TARGET_WARP=y
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_MALLOC_LEN=0x2300000
# CONFIG_CMD_BMODE is not set
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=3
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_LPC32XX=y
CONFIG_SYS_TEXT_BASE=0x80100000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_CMD_MAX6957=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x100000
-CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_TEXT_BASE=0x00000000
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00800000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_X530=y
CONFIG_ENV_SIZE=0x10000
CONFIG_SILENT_CONSOLE=y
CONFIG_SILENT_U_BOOT_ONLY=y
CONFIG_SILENT_CONSOLE_UPDATE_ON_RELOC=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_POSITION_INDEPENDENT=y
CONFIG_TARGET_XENGUEST_ARM64=y
CONFIG_SYS_TEXT_BASE=0x40080000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_IDENT_STRING=" xenguest"
CONFIG_SYS_LOAD_ADDR=0x40000000
CONFIG_BOOTDELAY=10
# CONFIG_MMC is not set
# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
CONFIG_DM_SERIAL=y
-# CONFIG_EFI_LOADER is not set
CONFIG_SYS_ICACHE_OFF=y
CONFIG_ARCH_VERSAL=y
CONFIG_SYS_TEXT_BASE=0xFFFC0000
+CONFIG_SYS_MALLOC_LEN=0x2000
CONFIG_NR_DRAM_BANKS=3
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_MEMTEST_END=0x00001000
CONFIG_ENV_SIZE=0x80
-CONFIG_SYS_MALLOC_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="versal-mini"
CONFIG_SYS_MEM_RSVD_FOR_MMU=y
CONFIG_COUNTER_FREQUENCY=100000000
CONFIG_SYS_ICACHE_OFF=y
CONFIG_ARCH_VERSAL=y
CONFIG_SYS_TEXT_BASE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x80
-CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DEFAULT_DEVICE_TREE="versal-mini-emmc0"
CONFIG_COUNTER_FREQUENCY=100000000
# CONFIG_PSCI_RESET is not set
CONFIG_SYS_ICACHE_OFF=y
CONFIG_ARCH_VERSAL=y
CONFIG_SYS_TEXT_BASE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x80
-CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DEFAULT_DEVICE_TREE="versal-mini-emmc1"
CONFIG_COUNTER_FREQUENCY=100000000
# CONFIG_PSCI_RESET is not set
CONFIG_SYS_ICACHE_OFF=y
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0xFFFC0000
+CONFIG_SYS_MALLOC_LEN=0x1a00
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_MEMTEST_END=0x00001000
CONFIG_ENV_SIZE=0x80
-CONFIG_SYS_MALLOC_LEN=0x1a00
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini"
CONFIG_SYS_MEM_RSVD_FOR_MMU=y
CONFIG_ZYNQMP_PSU_INIT_ENABLED=y
CONFIG_SYS_ICACHE_OFF=y
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_SYS_MALLOC_F_LEN=0x1000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x80
-CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-emmc0"
CONFIG_SPL_SYS_MALLOC_F_LEN=0x600
CONFIG_SPL=y
CONFIG_SYS_ICACHE_OFF=y
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_SYS_MALLOC_F_LEN=0x1000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x80
-CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-emmc1"
CONFIG_SPL_SYS_MALLOC_F_LEN=0x600
CONFIG_SPL=y
CONFIG_SYS_ICACHE_OFF=y
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x80
-CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-nand"
# CONFIG_CMD_ZYNQMP is not set
CONFIG_SYS_LOAD_ADDR=0x8000000
CONFIG_SYS_ICACHE_OFF=y
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x80
-CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-nand"
# CONFIG_CMD_ZYNQMP is not set
CONFIG_SYS_LOAD_ADDR=0x8000000
CONFIG_SYS_ICACHE_OFF=y
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0xFFFC0000
+CONFIG_SYS_MALLOC_LEN=0x1a00
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x80
-CONFIG_SYS_MALLOC_LEN=0x1a00
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-qspi"
CONFIG_SPL=y
CONFIG_SYS_MEM_RSVD_FOR_MMU=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ZYNQMP_R5=y
CONFIG_SYS_TEXT_BASE=0x10000000
+CONFIG_SYS_MALLOC_LEN=0x1400000
CONFIG_SYS_MALLOC_F_LEN=0x1000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x1400000
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-r5"
CONFIG_DEBUG_UART_BASE=0xff010000
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_POSITION_INDEPENDENT=y
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_SYS_MALLOC_LEN=0x4040000
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_MEMTEST_END=0x00001000
-CONFIG_SYS_MALLOC_LEN=0x4040000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu100-revC"
CONFIG_SPL_STACK_R_ADDR=0x18000000
CONFIG_DFU_TFTP=y
CONFIG_DFU_TIMEOUT=y
CONFIG_DFU_MMC=y
+CONFIG_DFU_MTD=y
CONFIG_DFU_NAND=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
-CONFIG_DFU_MTD=y
CONFIG_SET_DFU_ALT_INFO=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1800000
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_XTENSA=y
CONFIG_SYS_CPU="dc233c"
+CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_XTFPGA_KC705=y
CONFIG_SYS_LOAD_ADDR=0x02000000
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x100000
-CONFIG_ENV_SIZE=0x190
CONFIG_SYS_MALLOC_LEN=0x8000
+CONFIG_ENV_SIZE=0x190
CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-nand"
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_SPL=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0xFFFC0000
-CONFIG_ENV_SIZE=0x190
CONFIG_SYS_MALLOC_LEN=0x1000
+CONFIG_ENV_SIZE=0x190
CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-nor"
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_SPL=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0xFFFC0000
-CONFIG_ENV_SIZE=0x190
CONFIG_SYS_MALLOC_LEN=0x1000
+CONFIG_ENV_SIZE=0x190
CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-qspi-single"
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_SPL=y
+++ /dev/null
-AMCC suggested to set the PMU bit to 0 for best performace on the
-PPC440 DDR controller. The 440er common DDR setup files (sdram.c &
-spd_sdram.c) are changed accordingly. So all 440er boards using
-these setup routines will automatically receive this performance
-increase.
-
-Please see below some benchmarks done by AMCC to demonstrate this
-performance changes:
-
-
-----------------------------------------
-SDRAM0_CFG0[PMU] = 1 (U-Boot default for Bamboo, Yosemite and Yellowstone)
-----------------------------------------
-Stream benchmark results
--------------------------------------------------------------
-This system uses 8 bytes per DOUBLE PRECISION word.
--------------------------------------------------------------
-Array size = 2000000, Offset = 0
-Total memory required = 45.8 MB.
-Each test is run 10 times, but only
-the *best* time for each is used.
--------------------------------------------------------------
-Your clock granularity/precision appears to be 1 microseconds.
-Each test below will take on the order of 112345 microseconds.
- (= 112345 clock ticks)
-Increase the size of the arrays if this shows that you are not getting
-at least 20 clock ticks per test.
--------------------------------------------------------------
-WARNING -- The above is only a rough guideline.
-For best results, please be sure you know the precision of your system
-timer.
--------------------------------------------------------------
-Function Rate (MB/s) RMS time Min time Max time
-Copy: 256.7683 0.1248 0.1246 0.1250
-Scale: 246.0157 0.1302 0.1301 0.1302
-Add: 255.0316 0.1883 0.1882 0.1885
-Triad: 253.1245 0.1897 0.1896 0.1899
-
-
-TTCP Benchmark Results
-ttcp-t: socket
-ttcp-t: connect
-ttcp-t: buflen=8192, nbuf=2048, align=16384/0, port=5000 tcp ->
-localhost
-ttcp-t: 16777216 bytes in 0.28 real seconds = 454.29 Mbit/sec +++
-ttcp-t: 2048 I/O calls, msec/call = 0.14, calls/sec = 7268.57
-ttcp-t: 0.0user 0.1sys 0:00real 60% 0i+0d 0maxrss 0+2pf 3+1506csw
-
-----------------------------------------
-SDRAM0_CFG0[PMU] = 0 (Suggested modification)
-Setting PMU = 0 provides a noticeable performance improvement *2% to
-5% improvement in memory performance.
-*Improves the Mbit/sec for TTCP benchmark by almost 76%.
-----------------------------------------
-Stream benchmark results
--------------------------------------------------------------
-This system uses 8 bytes per DOUBLE PRECISION word.
--------------------------------------------------------------
-Array size = 2000000, Offset = 0
-Total memory required = 45.8 MB.
-Each test is run 10 times, but only
-the *best* time for each is used.
--------------------------------------------------------------
-Your clock granularity/precision appears to be 1 microseconds.
-Each test below will take on the order of 120066 microseconds.
- (= 120066 clock ticks)
-Increase the size of the arrays if this shows that you are not getting
-at least 20 clock ticks per test.
--------------------------------------------------------------
-WARNING -- The above is only a rough guideline.
-For best results, please be sure you know the precision of your system
-timer.
--------------------------------------------------------------
-Function Rate (MB/s) RMS time Min time Max time
-Copy: 262.5167 0.1221 0.1219 0.1223
-Scale: 258.4856 0.1238 0.1238 0.1240
-Add: 262.5404 0.1829 0.1828 0.1831
-Triad: 266.8594 0.1800 0.1799 0.1802
-
-TTCP Benchmark Results
-ttcp-t: socket
-ttcp-t: connect
-ttcp-t: buflen=8192, nbuf=2048, align=16384/0, port=5000 tcp ->
-localhost
-ttcp-t: 16777216 bytes in 0.16 real seconds = 804.06 Mbit/sec +++
-ttcp-t: 2048 I/O calls, msec/call = 0.08, calls/sec = 12864.89
-ttcp-t: 0.0user 0.0sys 0:00real 46% 0i+0d 0maxrss 0+2pf 120+1csw
-
-
-2006-07-28, Stefan Roese <sr@denx.de>
+++ /dev/null
----------------------------------------------------------------------
-Cleanup of AMCC eval boards (Walnut/Sycamore, Bubinga, Ebony, Ocotea)
----------------------------------------------------------------------
-
-Changes to all AMCC eval boards:
---------------------------------
-
-o Changed u-boot image size to 256 kBytes instead of 512 kBytes on most
- boards.
-
-o Use 115200 baud as default console baudrate.
-
-o Added config option to use redundant environment in flash. This is also
- the default setting. Option for environment in nvram is still available
- for backward compatibility.
-
-o Merged board specific flash drivers to common flash driver:
- board/amcc/common/flash.c
-
-
-Sycamore/Walnut (one port supporting both eval boards):
--------------------------------------------------------
-
-o Cleanup to allow easier "cloning" for different (custom) boards:
-
- o Moved EBC configuration from board specific asm-file "init.S"
- using defines in board configuration file. No board specific
- asm file needed anymore.
-
-
-August 01 2005, Stefan Roese <sr@denx.de>
--------------------------
These changes implement the bedbug (emBEDded deBUGger) debugger in U-Boot.
-A specific implementation is made for the AMCC 405 processor but other flavors
-can be easily implemented.
#####################
### Modifications ###
./common/Makefile
Included cmd_bedbug.c and bedbug.c in the Makefile.
-./common/command.c
- Added bedbug commands to command table.
-
./common/board.c
Added call to initialize debugger on startup.
-./arch/powerpc/cpu/ppc4xx/Makefile
- Added bedbug_405.c to the Makefile.
-
-./arch/powerpc/cpu/ppc4xx/start.S
- Added code to handle the debug exception (0x2000) on the 405.
- Also added code to handle critical exceptions since the debug
- is treated as critical on the 405.
-
-./arch/powerpc/cpu/ppc4xx/traps.c
- Added more detailed output for the program exception to tell
- if it is an illegal instruction, privileged instruction or
- a trap. Also added debug trap handler.
-
./include/ppc_asm.tmpl
Added code to handle critical exceptions
hardware breakpoints and stepping through code. These
routines are common to all PowerPC processors.
-./arch/powerpc/cpu/ppc4xx/bedbug_405.c
- AMCC PPC405 specific debugger routines.
-
-
Bedbug support for the MPC860
-----------------------------
+++ /dev/null
- LYNX KDI SUPPORT
-
- Last Update: July 20, 2003
-=======================================================================
-
-This file describes support for LynuxWorks KDI within U-Boot. Support
-is enabled by defining CONFIG_LYNXKDI.
-
-
-LYNXOS AND BLUECAT SUPPORTED
-============================
-Both LynxOS and BlueCat linux KDIs are supported. The implementation
-automatically detects which is being booted. When you use mkimage
-you should specify "lynxos" for both (see target-specific notes).
-
-
-SUPPORTED ARCHITECTURE/TARGETS
-==============================
-The following targets have been tested:
-
--PowerPC MPC8260ADS
-
-
-FILES TO LOOK AT
-================
-include/lynxkdi.h -defines a simple struct passed to a kdi.
-common/lynxkdi.c -implements the call to the kdi.
-common/cmd_bootm.c -top-level command implementation ("bootm").
-
-
-====================================================================
-TARGET SPECIFIC NOTES
-====================================================================
-
-MPC8260ADS
-===========
-The default LynxOS and BlueCat implementations require some
-modifications to the config file.
-
-Edit include/configs/MPC8260ADS.h to use the following:
-
-#define CONFIG_SYS_IMMR 0xFA200000
-#define CONFIG_SYS_BCSR 0xFA100000
-#define CONFIG_SYS_BR1_PRELIM 0xFA101801
-
-When creating a LynxOS or BlueCat u-boot image using mkimage,
-you must specify the following:
-
-Both: -A ppc -O lynxos -T kernel -C none
-LynxOS: -a 0x00004000 -e 0x00004020
-BlueCat: -a 0x00500000 -e 0x00507000
-
-To pass the MAC address to BlueCat you should define the
-"fcc2_ether_addr" parameter in the "bootargs" environment
-variable. E.g.:
-
-==> setenv bootargs fcc2_ether_addr=00:11:22:33:44:55:66
+++ /dev/null
-This file contains status information for the port of U-Boot to the
-Motorola mpc74xx series of CPUs.
-
-Author: Josh Huber <huber@mclx.com>
- Mission Critical Linux, Inc.
-
-Currently the support for these CPUs is pretty minimal, but enough to
-get things going. (much like the support for the Galileo Eval Board)
-
-There is a framework in place to enable the L2 cache, and to program
-the BATs. Currently, there are still problems with the code which
-sets up the L2 cache, so it's not enabled. (IMHO, it shouldn't be
-anyway). Additionally, there is support for enabling the MMU, which
-we also don't do. The BATs are programmed just for the benefit of
-jumping into Linux in a sane configuration.
-
-Most of the code was based on other cpus supported by U-Boot.
-
-If you find any errors in the CPU setup code, please send us a note.
-
-Thanks,
-Josh
+++ /dev/null
------------------------------
-NAND boot on PPC440 platforms
------------------------------
-
-This document describes the U-Boot NAND boot feature as it
-is implemented for the AMCC Sequoia (PPC440EPx) board.
-
-The PPC440EP(x)/GR(x) cpu's can boot directly from NAND FLASH,
-completely without NOR FLASH. This can be done by using the NAND
-boot feature of the 440 NAND flash controller (NDFC).
-
-Here a short description of the different boot stages:
-
-a) IPL (Initial Program Loader, integrated inside CPU)
-------------------------------------------------------
-Will load first 4k from NAND (SPL) into cache and execute it from there.
-
-b) SPL (Secondary Program Loader)
----------------------------------
-Will load special U-Boot version (NUB) from NAND and execute it. This SPL
-has to fit into 4kByte. It sets up the CPU and configures the SDRAM
-controller and the NAND controller so that the special U-Boot image can be
-loaded from NAND to SDRAM.
-This special image is build in the directory "nand_spl".
-
-c) NUB (NAND U-Boot)
---------------------
-This NAND U-Boot (NUB) is a special U-Boot version which can be started
-from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
-
-On 440EPx the SPL is copied to internal SRAM before the NAND controller
-is set up. While still running from cache, I experienced problems accessing
-the NAND controller.
-
-
-Example: Build and install NAND boot image for Sequoia (440EPx):
-
-a) Configure for sequoia with NAND boot support:
-# make sequoia_nand_config
-
-b) Build image(s)
-# make
-
-This will generate the SPL image in the "nand_spl" directory:
-nand_spl/u-boot-spl.bin
-Also another image is created spanning a whole NAND block (16kBytes):
-nand_spl/u-boot-spl-16k.bin
-The main NAND U-Boot image is generated in the toplevel directory:
-u-boot.bin
-A combined image of u-boot-spl-16k.bin and u-boot.bin is also created:
-u-boot-nand.bin
-
-This image should be programmed at offset 0 in the NAND flash:
-
-# tftp 100000 /tftpboot/sequoia/u-boot-nand.bin
-# nand erase 0 60000
-# nand write 100000 0 60000
-
-
-September 07 2006, Stefan Roese <sr@denx.de>
C API for working with Android Boot Image format
------------------------------------------------
-.. kernel-doc:: common/image-android.c
+.. kernel-doc:: boot/image-android.c
:internal:
References
rng
sandbox
serial
+ sysreset
timer
unicode
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+System reset
+============
+
+.. kernel-doc:: include/sysreset.h
+ :internal:
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+Apple
+=====
+
+.. toctree::
+ :maxdepth: 2
+
+ m1
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for Apple Silicon Macs
+=============================
+
+Allows Apple Silicon Macs to boot U-Boot via the m1n1 bootloader
+developed by the Asahi Linux project. At this point the machines with
+the following SoCs work:
+
+ - Apple M1 SoC
+
+On these SoCs the following hardware is supported:
+
+ - S5L serial port
+ - Framebuffer
+ - USB 3.1 Type-C ports
+
+Device trees are currently provided for the M1 Mac mini (2020, J274)
+and M1 MacBook Pro 13" (2020, J293). The M1 MacBook Air (2020) is
+expected to work with the J293 device tree. The M1 iMac (2021) may
+work with the J274 device tree.
+
+Building U-Boot
+---------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-none-elf-
+ $ make apple_m1_defconfig
+ $ make
+
+This will build ``u-boot-nodtb.bin`` as well as devices trees for some
+of the supported machines. These device trees can be found in the
+``arch/arm/dts`` subdirectory of your build.
+
+Image creation
+--------------
+
+In order to run U-Boot on an Apple Silicon Mac, U-Boot has to be used
+as a payload for the m1n1 bootloader. Instructions for building m1n1
+can be found here:
+
+ https://github.com/AsahiLinux/docs/wiki/SW%3Am1n1
+
+.. code-block:: bash
+
+ $ cat m1n1.macho t8103-j274.dtb u-boot-nodtb.bin > u-boot.macho
+
+This uses ``u-boot-nodtb.bin`` as the device tree is passed to U-Boot
+by m1n1 after making some adjustments.
+
+Image installation
+------------------
+
+Instructions on how to install U-Boot on your Mac can be found at:
+
+ https://github.com/AsahiLinux/docs/wiki/Developer-Quickstart
+
+Just replace ``m1n1.macho`` with ``u-boot.macho`` in the instructions.
These have been tested in QEMU 2.9.0 but should work in at least 2.5.0 as well.
+Enabling TPMv2 support
+----------------------
+
+To emulate a TPM the swtpm package may be used. It can be built from the
+following repositories:
+
+ https://github.com/stefanberger/swtpm.git
+
+Swtpm provides a socket for the TPM emulation which can be consumed by QEMU.
+
+In a first console invoke swtpm with::
+
+ swtpm socket --tpmstate dir=/tmp/mytpm1 \
+ --ctrl type=unixio,path=/tmp/mytpm1/swtpm-sock --log level=20
+
+In a second console invoke qemu-system-aarch64 with::
+
+ -chardev socket,id=chrtpm,path=/tmp/mytpm1/swtpm-sock \
+ -tpmdev emulator,id=tpm0,chardev=chrtpm \
+ -device tpm-tis-device,tpmdev=tpm0
+
+Enable the TPM on U-Boot's command line with::
+
+ tpm2 startup TPM2_SU_CLEAR
+
Debug UART
----------
advantech/index
AndesTech/index
amlogic/index
+ apple/index
atmel/index
congatec/index
coreboot/index
openpiton/index
qualcomm/index
rockchip/index
+ samsung/index
siemens/index
sifive/index
sipeed/index
:maxdepth: 2
sl28
+ sl-mx6ul
+ sl-mx8mm
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+Kontron Electronics SL i.MX6UL/ULL SoM
+======================================
+
+The Kontron SoM-Line i.MX6UL/ULL (N6x1x) by Kontron Electronics GmbH is a SoM module
+with either an i.MX6UL or i.MX6ULL SoC, 256/512 MB DDR3 RAM, SPI NOR, SPI NAND and Ethernet PHY.
+
+The matching evaluation boards (Board-Line) have two Ethernet ports, USB 2.0,
+RGB, SD card, CAN, RS485, RS232 and much more.
+
+Quick Start
+-----------
+
+- Build U-Boot
+- Boot
+
+Build U-Boot
+^^^^^^^^^^^^
+
+.. code-block:: bash
+
+ $ make kontron-sl-mx6ul_defconfig
+ $ make
+
+Burn the flash.bin to SD card at an offset of 1 KiB:
+
+.. code-block:: bash
+
+ $ dd if=flash.bin of=/dev/sd[x] bs=1K seek=1 conv=notrunc
+
+Boot
+^^^^
+
+Put the SD card in the slot on the board and apply power.
+
+Further Information
+-------------------
+
+The bootloader configuration is setup to be used with kernel FIT images. Legacy
+images might not be working out of the box.
+
+Please see https://docs.kontron-electronics.de for further vendor documentation.
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+Kontron Electronics SL i.MX8MM SoM
+==================================
+
+The Kontron SoM-Line i.MX8MM (N801x) by Kontron Electronics GmbH is a SoM module
+with an i.MX8M-Mini SoC, 1/2/4 GB LPDDR4 RAM, SPI NOR, eMMC and PMIC.
+
+The matching evaluation boards (Board-Line) have two Ethernet ports, USB 2.0,
+HDMI/LVDS, SD card, CAN, RS485, RS232 and much more.
+
+Quick Start
+-----------
+
+- Get and Build the Trusted Firmware-A (TF-A)
+- Get the DDR firmware
+- Build U-Boot
+- Boot
+
+Get and Build the Trusted Firmware-A (TF-A)
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Note: builddir is U-Boot build directory (source directory for in-tree builds)
+
+There are two sources for the TF-A. Mainline and NXP. Get the one you prefer
+(support and features might differ).
+
+**NXP's imx-atf**
+
+1. Get TF-A from: https://source.codeaurora.org/external/imx/imx-atf, branch: imx_5.4.70_2.3.0
+2. Apply the patch to select the correct UART for the console, otherwise the TF-A will lock up during boot.
+3. Build
+
+ .. code-block:: bash
+
+ $ make PLAT=imx8mm bl31
+ $ cp build/imx8mm/release/bl31.bin $(builddir)
+
+**Mainline TF-A**
+
+1. Get TF-A from: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/, tag: v2.4
+2. Build
+
+ .. code-block:: bash
+
+ $ make PLAT=imx8mm CROSS_COMPILE=aarch64-linux-gnu- IMX_BOOT_UART_BASE="0x30880000" bl31
+ $ cp build/imx8mm/release/bl31.bin $(builddir)
+
+Get the DDR firmware
+^^^^^^^^^^^^^^^^^^^^
+
+.. code-block:: bash
+
+ $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin
+ $ chmod +x firmware-imx-8.9.bin
+ $ ./firmware-imx-8.9.bin
+ $ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4*.bin $(builddir)
+
+Build U-Boot
+^^^^^^^^^^^^
+
+.. code-block:: bash
+
+ $ make kontron-sl-mx8mm_defconfig
+ $ export ATF_LOAD_ADDR=0x920000
+ $ make
+
+Burn the flash.bin to SD card at an offset of 33 KiB:
+
+.. code-block:: bash
+
+ $ dd if=flash.bin of=/dev/sd[x] bs=1K seek=33 conv=notrunc
+
+Boot
+^^^^
+
+Put the SD card in the slot on the board and apply power.
+
+Further Information
+-------------------
+
+The bootloader configuration is setup to be used with kernel FIT images. Legacy
+images might not be working out of the box.
+
+Please see https://docs.kontron-electronics.de for further vendor documentation.
.. SPDX-License-Identifier: GPL-2.0+
-Summary
-=======
+Kontron SMARC-sAL28
+===================
The Kontron SMARC-sAL28 board is a TSN-enabled dual-core ARM A72
processor module with an on-chip 6-port TSN switch and a 3D GPU.
Quickstart
-==========
+----------
Compile U-Boot
---------------
+^^^^^^^^^^^^^^
Configure and compile the binary::
Copy u-boot.rom to a TFTP server.
Install the bootloader on the board
------------------------------------
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Please note, this bootloader doesn't support the builtin watchdog (yet),
therefore you have to disable it, see below. Otherwise you'll end up in
mode by asserting the ``FORCE_RECOV#`` line during board reset.
Disable the builtin watchdog
-----------------------------
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^
- boot into the failsafe bootloader, either by asserting the
``FORCE_RECOV#`` line or if you still have the original bootloader
- power-cycle the board
+Update image
+------------
+
+After the build finished, there will be an update image called
+u-boot.update. This can either be used in the DFU mode (which isn't
+supported yet) or encapsulated in an EFI UpdateCapsule.
+
+To build the capsule use the following command
+
+ $ tools/mkeficapsule -f u-boot.update -i 1 UpdateUboot
+
+Afterward you can copy this file to your ESP into the /EFI/UpdateCapsule/
+folder. On the next EFI boot this will automatically update your
+bootloader.
+
Useful I2C tricks
-=================
+-----------------
The board has a board management controller which is not supported in
u-boot (yet). But you can use the i2c command to access it.
Non-volatile Board Configuration Bits
-=====================================
+-------------------------------------
The board has 16 configuration bits which are stored in the CPLD and are
non-volatile. These can be changed by the `sl28 nvm` command.
factory defaults, ie. all bits are off.
Power-On Inhibit
-----------------
+^^^^^^^^^^^^^^^^
If this is set, the board doesn't automatically turn on when power is
applied. Instead, the user has to either toggle the ``PWR_BTN#`` line or
use any other wake-up source such as RTC alarm or Wake-on-LAN.
eMMC Boot
----------
+^^^^^^^^^
If this is set, the RCW will be fetched from the on-board eMMC at offset
1MiB. For further details, have a look at the `Reset Configuration Word
Documentation`_.
Watchdog
---------
+^^^^^^^^
By default, the CPLD watchdog is enabled in failsafe mode. Using bits 2 and
3, the user can change its mode or disable it altogether.
===== ===== ===============================
Clock Generator Select
-----------------------
+^^^^^^^^^^^^^^^^^^^^^^
The board is prepared to supply different SerDes clock speeds. But for now,
only setting 0 is supported, otherwise the CPU will hang because the PLL
will not lock.
Clock Output Disable And Keep Devices In Reset
-----------------------------------------------
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
To safe power, the user might disable different devices and clock output of
the board. It is not supported to disable the "CPU SerDes clock #2" for
now, otherwise the CPU will hang because the PLL will not lock.
Automatic reset of the onboard PHYs
------------------------------------
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
By default, there is no hardware reset of the onboard PHY. This is because
for Wake-on-LAN, some registers have to retain their values. If you don't
Further documentation
-=====================
+---------------------
- `Vendor Documentation`_
- `Reset Configuration Word Documentation`_
.. code-block:: bash
$sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=33 conv=notrunc
- $sudo dd if=u-boot.itb of=/dev/sdc bs=1024 seek=384 conv=sync
Boot
----
.. code-block:: bash
$sudo dd if=build/flash.bin of=/dev/sd[x] bs=1K seek=32 conv=notrunc; sync
- $sudo dd if=build/u-boot.itb of=/dev/sd[x] bs=1K seek=384 conv=notrunc; sync
Boot
----
For details on the addition of two numbers in recommended B-copy offset, see
SIT format below.
-+----------+--------------------+-----------------------+-----------------------------+
-| SoC | SIT offset (fixed) | A-copy offset (fixed) | B-copy offset (recommended) |
-+----------+--------------------+-----------------------+-----------------------------+
-| iMX7D | 0x1 | 0x2 | 0x800+0x2 |
-+----------+--------------------+-----------------------+-----------------------------+
-| iMX8MM | 0x41 | 0x42 | 0x1000+0x42 |
-+----------+--------------------+-----------------------+-----------------------------+
++----------+-----------------------------+--------------------+-----------------------+-----------------------------+
+| SoC | Boot Device Type | SIT offset (fixed) | A-copy offset (fixed) | B-copy offset (recommended) |
++----------+-----------------------------+--------------------+-----------------------+-----------------------------+
+| iMX7D | | 0x1 | 0x2 | 0x800+0x2 |
++----------+-----------------------------+--------------------+-----------------------+-----------------------------+
+| iMX8MM | SD/eSD/MMC/eMMC normal boot | 0x41 | 0x42 | 0x1000+0x42 |
++----------+-----------------------------+--------------------+-----------------------+-----------------------------+
+| iMX8MM | eMMC Fast boot fuse blown | 0x1 | 0x2 | 0x1000+0x2 |
++----------+-----------------------------+--------------------+-----------------------+-----------------------------+
SIT format
~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
To perform a reboot into B-copy, the PERSIST_SECONDARY_BOOT must be set
-in SRC_GPR0 register. Example on iMX8MM::
+in SRC_GPR10 register. Example on iMX8MM::
=> mw 0x30390098 0x40000000
:maxdepth: 2
dragonboard410c
+ sdm845
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Dzmitry Sankouski <dsankouski@gmail.com>
+
+Snapdragon 845
+================
+
+About this
+----------
+This document describes the information about Qualcomm Snapdragon 845
+supported boards and it's usage steps.
+
+SDM845 - hi-end qualcomm chip, introduced in late 2017.
+Mostly used in flagship phones and tablets of 2018.
+
+U-Boot can be used as a replacement for Qualcomm's original ABL (UEFI) bootloader.
+It is loaded as an Android boot image through ABL
+
+Installation
+------------
+First, setup ``CROSS_COMPILE`` for aarch64. Then, build U-Boot for your board::
+
+ $ export CROSS_COMPILE=<aarch64 toolchain prefix>
+ $ make <your board name here, see Boards section>_defconfig
+ $ make
+
+This will build ``u-boot.bin`` in the configured output directory.
+
+Boards
+------------
+starqlte
+^^^^^^^^^^^^
+
+The starqltechn is a production board for Samsung S9 (SM-G9600) phone,
+based on the Qualcomm SDM845 SoC.
+
+More information can be found on the `Samsung S9 page`_.
+
+.. _Samsung S9 page: https://en.wikipedia.org/wiki/Samsung_Galaxy_S9
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Dzmitry Sankouski <dsankouski@gmail.com>
+
+Samsung 2017 A series phones
+============================
+
+About this
+----------
+This document describes the information about Samsung A(7/5/3) 2017 midrange
+phones and u-boot usage steps.
+
+U-Boot can be used as a chain-loaded bootloader to replace Samsung's original SBOOT bootloader.
+It is loaded as an Android boot image through SBOOT.
+
+Phone specs
+-----------
+A3 (SM-320) (a3y17lte)
+^^^^^^^^^^^^^^^^^^^^^^
+- 4.7 AMOLED display
+- Exynos 7870 SoC
+- 16GB flash
+- 2GB RAM
+
+.. A3 2017 wiki page: https://en.wikipedia.org/wiki/Samsung_Galaxy_A3_(2017)
+
+A5 (SM-520) (a5y17lte)
+^^^^^^^^^^^^^^^^^^^^^^
+- 5.2 AMOLED display
+- Exynos 7880 SoC
+- 32GB flash
+- 3GB RAM
+
+.. A5 2017 wiki page: https://en.wikipedia.org/wiki/Samsung_Galaxy_A5_(2017)
+
+A7 (SM-720) (a5y17lte)
+^^^^^^^^^^^^^^^^^^^^^^
+- 5.7 AMOLED display
+- Exynos 7880 SoC
+- 32GB flash
+- 3GB RAM
+
+.. A7 2017 wiki page: https://en.wikipedia.org/wiki/Samsung_Galaxy_A7_(2017)
+
+Installation
+------------
+
+Building u-boot
+^^^^^^^^^^^^^^^
+
+First, setup ``CROSS_COMPILE`` for aarch64.
+Then, build U-Boot for your phone, for example ``a5y17lte``::
+
+ $ export CROSS_COMPILE=<aarch64 toolchain prefix>
+ $ make a5y17lte_defconfig
+ $ make
+
+This will build ``u-boot.bin`` in the configured output directory.
+
+Payload
+^^^^^^^
+What is a payload?
+""""""""""""""""""
+A payload file is a file to be used instead of linux kernel in android boot image.
+This file will be loaded into memory, and executed by SBOOT,
+and is therefore SBOOT's payload.
+It may be pure u-boot (with loading u-boot's payload from flash in mind),
+or u-boot + u-boot's payload.
+
+It should be kept in mind, that SBOOT binary patches it's payload after loading
+in address range 0x401f8550-0x401f9280. Given SBOOT loads payload to 0x40001000,
+a range of 0x1f7550-0x1f8280 (2061648-2065024) in a payload file
+will be corrupted after loading to RAM.
+
+Creating payload file
+"""""""""""""""""""""
+- Assemble FIT image for your kernel
+- Create a file for u-boot payload ``touch sboot-payload``
+- Write zeroes till 0x200000 address to be sure SBOOT won't corrupt your info
+ ``dd if=/dev/zero of=sboot-payload bs=$((0x200000)) count=1``
+- Write u-boot to the start of the payload ``dd if=<u-boot.bin path> of=sboot-payload``
+- Write FIT image to payload from 0x200000 address
+ ``dd if=<FIT image path> of=sboot-payload seek=1 bs=2M``
+
+Creating android boot image
+"""""""""""""""""""""""""""
+Once payload created, it's time for android image::
+
+ mkbootimg --base 0x40000000 --kernel_offset 0x00000000 --ramdisk_offset 0x01000000 --tags_offset 0x00000100 --pagesize 2048 --second_offset 0x00f00000 --kernel <sboot-payload path> -o uboot.img
+
+Note, that stock Samsung bootloader ignores offsets, set in mkbootimg.
+
+Flashing
+""""""""
+Flash like regular android boot image.
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+Samsung
+========
+
+.. toctree::
+ :maxdepth: 2
+
+ axy17lte
.. code-block:: bash
$ cd ..
- $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.4.1.bin
- $ chmod +x firmware-imx-8.4.1.bin
- $ ./firmware-imx-8.4.1.bin
- $ cp firmware-imx-8.4.1/firmware/ddr/synopsys/lpddr4*.bin ./
+ $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.10.1.bin
+ $ chmod +x firmware-imx-8.10.1.bin
+ $ ./firmware-imx-8.10.1.bin
+ $ cp firmware-imx-8.10.1/firmware/ddr/synopsys/lpddr4*.bin ./
Build U-Boot
------------
$ export CROSS_COMPILE=aarch64-linux-gnu-
$ export ATF_LOAD_ADDR=0x920000
$ make verdin-imx8mm_defconfig
- $ make flash.bin
+ $ make
Flash to eMMC
-------------
.. code-block:: bash
- U-Boot SPL 2020.01-00187-gd411d164e5 (Jan 26 2020 - 04:47:26 +0100)
- Normal Boot
- Trying to boot from MMC1
-
- U-Boot 2020.01-00187-gd411d164e5 (Jan 26 2020 - 04:47:26 +0100)
-
- CPU: Freescale i.MX8MMQ rev1.0 at 0 MHz
- Reset cause: POR
- DRAM: 2 GiB
- MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
- Loading Environment from MMC... OK
- In: serial
- Out: serial
- Err: serial
- Model: Toradex Verdin iMX8M Mini Quad 2GB Wi-Fi / BT IT V1.0A, Serial:
- Net: eth0: ethernet@30be0000
- Hit any key to stop autoboot: 0
- Verdin iMX8MM #
+U-Boot SPL 2021.10-rc2-00028-gee010ba1129 (Aug 23 2021 - 16:56:02 +0200)
+Normal Boot
+WDT: Started with servicing (60s timeout)
+Trying to boot from MMC1
+NOTICE: BL31: v2.2(release):rel_imx_5.4.70_2.3.2_rc1-5-g835a8f67b
+NOTICE: BL31: Built : 18:02:12, Aug 16 2021
+
+
+U-Boot 2021.10-rc2-00028-gee010ba1129 (Aug 23 2021 - 16:56:02 +0200)
+
+CPU: Freescale i.MX8MMQ rev1.0 at 1200 MHz
+Reset cause: POR
+DRAM: 2 GiB
+WDT: Started with servicing (60s timeout)
+MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
+Loading Environment from MMC... OK
+In: serial
+Out: serial
+Err: serial
+Model: Toradex Verdin iMX8M Mini Quad 2GB Wi-Fi / BT IT V1.1A, Serial# 06760554
+Carrier: Toradex Verdin Development Board V1.1A, Serial# 10754333
+Setting variant to wifi
+Net: eth0: ethernet@30be0000
+Hit any key to stop autoboot: 0
+Verdin iMX8MM #
device-tree-compiler dfu-util efitools flex gdisk graphviz imagemagick \
liblz4-tool libguestfs-tools libncurses-dev libpython3-dev libsdl2-dev \
libssl-dev lz4 lzma lzma-alone openssl pkg-config python3 \
- python3-coverage python3-pycryptodome python3-pyelftools python3-pytest \
- python3-sphinxcontrib.apidoc python3-sphinx-rtd-theme python3-virtualenv \
- swig
+ python3-coverage python3-pkg-resources python3-pycryptodome \
+ python3-pyelftools python3-pytest python3-sphinxcontrib.apidoc \
+ python3-sphinx-rtd-theme python3-virtualenv swig
SUSE based
~~~~~~~~~~
devicetree at runtime, for example if an earlier bootloader stage creates
it and passes it to U-Boot.
-If CONFIG_OF_HOSTFILE is defined, then it will be read from a file on
-startup. This is only useful for sandbox. Use the -d flag to U-Boot to
-specify the file to read, -D for the default and -T for the test devicetree,
-used to run sandbox unit tests.
+If CONFIG_SANDBOX is defined, then it will be read from a file on
+startup. Use the -d flag to U-Boot to specify the file to read, -D for the
+default and -T for the test devicetree, used to run sandbox unit tests.
You cannot use more than one of these options at the same time.
-SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2014 Red Hat Inc.
- * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
- * Copyright (C) 2015 K. Merker <merker@debian.org>
- */
+.. SPDX-License-Identifier: GPL-2.0+
Generic Distro Configuration Concept
====================================
The standard format for boot configuration files is that of extlinux.conf, as
handled by U-Boot's "syslinux" (disk) or "pxe boot" (network). This is roughly
-as specified at:
+as specified at BootLoaderSpec_:
-http://www.freedesktop.org/wiki/Specifications/BootLoaderSpec/
... with the exceptions that the BootLoaderSpec document:
* Does not document the fdtdir option, which automatically selects the DTB to
pass to the kernel.
-One example extlinux.conf generated by the Fedora installer is:
+One example extlinux.conf generated by the Fedora installer is::
-------------------------------------------------------------
-# extlinux.conf generated by anaconda
+ # extlinux.conf generated by anaconda
-ui menu.c32
+ ui menu.c32
-menu autoboot Welcome to Fedora. Automatic boot in # second{,s}. Press a key for options.
-menu title Fedora Boot Options.
-menu hidden
+ menu autoboot Welcome to Fedora. Automatic boot in # second{,s}. Press a key for options.
+ menu title Fedora Boot Options.
+ menu hidden
-timeout 50
-#totaltimeout 9000
+ timeout 50
+ #totaltimeout 9000
-default Fedora (3.17.0-0.rc4.git2.1.fc22.armv7hl+lpae) 22 (Rawhide)
+ default Fedora (3.17.0-0.rc4.git2.1.fc22.armv7hl+lpae) 22 (Rawhide)
-label Fedora (3.17.0-0.rc4.git2.1.fc22.armv7hl) 22 (Rawhide)
- kernel /boot/vmlinuz-3.17.0-0.rc4.git2.1.fc22.armv7hl
- append ro root=UUID=8eac677f-8ea8-4270-8479-d5ddbb797450 console=ttyS0,115200n8 LANG=en_US.UTF-8 drm.debug=0xf
- fdtdir /boot/dtb-3.17.0-0.rc4.git2.1.fc22.armv7hl
- initrd /boot/initramfs-3.17.0-0.rc4.git2.1.fc22.armv7hl.img
+ label Fedora (3.17.0-0.rc4.git2.1.fc22.armv7hl) 22 (Rawhide)
+ kernel /boot/vmlinuz-3.17.0-0.rc4.git2.1.fc22.armv7hl
+ append ro root=UUID=8eac677f-8ea8-4270-8479-d5ddbb797450 console=ttyS0,115200n8 LANG=en_US.UTF-8 drm.debug=0xf
+ fdtdir /boot/dtb-3.17.0-0.rc4.git2.1.fc22.armv7hl
+ initrd /boot/initramfs-3.17.0-0.rc4.git2.1.fc22.armv7hl.img
-label Fedora (3.17.0-0.rc4.git2.1.fc22.armv7hl+lpae) 22 (Rawhide)
- kernel /boot/vmlinuz-3.17.0-0.rc4.git2.1.fc22.armv7hl+lpae
- append ro root=UUID=8eac677f-8ea8-4270-8479-d5ddbb797450 console=ttyS0,115200n8 LANG=en_US.UTF-8 drm.debug=0xf
- fdtdir /boot/dtb-3.17.0-0.rc4.git2.1.fc22.armv7hl+lpae
- initrd /boot/initramfs-3.17.0-0.rc4.git2.1.fc22.armv7hl+lpae.img
+ label Fedora (3.17.0-0.rc4.git2.1.fc22.armv7hl+lpae) 22 (Rawhide)
+ kernel /boot/vmlinuz-3.17.0-0.rc4.git2.1.fc22.armv7hl+lpae
+ append ro root=UUID=8eac677f-8ea8-4270-8479-d5ddbb797450 console=ttyS0,115200n8 LANG=en_US.UTF-8 drm.debug=0xf
+ fdtdir /boot/dtb-3.17.0-0.rc4.git2.1.fc22.armv7hl+lpae
+ initrd /boot/initramfs-3.17.0-0.rc4.git2.1.fc22.armv7hl+lpae.img
-label Fedora-0-rescue-8f6ba7b039524e0eb957d2c9203f04bc (0-rescue-8f6ba7b039524e0eb957d2c9203f04bc)
- kernel /boot/vmlinuz-0-rescue-8f6ba7b039524e0eb957d2c9203f04bc
- initrd /boot/initramfs-0-rescue-8f6ba7b039524e0eb957d2c9203f04bc.img
- append ro root=UUID=8eac677f-8ea8-4270-8479-d5ddbb797450 console=ttyS0,115200n8
- fdtdir /boot/dtb-3.16.0-0.rc6.git1.1.fc22.armv7hl+lpae
-------------------------------------------------------------
+ label Fedora-0-rescue-8f6ba7b039524e0eb957d2c9203f04bc (0-rescue-8f6ba7b039524e0eb957d2c9203f04bc)
+ kernel /boot/vmlinuz-0-rescue-8f6ba7b039524e0eb957d2c9203f04bc
+ initrd /boot/initramfs-0-rescue-8f6ba7b039524e0eb957d2c9203f04bc.img
+ append ro root=UUID=8eac677f-8ea8-4270-8479-d5ddbb797450 console=ttyS0,115200n8
+ fdtdir /boot/dtb-3.16.0-0.rc6.git1.1.fc22.armv7hl+lpae
-Another hand-crafted network boot configuration file is:
-------------------------------------------------------------
-TIMEOUT 100
+Another hand-crafted network boot configuration file is::
-MENU TITLE TFTP boot options
+ TIMEOUT 100
-LABEL jetson-tk1-emmc
- MENU LABEL ../zImage root on Jetson TK1 eMMC
- LINUX ../zImage
- FDTDIR ../
- APPEND console=ttyS0,115200n8 console=tty1 loglevel=8 rootwait rw earlyprintk root=PARTUUID=80a5a8e9-c744-491a-93c1-4f4194fd690b
+ MENU TITLE TFTP boot options
-LABEL venice2-emmc
- MENU LABEL ../zImage root on Venice2 eMMC
- LINUX ../zImage
- FDTDIR ../
- APPEND console=ttyS0,115200n8 console=tty1 loglevel=8 rootwait rw earlyprintk root=PARTUUID=5f71e06f-be08-48ed-b1ef-ee4800cc860f
+ LABEL jetson-tk1-emmc
+ MENU LABEL ../zImage root on Jetson TK1 eMMC
+ LINUX ../zImage
+ FDTDIR ../
+ APPEND console=ttyS0,115200n8 console=tty1 loglevel=8 rootwait rw earlyprintk root=PARTUUID=80a5a8e9-c744-491a-93c1-4f4194fd690b
-LABEL sdcard
- MENU LABEL ../zImage, root on 2GB sdcard
- LINUX ../zImage
- FDTDIR ../
- APPEND console=ttyS0,115200n8 console=tty1 loglevel=8 rootwait rw earlyprintk root=PARTUUID=b2f82cda-2535-4779-b467-094a210fbae7
+ LABEL venice2-emmc
+ MENU LABEL ../zImage root on Venice2 eMMC
+ LINUX ../zImage
+ FDTDIR ../
+ APPEND console=ttyS0,115200n8 console=tty1 loglevel=8 rootwait rw earlyprintk root=PARTUUID=5f71e06f-be08-48ed-b1ef-ee4800cc860f
-LABEL fedora-installer-fk
- MENU LABEL Fedora installer w/ Fedora kernel
- LINUX fedora-installer/vmlinuz
- INITRD fedora-installer/initrd.img.orig
- FDTDIR fedora-installer/dtb
- APPEND loglevel=8 ip=dhcp inst.repo=http://10.0.0.2/mirrors/fedora/linux/development/rawhide/armhfp/os/ rd.shell cma=64M
-------------------------------------------------------------
+ LABEL sdcard
+ MENU LABEL ../zImage, root on 2GB sdcard
+ LINUX ../zImage
+ FDTDIR ../
+ APPEND console=ttyS0,115200n8 console=tty1 loglevel=8 rootwait rw earlyprintk root=PARTUUID=b2f82cda-2535-4779-b467-094a210fbae7
+
+ LABEL fedora-installer-fk
+ MENU LABEL Fedora installer w/ Fedora kernel
+ LINUX fedora-installer/vmlinuz
+ INITRD fedora-installer/initrd.img.orig
+ FDTDIR fedora-installer/dtb
+ APPEND loglevel=8 ip=dhcp inst.repo=http://10.0.0.2/mirrors/fedora/linux/development/rawhide/armhfp/os/ rd.shell cma=64M
U-Boot Implementation
=====================
from Kconfig itself, for e.g. all boards using a specific SoC then
add a "imply DISTRO_DEFAULTS" to your SoC CONFIG option.
-In your board configuration file, include the following:
+In your board configuration file, include the following::
-------------------------------------------------------------
-#ifndef CONFIG_SPL_BUILD
-#include <config_distro_bootcmd.h>
-#endif
-------------------------------------------------------------
+ #ifndef CONFIG_SPL_BUILD
+ #include <config_distro_bootcmd.h>
+ #endif
The first of those headers primarily enables a core set of U-Boot features,
such as support for MBR and GPT partitions, ext* and FAT filesystems, booting
the user doesn't have to configure them.
fdt_addr:
-
Mandatory for any system that provides the DTB in HW (e.g. ROM) and wishes
to pass that DTB to Linux, rather than loading a DTB from the boot
filesystem. Prohibited for any other system.
address.
fdt_addr_r:
-
Mandatory. The location in RAM where the DTB will be loaded or copied to when
processing the fdtdir/devicetreedir or fdt/devicetree options in
extlinux.conf.
A size of 1MB for the FDT/DTB seems reasonable.
fdtfile:
-
Mandatory. the name of the DTB file for the specific board for instance
the espressobin v5 board the value is "marvell/armada-3720-espressobin.dtb"
while on a clearfog pro it is "armada-388-clearfog-pro.dtb" in the case of
SoC vendor directories.
ramdisk_addr_r:
-
Mandatory. The location in RAM where the initial ramdisk will be loaded to
when processing the initrd option in extlinux.conf.
- It is recommended that this location be highest in RAM out of fdt_addr_,
+ It is recommended that this location be highest in RAM out of fdt_addr_r,
kernel_addr_r, and ramdisk_addr_r, so that the RAM disk can vary in size
and use any available RAM.
kernel_addr_r:
-
Mandatory. The location in RAM where the kernel will be loaded to when
processing the kernel option in the extlinux.conf.
size has to at least the size of loaded image for decompression to succeed.
pxefile_addr_r:
-
Mandatory. The location in RAM where extlinux.conf will be loaded to prior
to processing.
A size of 1MB for extlinux.conf is more than adequate.
scriptaddr:
-
Mandatory, if the boot script is boot.scr rather than extlinux.conf. The
location in RAM where boot.scr will be loaded to prior to execution.
Boot Target Configuration
-------------------------
-<config_distro_bootcmd.h> defines $bootcmd and many helper command variables
-that automatically search attached disks for boot configuration files and
-execute them. Boards must provide configure <config_distro_bootcmd.h> so that
-it supports the correct set of possible boot device types. To provide this
+The `config_distro_bootcmd.h` file defines $bootcmd and many helper command
+variables that automatically search attached disks for boot configuration files
+and execute them. Boards must provide configure <config_distro_bootcmd.h> so
+that it supports the correct set of possible boot device types. To provide this
configuration, simply define macro BOOT_TARGET_DEVICES prior to including
-<config_distro_bootcmd.h>. For example:
-
-------------------------------------------------------------
-#ifndef CONFIG_SPL_BUILD
-#define BOOT_TARGET_DEVICES(func) \
- func(MMC, mmc, 1) \
- func(MMC, mmc, 0) \
- func(USB, usb, 0) \
- func(PXE, pxe, na) \
- func(DHCP, dhcp, na)
-#include <config_distro_bootcmd.h>
-#endif
-------------------------------------------------------------
+<config_distro_bootcmd.h>. For example::
+
+ #ifndef CONFIG_SPL_BUILD
+ #define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 1) \
+ func(MMC, mmc, 0) \
+ func(USB, usb, 0) \
+ func(PXE, pxe, na) \
+ func(DHCP, dhcp, na)
+ #include <config_distro_bootcmd.h>
+ #endif
Each entry in the macro defines a single boot device (e.g. a specific eMMC
device or SD card) or type of boot device (e.g. USB disk). The parameters to
be altered to influence the boot process:
boot_targets:
-
The list of boot locations searched.
Example: mmc0, mmc1, usb, pxe
Entries may be removed or re-ordered in this list to affect the boot order.
boot_prefixes:
-
For disk-based booting, the list of directories within a partition that are
searched for boot configuration files (extlinux.conf, boot.scr).
directories which are searched.
boot_scripts:
-
The name of U-Boot style boot.scr files that $bootcmd searches for.
Example: boot.scr.uimg boot.scr
filenames which are supported.
scan_dev_for_extlinux:
-
If you want to disable extlinux.conf on all disks, set the value to something
innocuous, e.g. setenv scan_dev_for_extlinux true.
scan_dev_for_scripts:
-
If you want to disable boot.scr on all disks, set the value to something
innocuous, e.g. setenv scan_dev_for_scripts true.
boot_net_usb_start:
-
If you want to prevent USB enumeration by distro boot commands which execute
network operations, set the value to something innocuous, e.g. setenv
boot_net_usb_start true. This would be useful if you know your Ethernet
avoiding unnecessary actions.
boot_net_pci_enum:
-
If you want to prevent PCI enumeration by distro boot commands which execute
network operations, set the value to something innocuous, e.g. setenv
boot_net_pci_enum true. This would be useful if you know your Ethernet
The list of possible targets consists of:
- network targets
+
* dhcp
* pxe
- storage targets (to which a device number must be appended)
+
* mmc
* sata
* scsi
way in future u-boot versions. In particular the <device type>_boot
variables (e.g. mmc_boot, usb_boot) are a strictly internal implementation
detail and must not be used as a public interface.
+
+.. _BootLoaderSpec: http://www.freedesktop.org/wiki/Specifications/BootLoaderSpec/
+
+.. sectionauthor:: (C) Copyright 2014 Red Hat Inc.
+.. sectionauthor:: Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
+.. sectionauthor:: Copyright (C) 2015 K. Merker <merker@debian.org>
commands
config_binding
devicetree/index
+ distro
driver-model/index
global_data
logging
opt for using QEMU [1] and the OVMF [2], as detailed below.
To build U-Boot as an EFI application (32-bit EFI required), enable CONFIG_EFI
-and CONFIG_EFI_APP. The efi-x86_app config (efi-x86_app_defconfig) is set up
+and CONFIG_EFI_APP. The efi-x86_app config (efi-x86_app32_defconfig) is set up
for this. Just build U-Boot as normal, e.g.::
- make efi-x86_app_defconfig
+ make efi-x86_app32_defconfig
make
To build U-Boot as an EFI payload (32-bit or 64-bit EFI can be used), enable
Trying it out
-------------
QEMU is an emulator and it can emulate an x86 machine. Please make sure your
-QEMU version is 2.3.0 or above to test this. You can run the payload with
+QEMU version is 6.0.0 or above to test this. You can run the payload with
something like this::
mkdir /tmp/efi
cp /path/to/u-boot*.efi /tmp/efi
- qemu-system-x86_64 -bios bios.bin -hda fat:/tmp/efi/
+ qemu-system-x86_64 -pflash edk2-x86_64-code.fd -hda fat:rw:/tmp/efi/
Add -nographic if you want to use the terminal for output. Once it starts
type 'fs0:u-boot-payload.efi' to run the payload or 'fs0:u-boot-app.efi' to
-run the application. 'bios.bin' is the EFI 'BIOS'. Check [2] to obtain a
-prebuilt EFI BIOS for QEMU or you can build one from source as well.
+run the application. 'edk2-x86_64-code.fd' is the EFI 'BIOS'. QEMU already
+ships both 32-bit and 64-bit EFI BIOS images. For 32-bit EFI 'BIOS' image,
+use 'edk2-i386-code.fd'.
+
To try it on real hardware, put u-boot-app.efi on a suitable boot medium,
such as a USB stick. Then you can type something like this to start it::
EFI (or vice versa). Also it will often fail to print an error message if
you get this wrong.
+You may find the script `scripts/build-efi.sh` helpful for building and testing
+U-Boot on UEFI on QEMU. It also includes links to UEFI binaries dating from
+2021.
+
+See `Example run`_ for an example run.
Inner workings
--------------
Everything else is built as a normal U-Boot, so is always 32-bit on x86 at
present.
+Example run
+-----------
+
+This shows running with serial enabled (see `include/configs/efi-x86_app.h`)::
+
+ $ scripts/build-efi.sh -wsPr
+ Packaging efi-x86_app32
+ Running qemu-system-i386
+
+ BdsDxe: failed to load Boot0001 "UEFI QEMU HARDDISK QM00005 " from PciRoot(0x0)/Pci(0x3,0x0)/Sata(0x0,0xFFFF,0x0): Not Found
+ BdsDxe: loading Boot0002 "EFI Internal Shell" from Fv(7CB8BDC9-F8EB-4F34-AAEA-3EE4AF6516A1)/FvFile(7C04A583-9E3E-4F1C-AD65-E05268D0B4D1)
+ BdsDxe: starting Boot0002 "EFI Internal Shell" from Fv(7CB8BDC9-F8EB-4F34-AAEA-3EE4AF6516A1)/FvFile(7C04A583-9E3E-4F1C-AD65-E05268D0B4D1)
+
+ UEFI Interactive Shell v2.2
+ EDK II
+ UEFI v2.70 (EDK II, 0x00010000)
+ Mapping table
+ FS0: Alias(s):HD0a65535a1:;BLK1:
+ PciRoot(0x0)/Pci(0x3,0x0)/Sata(0x0,0xFFFF,0x0)/HD(1,GPT,0FFD5E61-3B0C-4326-8049-BDCDC910AF72,0x800,0xB000)
+ BLK0: Alias(s):
+ PciRoot(0x0)/Pci(0x3,0x0)/Sata(0x0,0xFFFF,0x0)
+
+ Press ESC in 5 seconds to skip startup.nsh or any other key to continue.
+ Shell> fs0:u-boot-app.efi
+ U-Boot EFI App (using allocated RAM address 47d4000) key=8d4, image=06a6f610
+ starting
+
+
+ U-Boot 2022.01-rc4 (Sep 19 2021 - 14:03:20 -0600)
+
+ CPU: x86, vendor Intel, device 663h
+ DRAM: 32 MiB
+ 0: efi_media_0 PciRoot(0x0)/Pci(0x3,0x0)/Sata(0x0,0xFFFF,0x0)
+ 1: <partition> PciRoot(0x0)/Pci(0x3,0x0)/Sata(0x0,0xFFFF,0x0)/HD(1,GPT,0FFD5E61-3B0C-4326-8049-BDCDC910AF72,0x800,0xB000)
+ Loading Environment from nowhere... OK
+ Model: EFI x86 Application
+ Hit any key to stop autoboot: 0
+
+ Partition Map for EFI device 0 -- Partition Type: EFI
+
+ Part Start LBA End LBA Name
+ Attributes
+ Type GUID
+ Partition GUID
+ 1 0x00000800 0x0000b7ff "boot"
+ attrs: 0x0000000000000000
+ type: ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
+ guid: 0ffd5e61-3b0c-4326-8049-bdcdc910af72
+ 19 startup.nsh
+ 528384 u-boot-app.efi
+ 10181 NvVars
+
+ 3 file(s), 0 dir(s)
+
+ => QEMU: Terminated
+
+
Future work
-----------
This work could be extended in a number of ways:
- Add ARM support
-- Add 64-bit application support
+- Add 64-bit application support (in progress)
- Figure out how to solve the interrupt problem
-- Add more drivers to the application side (e.g. video, block devices, USB,
+- Add more drivers to the application side (e.g. block devices, USB,
environment access). This would mostly be an academic exercise as a strong
use case is not readily apparent, but it might be fun.
July 2015
* [1] http://www.qemu.org
-* [2] http://www.tianocore.org/ovmf/
+* [2] https://github.com/tianocore/tianocore.github.io/wiki/OVMF
[1] https://optee.readthedocs.io/en/latest/building/efi_vars/stmm.html
+Enabling UEFI Capsule Update feature
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Support has been added for the UEFI capsule update feature which
+enables updating the U-Boot image using the UEFI firmware management
+protocol (FMP). The capsules are not passed to the firmware through
+the UpdateCapsule runtime service. Instead, capsule-on-disk
+functionality is used for fetching the capsule from the EFI System
+Partition (ESP) by placing the capsule file under the
+\EFI\UpdateCapsule directory.
+
+The directory \EFI\UpdateCapsule is checked for capsules only within the
+EFI system partition on the device specified in the active boot option
+determined by reference to BootNext variable or BootOrder variable processing.
+The active Boot Variable is the variable with highest priority BootNext or
+within BootOrder that refers to a device found to be present. Boot variables
+in BootOrder but referring to devices not present are ignored when determining
+active boot variable.
+Before starting a capsule update make sure your capsules are installed in the
+correct ESP partition or set BootNext.
+
+Performing the update
+*********************
+
+Since U-boot doesn't currently support SetVariable at runtime there's a Kconfig
+option (CONFIG_EFI_IGNORE_OSINDICATIONS) to disable the OsIndications variable
+check. If that option is enabled just copy your capsule to \EFI\UpdateCapsule.
+
+If that option is disabled, you'll need to set the OsIndications variable with::
+
+ => setenv -e -nv -bs -rt -v OsIndications =0x04
+
+Finally, the capsule update can be initiated either by rebooting the board,
+which is the preferred method, or by issuing the following command::
+
+ => efidebug capsule disk-update
+
+**The efidebug command is should only be used during debugging/development.**
+
+Enabling Capsule Authentication
+*******************************
+
+The UEFI specification defines a way of authenticating the capsule to
+be updated by verifying the capsule signature. The capsule signature
+is computed and prepended to the capsule payload at the time of
+capsule generation. This signature is then verified by using the
+public key stored as part of the X509 certificate. This certificate is
+in the form of an efi signature list (esl) file, which is embedded as
+part of U-Boot.
+
+The capsule authentication feature can be enabled through the
+following config, in addition to the configs listed above for capsule
+update::
+
+ CONFIG_EFI_CAPSULE_AUTHENTICATE=y
+ CONFIG_EFI_CAPSULE_KEY_PATH=<path to .esl cert>
+
+The public and private keys used for the signing process are generated
+and used by the steps highlighted below::
+
+ 1. Install utility commands on your host
+ * OPENSSL
+ * efitools
+
+ 2. Create signing keys and certificate files on your host
+
+ $ openssl req -x509 -sha256 -newkey rsa:2048 -subj /CN=CRT/ \
+ -keyout CRT.key -out CRT.crt -nodes -days 365
+ $ cert-to-efi-sig-list CRT.crt CRT.esl
+
+ $ openssl x509 -in CRT.crt -out CRT.cer -outform DER
+ $ openssl x509 -inform DER -in CRT.cer -outform PEM -out CRT.pub.pem
+
+ $ openssl pkcs12 -export -out CRT.pfx -inkey CRT.key -in CRT.crt
+ $ openssl pkcs12 -in CRT.pfx -nodes -out CRT.pem
+
+The capsule file can be generated by using the GenerateCapsule.py
+script in EDKII::
+
+ $ ./BaseTools/BinWrappers/PosixLike/GenerateCapsule -e -o \
+ <capsule_file_name> --monotonic-count <val> --fw-version \
+ <val> --lsv <val> --guid \
+ e2bb9c06-70e9-4b14-97a3-5a7913176e3f --verbose \
+ --update-image-index <val> --signer-private-cert \
+ /path/to/CRT.pem --trusted-public-cert \
+ /path/to/CRT.pub.pem --other-public-cert /path/to/CRT.pub.pem \
+ <u-boot.bin>
+
+Place the capsule generated in the above step on the EFI System
+Partition under the EFI/UpdateCapsule directory
+
+Testing on QEMU
+***************
+
+Currently, support has been added on the QEMU ARM64 virt platform for
+updating the U-Boot binary as a raw image when the platform is booted
+in non-secure mode, i.e. with CONFIG_TFABOOT disabled. For this
+configuration, the QEMU platform needs to be booted with
+'secure=off'. The U-Boot binary placed on the first bank of the NOR
+flash at offset 0x0. The U-Boot environment is placed on the second
+NOR flash bank at offset 0x4000000.
+
+The capsule update feature is enabled with the following configuration
+settings::
+
+ CONFIG_MTD=y
+ CONFIG_FLASH_CFI_MTD=y
+ CONFIG_CMD_MTDPARTS=y
+ CONFIG_CMD_DFU=y
+ CONFIG_DFU_MTD=y
+ CONFIG_PCI_INIT_R=y
+ CONFIG_EFI_CAPSULE_ON_DISK=y
+ CONFIG_EFI_CAPSULE_FIRMWARE_MANAGEMENT=y
+ CONFIG_EFI_CAPSULE_FIRMWARE=y
+ CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+
+In addition, the following config needs to be disabled(QEMU ARM specific)::
+
+ CONFIG_TFABOOT
+
+The capsule file can be generated by using the tools/mkeficapsule::
+
+ $ mkeficapsule --raw <u-boot.bin> --index 1 <capsule_file_name>
+
Executing the boot manager
~~~~~~~~~~~~~~~~~~~~~~~~~~
--- /dev/null
+This document describes the generic device tree binding for IOMMUs and their
+master(s).
+
+
+IOMMU device node:
+==================
+
+An IOMMU can provide the following services:
+
+* Remap address space to allow devices to access physical memory ranges that
+ they otherwise wouldn't be capable of accessing.
+
+ Example: 32-bit DMA to 64-bit physical addresses
+
+* Implement scatter-gather at page level granularity so that the device does
+ not have to.
+
+* Provide system protection against "rogue" DMA by forcing all accesses to go
+ through the IOMMU and faulting when encountering accesses to unmapped
+ address regions.
+
+* Provide address space isolation between multiple contexts.
+
+ Example: Virtualization
+
+Device nodes compatible with this binding represent hardware with some of the
+above capabilities.
+
+IOMMUs can be single-master or multiple-master. Single-master IOMMU devices
+typically have a fixed association to the master device, whereas multiple-
+master IOMMU devices can translate accesses from more than one master.
+
+The device tree node of the IOMMU device's parent bus must contain a valid
+"dma-ranges" property that describes how the physical address space of the
+IOMMU maps to memory. An empty "dma-ranges" property means that there is a
+1:1 mapping from IOMMU to memory.
+
+Required properties:
+--------------------
+- #iommu-cells: The number of cells in an IOMMU specifier needed to encode an
+ address.
+
+The meaning of the IOMMU specifier is defined by the device tree binding of
+the specific IOMMU. Below are a few examples of typical use-cases:
+
+- #iommu-cells = <0>: Single master IOMMU devices are not configurable and
+ therefore no additional information needs to be encoded in the specifier.
+ This may also apply to multiple master IOMMU devices that do not allow the
+ association of masters to be configured. Note that an IOMMU can by design
+ be multi-master yet only expose a single master in a given configuration.
+ In such cases the number of cells will usually be 1 as in the next case.
+- #iommu-cells = <1>: Multiple master IOMMU devices may need to be configured
+ in order to enable translation for a given master. In such cases the single
+ address cell corresponds to the master device's ID. In some cases more than
+ one cell can be required to represent a single master ID.
+- #iommu-cells = <4>: Some IOMMU devices allow the DMA window for masters to
+ be configured. The first cell of the address in this may contain the master
+ device's ID for example, while the second cell could contain the start of
+ the DMA window for the given device. The length of the DMA window is given
+ by the third and fourth cells.
+
+Note that these are merely examples and real-world use-cases may use different
+definitions to represent their individual needs. Always refer to the specific
+IOMMU binding for the exact meaning of the cells that make up the specifier.
+
+
+IOMMU master node:
+==================
+
+Devices that access memory through an IOMMU are called masters. A device can
+have multiple master interfaces (to one or more IOMMU devices).
+
+Required properties:
+--------------------
+- iommus: A list of phandle and IOMMU specifier pairs that describe the IOMMU
+ master interfaces of the device. One entry in the list describes one master
+ interface of the device.
+
+When an "iommus" property is specified in a device tree node, the IOMMU will
+be used for address translation. If a "dma-ranges" property exists in the
+device's parent node it will be ignored. An exception to this rule is if the
+referenced IOMMU is disabled, in which case the "dma-ranges" property of the
+parent shall take effect. Note that merely disabling a device tree node does
+not guarantee that the IOMMU is really disabled since the hardware may not
+have a means to turn off translation. But it is invalid in such cases to
+disable the IOMMU's device tree node in the first place because it would
+prevent any driver from properly setting up the translations.
+
+Optional properties:
+--------------------
+- pasid-num-bits: Some masters support multiple address spaces for DMA, by
+ tagging DMA transactions with an address space identifier. By default,
+ this is 0, which means that the device only has one address space.
+
+- dma-can-stall: When present, the master can wait for a transaction to
+ complete for an indefinite amount of time. Upon translation fault some
+ IOMMUs, instead of aborting the translation immediately, may first
+ notify the driver and keep the transaction in flight. This allows the OS
+ to inspect the fault and, for example, make physical pages resident
+ before updating the mappings and completing the transaction. Such IOMMU
+ accepts a limited number of simultaneous stalled transactions before
+ having to either put back-pressure on the master, or abort new faulting
+ transactions.
+
+ Firmware has to opt-in stalling, because most buses and masters don't
+ support it. In particular it isn't compatible with PCI, where
+ transactions have to complete before a time limit. More generally it
+ won't work in systems and masters that haven't been designed for
+ stalling. For example the OS, in order to handle a stalled transaction,
+ may attempt to retrieve pages from secondary storage in a stalled
+ domain, leading to a deadlock.
+
+
+Notes:
+======
+
+One possible extension to the above is to use an "iommus" property along with
+a "dma-ranges" property in a bus device node (such as PCI host bridges). This
+can be useful to describe how children on the bus relate to the IOMMU if they
+are not explicitly listed in the device tree (e.g. PCI devices). However, the
+requirements of that use-case haven't been fully determined yet. Implementing
+this is therefore not recommended without further discussion and extension of
+this binding.
+
+
+Examples:
+=========
+
+Single-master IOMMU:
+--------------------
+
+ iommu {
+ #iommu-cells = <0>;
+ };
+
+ master {
+ iommus = <&{/iommu}>;
+ };
+
+Multiple-master IOMMU with fixed associations:
+----------------------------------------------
+
+ /* multiple-master IOMMU */
+ iommu {
+ /*
+ * Masters are statically associated with this IOMMU and share
+ * the same address translations because the IOMMU does not
+ * have sufficient information to distinguish between masters.
+ *
+ * Consequently address translation is always on or off for
+ * all masters at any given point in time.
+ */
+ #iommu-cells = <0>;
+ };
+
+ /* static association with IOMMU */
+ master@1 {
+ reg = <1>;
+ iommus = <&{/iommu}>;
+ };
+
+ /* static association with IOMMU */
+ master@2 {
+ reg = <2>;
+ iommus = <&{/iommu}>;
+ };
+
+Multiple-master IOMMU:
+----------------------
+
+ iommu {
+ /* the specifier represents the ID of the master */
+ #iommu-cells = <1>;
+ };
+
+ master@1 {
+ /* device has master ID 42 in the IOMMU */
+ iommus = <&{/iommu} 42>;
+ };
+
+ master@2 {
+ /* device has master IDs 23 and 24 in the IOMMU */
+ iommus = <&{/iommu} 23>, <&{/iommu} 24>;
+ };
+
+Multiple-master IOMMU with configurable DMA window:
+---------------------------------------------------
+
+ / {
+ iommu {
+ /*
+ * One cell for the master ID and one cell for the
+ * address of the DMA window. The length of the DMA
+ * window is encoded in two cells.
+ *
+ * The DMA window is the range addressable by the
+ * master (i.e. the I/O virtual address space).
+ */
+ #iommu-cells = <4>;
+ };
+
+ master {
+ /* master ID 42, 4 GiB DMA window starting at 0 */
+ iommus = <&{/iommu} 42 0 0x1 0x0>;
+ };
+ };
--- /dev/null
+Qualcomm GENI UART
+
+Required properties:
+- compatible: must be "qcom,msm-geni-uart"
+- reg: start address and size of the registers
+- clock: interface clock (must accept baudrate as a frequency)
docutils==0.16
-Sphinx==2.4.4
+Sphinx==3.4.3
sphinx_rtd_theme
six
mode
speed mode to set.
- CONFIG_MMC_SPEED_MODE_SET should be enabled. The required speed mode is
- passed as the index from the following list.
-
- 0 - MMC_LEGACY
- 1 - MMC_HS
- 2 - SD_HS
- 3 - MMC_HS_52
- 4 - MMC_DDR_52
- 5 - UHS_SDR12
- 6 - UHS_SDR25
- 7 - UHS_SDR50
- 8 - UHS_DDR50
- 9 - UHS_SDR104
- 10 - MMC_HS_200
- 11 - MMC_HS_400
- 12 - MMC_HS_400_ES
+ CONFIG_MMC_SPEED_MODE_SET should be enabled. The requested speed mode is
+ passed as a decimal number according to the following table:
+
+ ========== ==========================
+ Speed mode Description
+ ========== ==========================
+ 0 MMC legacy
+ 1 MMC High Speed (26MHz)
+ 2 SD High Speed (50MHz)
+ 3 MMC High Speed (52MHz)
+ 4 MMC DDR52 (52MHz)
+ 5 UHS SDR12 (25MHz)
+ 6 UHS SDR25 (50MHz)
+ 7 UHS SDR50 (100MHz)
+ 8 UHS DDR50 (50MHz)
+ 9 UHS SDR104 (208MHz)
+ 10 HS200 (200MHz)
+ 11 HS400 (200MHz)
+ 12 HS400ES (200MHz)
+ ========== ==========================
A speed mode can be set only if it has already been enabled in the device tree
source "drivers/input/Kconfig"
+source "drivers/iommu/Kconfig"
+
source "drivers/led/Kconfig"
source "drivers/mailbox/Kconfig"
obj-y += pwm/
obj-y += reset/
obj-y += input/
+obj-y += iommu/
# SOC specific infrastructure drivers.
obj-y += smem/
obj-y += thermal/
if (priv->base == FDT_ADDR_T_NONE)
return -EINVAL;
- ret = dev_read_resource_byname(dev, "ecc-addr", &res_regs);
+ ret = dev_read_resource_byname(dev, "sata-ecc", &res_regs);
if (ret)
priv->ecc_base = 0;
else
{
struct sifive_ccache *priv = dev_get_priv(dev);
- info->base = (phys_addr_t)priv->base;
+ info->base = (uintptr_t)priv->base;
return 0;
}
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_TFABOOT
-#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SPL_BUILD)
/* activate clock tree initialization in the driver */
#define STM32MP1_CLOCK_TREE_INIT
#endif
-#endif
#define MAX_HSI_HZ 64000000
struct prci_clk_desc *data =
(struct prci_clk_desc *)dev_get_driver_data(dev);
- pd->va = (void *)dev_read_addr(dev);
- if (IS_ERR(pd->va))
- return PTR_ERR(pd->va);
+ pd->va = dev_read_addr_ptr(dev);
+ if (!pd->va)
+ return -EINVAL;
err = clk_get_by_index(dev, 0, &pd->parent_hfclk);
if (err)
bool "Clock support for Allwinner SoCs"
depends on CLK && ARCH_SUNXI
select DM_RESET
+ select SPL_DM_RESET if SPL_CLK
default y
help
This enables support for common clock driver API on Allwinner
#include <dm/uclass.h>
#include <dm/uclass-internal.h>
#include <dm/util.h>
+#include <iommu.h>
#include <linux/err.h>
#include <linux/list.h>
#include <power-domain.h>
goto fail;
}
+ if (CONFIG_IS_ENABLED(IOMMU) && dev->parent &&
+ (device_get_uclass_id(dev) != UCLASS_IOMMU)) {
+ ret = dev_iommu_enable(dev);
+ if (ret)
+ goto fail;
+ }
+
ret = device_get_dma_constraints(dev);
if (ret)
goto fail;
#endif
}
+void *devfdt_get_addr_index_ptr(const struct udevice *dev, int index)
+{
+ fdt_addr_t addr = devfdt_get_addr_index(dev, index);
+
+ return (addr == FDT_ADDR_T_NONE) ? NULL : (void *)(uintptr_t)addr;
+}
+
fdt_addr_t devfdt_get_addr_size_index(const struct udevice *dev, int index,
fdt_size_t *size)
{
void *devfdt_get_addr_ptr(const struct udevice *dev)
{
- fdt_addr_t addr = devfdt_get_addr_index(dev, 0);
-
- return (addr == FDT_ADDR_T_NONE) ? NULL : (void *)(uintptr_t)addr;
+ return devfdt_get_addr_index_ptr(dev, 0);
}
void *devfdt_remap_addr_index(const struct udevice *dev, int index)
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
- *
+ * Copyright 2021 NXP
*/
#include <common.h>
* Perform progressive hashing on the given buffer and copy hash at
* destination buffer
*
- * The context is freed after completion of hash operation.
- *
+ * The context is freed after successful completion of hash operation.
+ * In case of failure, context is not freed.
* @hash_ctx: Pointer to the context for hashing
* @dest_buf: Pointer to the destination buffer where hash is to be copied
* @size: Size of the buffer being hashed
int i = 0, ret = 0;
if (size < driver_hash[caam_algo].digestsize) {
- free(ctx);
return -EINVAL;
}
ret = run_descriptor_jr(ctx->sha_desc);
- if (ret)
+ if (ret) {
debug("Error %x\n", ret);
- else
+ return ret;
+ } else {
memcpy(dest_buf, ctx->hash, sizeof(ctx->hash));
-
+ }
free(ctx);
return ret;
}
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014-2020 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include <common.h>
struct ccsr_ddr __iomem *ddr;
u32 temp32;
u32 total_gb_size_per_controller;
- int timeout;
+ int timeout = 0;
+ int ddr_freq_for_timeout = 0;
int mod_bnds = 0;
#ifdef CONFIG_SYS_FSL_ERRATUM_A008511
*/
bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
>> SDRAM_CFG_DBW_SHIFT);
- timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
- (get_ddr_freq(ctrl_num) >> 20)) << 2;
+ ddr_freq_for_timeout = (get_ddr_freq(ctrl_num) >> 20) << 2;
+ if (ddr_freq_for_timeout) {
+ timeout = ((total_gb_size_per_controller <<
+ (6 - bus_width)) * 100 /
+ ddr_freq_for_timeout);
+ } else {
+ debug("Error in getting timeout.\n");
+ }
total_gb_size_per_controller >>= 4; /* shift down to gb size */
debug("total %d GB\n", total_gb_size_per_controller);
debug("Need to wait up to %d * 10ms\n", timeout);
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2008-2016 Freescale Semiconductor, Inc.
- * Copyright 2017-2018 NXP Semiconductor
+ * Copyright 2017-2021 NXP Semiconductor
*/
#include <common.h>
unsigned int caslat_actual;
unsigned int retry = 16;
unsigned int tmp = ~0;
- const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
+ unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
#ifdef CONFIG_SYS_FSL_DDR3
const unsigned int taamax = 20000;
#else
}
common_caslat = tmp;
+ if (!mclk_ps) {
+ printf("DDR clock (MCLK cycle was 0 ps), So setting it to slowest DIMM(s) (tCKmin %u ps).\n",
+ outpdimm->tckmin_x_ps);
+ mclk_ps = outpdimm->tckmin_x_ps;
+ }
+
/* validate if the memory clk is in the range of dimms */
if (mclk_ps < outpdimm->tckmin_x_ps) {
printf("DDR clock (MCLK cycle %u ps) is faster than "
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2008-2014 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
/*
unsigned int s = __ilog2(step);
- if ((1 << s) != step)
- return step_string_tbl[7];
-
+ if (s <= 31) {
+ if ((1 << s) != step)
+ return step_string_tbl[7];
+ } else {
+ if ((1 << (s - 32)) != step)
+ return step_string_tbl[7];
+ }
if (s >= ARRAY_SIZE(step_string_tbl)) {
printf("Error for the step in %s\n", __func__);
s = 0;
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2008-2014 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include <common.h>
/* Round to nearest 10ps, being careful about 64-bit multiply/divide */
unsigned long long rem, mclk_ps = ULL_2E12;
-
- /* Now perform the big divide, the result fits in 32-bits */
- rem = do_div(mclk_ps, data_rate);
- result = (rem >= (data_rate >> 1)) ? mclk_ps + 1 : mclk_ps;
+ if (data_rate) {
+ /* Now perform the big divide, the result fits in 32-bits */
+ rem = do_div(mclk_ps, data_rate);
+ result = (rem >= (data_rate >> 1)) ? mclk_ps + 1 : mclk_ps;
+ } else {
+ result = 0;
+ }
return result;
}
help
This option enables using DFU to read and write to MMC based storage.
+config DFU_MTD
+ bool "MTD back end for DFU"
+ depends on DM_MTD
+ depends on CMD_MTDPARTS
+ help
+ This option enables using DFU to read and write to on any MTD device.
+
config DFU_NAND
bool "NAND back end for DFU"
depends on CMD_MTDPARTS
This option enables the support of "part" and "partubi" target in
SPI flash DFU back end.
-config DFU_MTD
- bool "MTD back end for DFU"
- depends on DM_MTD
- depends on CMD_MTDPARTS
- help
- This option enables using DFU to read and write to on any MTD device.
-
config DFU_VIRT
bool "VIRTUAL flash back end for DFU"
help
ret = dfu_flush(dfu, NULL, 0, i);
if (ret)
pr_err("DFU flush failed!");
+ puts("\n");
return ret;
}
static int dfu_read_medium_sf(struct dfu_entity *dfu, u64 offset, void *buf,
long *len)
{
- return spi_flash_read(dfu->data.sf.dev, dfu->data.sf.start + offset,
- *len, buf);
+ long seglen = *len;
+ int ret;
+
+ if (seglen > (16 << 20))
+ seglen = (16 << 20);
+
+ ret = spi_flash_read(dfu->data.sf.dev, dfu->data.sf.start + offset,
+ seglen, buf);
+ if (!ret)
+ *len = seglen;
+
+ return ret;
}
static u64 find_sector(struct dfu_entity *dfu, u64 start, u64 offset)
{ .compatible = "qcom,msm8916-pinctrl" },
{ .compatible = "qcom,apq8016-pinctrl" },
{ .compatible = "qcom,ipq4019-pinctrl" },
+ { .compatible = "qcom,sdm845-pinctrl" },
{ }
};
static const struct udevice_id pm8916_gpio_ids[] = {
{ .compatible = "qcom,pm8916-gpio" },
{ .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */
+ { .compatible = "qcom,pm8998-gpio" },
{ }
};
return log_msg_ret("bad type", -ENXIO);
reg = pmic_reg_read(dev->parent, priv->pid + REG_SUBTYPE);
- if (reg != 0x1)
+ if ((reg & 0x5) == 0)
return log_msg_ret("bad subtype", -ENXIO);
return 0;
static const struct udevice_id pm8941_pwrkey_ids[] = {
{ .compatible = "qcom,pm8916-pwrkey" },
{ .compatible = "qcom,pm8994-pwrkey" },
+ { .compatible = "qcom,pm8998-pwrkey" },
{ }
};
-U_BOOT_DRIVER(pwrkey_pm8941) = {
- .name = "pwrkey_pm8916",
+U_BOOT_DRIVER(pwrkey_pm89xx) = {
+ .name = "pwrkey_pm89xx",
.id = UCLASS_GPIO,
.of_match = pm8941_pwrkey_ids,
.of_to_plat = pm8941_pwrkey_of_to_plat,
{ .compatible = "samsung,exynos4x12-pinctrl" },
{ .compatible = "samsung,exynos5250-pinctrl" },
{ .compatible = "samsung,exynos5420-pinctrl" },
+ { .compatible = "samsung,exynos78x0-gpio" },
{ }
};
static int sifive_gpio_of_to_plat(struct udevice *dev)
{
struct sifive_gpio_plat *plat = dev_get_plat(dev);
- fdt_addr_t addr;
- addr = dev_read_addr(dev);
- if (addr == FDT_ADDR_T_NONE)
+ plat->base = dev_read_addr_ptr(dev);
+ if (!plat->base)
return -EINVAL;
- plat->base = (void *)addr;
return 0;
}
#include <dm.h>
#include <fdtdec.h>
#include <log.h>
-#include <asm/arch/gpio.h>
#include <asm/arch/stm32.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <linux/errno.h>
#include <linux/io.h>
+#include "stm32_gpio_priv.h"
+
#define STM32_GPIOS_PER_BANK 16
#define MODE_BITS(gpio_pin) ((gpio_pin) * 2)
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*/
-#ifndef _GPIO_H_
-#define _GPIO_H_
+#ifndef _STM32_GPIO_PRIV_H_
+#define _STM32_GPIO_PRIV_H_
enum stm32_gpio_mode {
STM32_GPIO_MODE_IN = 0,
int stm32_offset_to_index(struct udevice *dev, unsigned int offset);
-#endif /* _GPIO_H_ */
+#endif /* _STM32_GPIO_PRIV_H_ */
Add support for the Arm Ltd Versatile Express I2C driver. The I2C host
controller is present in the development boards manufactured by Arm Ltd.
+config SYS_I2C_MV
+ bool "Marvell PXA (Armada 3720) I2C driver"
+ help
+ Support for PXA based I2C controller used on Armada 3720 SoC.
+ In Linux, this driver is called i2c-pxa.
+
config SYS_I2C_MVTWSI
bool "Marvell I2C driver"
help
obj-$(CONFIG_$(SPL_)I2C_CROS_EC_TUNNEL) += cros_ec_tunnel.o
obj-$(CONFIG_$(SPL_)I2C_CROS_EC_LDO) += cros_ec_ldo.o
-obj-$(CONFIG_I2C_MV) += mv_i2c.o
obj-$(CONFIG_$(SPL_)SYS_I2C_LEGACY) += i2c_core.o
obj-$(CONFIG_SYS_I2C_ASPEED) += ast_i2c.o
obj-$(CONFIG_SYS_I2C_AT91) += at91_i2c.o
obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o
obj-$(CONFIG_SYS_I2C_LPC32XX) += lpc32xx_i2c.o
obj-$(CONFIG_SYS_I2C_MESON) += meson_i2c.o
+obj-$(CONFIG_SYS_I2C_MV) += mv_i2c.o
obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o
obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
obj-$(CONFIG_SYS_I2C_NEXELL) += nx_i2c.o
u32 clock_frequency_khz;
int ret;
- bus->base = (void __iomem *)devfdt_get_addr(dev);
+ bus->base = dev_read_addr_ptr(dev);
if (dev_read_u32(dev, "reg-shift", &bus->reg_shift)) {
/* no 'reg-shift', check for deprecated 'regstep' */
--- /dev/null
+#
+# IOMMU devices
+#
+
+menu "IOMMU device drivers"
+
+config IOMMU
+ bool "Enable Driver Model for IOMMU drivers"
+ depends on DM
+ help
+ Enable driver model for IOMMU devices. An IOMMU maps device
+ virtiual memory addresses to physical addresses. Devices
+ that sit behind an IOMMU can typically only access physical
+ memory if the IOMMU has been programmed to allow access to
+ that memory.
+
+config APPLE_DART
+ bool "Apple DART support"
+ depends on IOMMU && ARCH_APPLE
+ default y
+ help
+ Enable support for the DART on Apple SoCs. The DART is Apple's
+ IOMMU implementation. The driver performs the necessary
+ configuration to put the DART into bypass mode such that it can
+ be used transparently by U-Boot.
+
+endmenu
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-$(CONFIG_IOMMU) += iommu-uclass.o
+
+obj-$(CONFIG_APPLE_DART) += apple_dart.o
+obj-$(CONFIG_SANDBOX) += sandbox_iommu.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 Mark Kettenis <kettenis@openbsd.org>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <asm/io.h>
+
+#define DART_PARAMS2 0x0004
+#define DART_PARAMS2_BYPASS_SUPPORT BIT(0)
+#define DART_TLB_OP 0x0020
+#define DART_TLB_OP_OPMASK (0xfff << 20)
+#define DART_TLB_OP_FLUSH (0x001 << 20)
+#define DART_TLB_OP_BUSY BIT(2)
+#define DART_TLB_OP_SIDMASK 0x0034
+#define DART_ERROR_STATUS 0x0040
+#define DART_TCR(sid) (0x0100 + 4 * (sid))
+#define DART_TCR_TRANSLATE_ENABLE BIT(7)
+#define DART_TCR_BYPASS_DART BIT(8)
+#define DART_TCR_BYPASS_DAPF BIT(12)
+#define DART_TTBR(sid, idx) (0x0200 + 16 * (sid) + 4 * (idx))
+#define DART_TTBR_VALID BIT(31)
+#define DART_TTBR_SHIFT 12
+
+static int apple_dart_probe(struct udevice *dev)
+{
+ void *base;
+ int sid, i;
+
+ base = dev_read_addr_ptr(dev);
+ if (!base)
+ return -EINVAL;
+
+ u32 params2 = readl(base + DART_PARAMS2);
+ if (params2 & DART_PARAMS2_BYPASS_SUPPORT) {
+ for (sid = 0; sid < 16; sid++) {
+ writel(DART_TCR_BYPASS_DART | DART_TCR_BYPASS_DAPF,
+ base + DART_TCR(sid));
+ for (i = 0; i < 4; i++)
+ writel(0, base + DART_TTBR(sid, i));
+ }
+ }
+
+ return 0;
+}
+
+static const struct udevice_id apple_dart_ids[] = {
+ { .compatible = "apple,t8103-dart" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(apple_dart) = {
+ .name = "apple_dart",
+ .id = UCLASS_IOMMU,
+ .of_match = apple_dart_ids,
+ .probe = apple_dart_probe
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 Mark Kettenis <kettenis@openbsd.org>
+ */
+
+#define LOG_CATEGORY UCLASS_IOMMU
+
+#include <common.h>
+#include <dm.h>
+
+#if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA))
+int dev_iommu_enable(struct udevice *dev)
+{
+ struct ofnode_phandle_args args;
+ struct udevice *dev_iommu;
+ int i, count, ret = 0;
+
+ count = dev_count_phandle_with_args(dev, "iommus",
+ "#iommu-cells", 0);
+ for (i = 0; i < count; i++) {
+ ret = dev_read_phandle_with_args(dev, "iommus",
+ "#iommu-cells", 0, i, &args);
+ if (ret) {
+ debug("%s: dev_read_phandle_with_args failed: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = uclass_get_device_by_ofnode(UCLASS_IOMMU, args.node,
+ &dev_iommu);
+ if (ret) {
+ debug("%s: uclass_get_device_by_ofnode failed: %d\n",
+ __func__, ret);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+#endif
+
+UCLASS_DRIVER(iommu) = {
+ .id = UCLASS_IOMMU,
+ .name = "iommu",
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 Mark Kettenis <kettenis@openbsd.org>
+ */
+
+#include <common.h>
+#include <dm.h>
+
+static const struct udevice_id sandbox_iommu_ids[] = {
+ { .compatible = "sandbox,iommu" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(sandbox_iommu) = {
+ .name = "sandbox_iommu",
+ .id = UCLASS_IOMMU,
+ .of_match = sandbox_iommu_ids,
+};
Programmable memory pages that are stored on the some
Freescale i.MX processors.
+config SPL_MXC_OCOTP
+ bool "Enable MXC OCOTP driver in SPL"
+ depends on SPL && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610)
+ default y
+ help
+ If you say Y here, you will get support for the One Time
+ Programmable memory pages, that are stored on some
+ Freescale i.MX processors, in SPL.
+
config NUVOTON_NCT6102D
bool "Enable Nuvoton NCT6102D Super I/O driver"
help
obj-$(CONFIG_LED_STATUS) += status_led.o
obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o
obj-$(CONFIG_MPC83XX_SERDES) += mpc83xx_serdes.o
-obj-$(CONFIG_MXC_OCOTP) += mxc_ocotp.o
+obj-$(CONFIG_$(SPL_)MXC_OCOTP) += mxc_ocotp.o
obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o
obj-$(CONFIG_NUVOTON_NCT6102D) += nuvoton_nct6102d.o
obj-$(CONFIG_P2SB) += p2sb-uclass.o
return result;
}
+static int check_peripheral_id(struct pl180_mmc_host *host, u32 periph_id)
+{
+ return readl(&host->base->periph_id0) == (periph_id & 0xFF) &&
+ readl(&host->base->periph_id1) == ((periph_id >> 8) & 0xFF) &&
+ readl(&host->base->periph_id2) == ((periph_id >> 16) & 0xFF) &&
+ readl(&host->base->periph_id3) == ((periph_id >> 24) & 0xFF);
+}
+
static int host_set_ios(struct mmc *dev)
{
struct pl180_mmc_host *host = dev->priv;
sdi_clkcr &= ~(SDI_CLKCR_WIDBUS_MASK);
sdi_clkcr |= buswidth;
}
+ /* For MMCs' with peripheral id 0x02041180 and 0x03041180, H/W flow control
+ * needs to be enabled for multi block writes (MMC CMD 18).
+ */
+ if (check_peripheral_id(host, 0x02041180) ||
+ check_peripheral_id(host, 0x03041180))
+ sdi_clkcr |= SDI_CLKCR_HWFCEN;
writel(sdi_clkcr, &host->base->clock);
udelay(CLK_CHANGE_DELAY);
#define SDI_CLKCR_CLKEN 0x00000100
#define SDI_CLKCR_PWRSAV 0x00000200
#define SDI_CLKCR_BYPASS 0x00000400
+#define SDI_CLKCR_HWFCEN 0x00001000
#define SDI_CLKCR_WIDBUS_MASK 0x00001800
#define SDI_CLKCR_WIDBUS_1 0x00000000
#define SDI_CLKCR_WIDBUS_4 0x00000800
#include <dm/device_compat.h>
#include <linux/bitops.h>
#include <linux/delay.h>
+#include <linux/iopoll.h>
#include <linux/dma-mapping.h>
#include <sdhci.h>
return 0;
}
+static int fsl_esdhc_wait_dat0(struct udevice *dev, int state,
+ int timeout_us)
+{
+ int ret;
+ u32 tmp;
+ struct fsl_esdhc_priv *priv = dev_get_priv(dev);
+ struct fsl_esdhc *regs = priv->esdhc_regs;
+
+ ret = readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp,
+ !!(tmp & PRSSTAT_DAT0) == !!state,
+ timeout_us);
+ return ret;
+}
+
static const struct dm_mmc_ops fsl_esdhc_ops = {
.get_cd = fsl_esdhc_get_cd,
.send_cmd = fsl_esdhc_send_cmd,
#endif
.reinit = fsl_esdhc_reinit,
.hs400_prepare_ddr = fsl_esdhc_hs400_prepare_ddr,
+ .wait_dat0 = fsl_esdhc_wait_dat0,
};
static const struct udevice_id fsl_esdhc_ids[] = {
if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {
esdhc_write32(®s->strobe_dllctrl, ESDHC_STROBE_DLL_CTRL_RESET);
+ /* clear the reset bit on strobe dll before any setting */
+ esdhc_write32(®s->strobe_dllctrl, 0);
/*
* enable strobe dll ctrl and adjust the delay target
* for the uSDHC loopback read clock
*/
val = ESDHC_STROBE_DLL_CTRL_ENABLE |
+ ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT |
(priv->strobe_dll_delay_target <<
ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
esdhc_write32(®s->strobe_dllctrl, val);
- /* wait 1us to make sure strobe dll status register stable */
- mdelay(1);
+ /* wait 5us to make sure strobe dll status register stable */
+ mdelay(5);
val = esdhc_read32(®s->strobe_dllstat);
if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK))
pr_warn("HS400 strobe DLL status REF not lock!\n");
if (priv->clock != clock)
set_sysctl(priv, mmc, clock);
-#ifdef MMC_SUPPORTS_TUNING
if (mmc->clk_disable) {
#ifdef CONFIG_FSL_USDHC
esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
#endif
}
+#ifdef MMC_SUPPORTS_TUNING
/*
* For HS400/HS400ES mode, make sure set the strobe dll in the
* target clock rate. So call esdhc_set_strobe_dll() after the
| ESDHC_FLAG_HS400,
};
+static struct esdhc_soc_data usdhc_imx7ulp_data = {
+ .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
+ | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
+ | ESDHC_FLAG_HS400,
+};
+
static struct esdhc_soc_data usdhc_imx8qm_data = {
.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING |
ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 |
{ .compatible = "fsl,imx6sl-usdhc", },
{ .compatible = "fsl,imx6q-usdhc", },
{ .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,},
- { .compatible = "fsl,imx7ulp-usdhc", },
+ { .compatible = "fsl,imx7ulp-usdhc", .data = (ulong)&usdhc_imx7ulp_data,},
{ .compatible = "fsl,imx8qm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
{ .compatible = "fsl,imx8mm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
{ .compatible = "fsl,imx8mn-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
return ret;
/*
- * In cases when not allowed to poll by using CMD13 or because we aren't
+ * In cases when neiter allowed to poll by using CMD13 nor we are
* capable of polling by using mmc_wait_dat0, then rely on waiting the
* stated timeout to be sufficient.
*/
- if (ret == -ENOSYS || !send_status) {
+ if (ret == -ENOSYS && !send_status) {
mdelay(timeout_ms);
return 0;
}
return value;
}
+static int sdhci_wait_dat0(struct udevice *dev, int state,
+ int timeout_us)
+{
+ int tmp;
+ struct mmc *mmc = mmc_get_mmc_dev(dev);
+ struct sdhci_host *host = mmc->priv;
+ unsigned long timeout = timer_get_us() + timeout_us;
+
+ // readx_poll_timeout is unsuitable because sdhci_readl accepts
+ // two arguments
+ do {
+ tmp = sdhci_readl(host, SDHCI_PRESENT_STATE);
+ if (!!(tmp & SDHCI_DATA_0_LVL_MASK) == !!state)
+ return 0;
+ } while (!timeout_us || !time_after(timer_get_us(), timeout));
+
+ return -ETIMEDOUT;
+}
+
const struct dm_mmc_ops sdhci_ops = {
.send_cmd = sdhci_send_command,
.set_ios = sdhci_set_ios,
#ifdef MMC_SUPPORTS_TUNING
.execute_tuning = sdhci_execute_tuning,
#endif
+ .wait_dat0 = sdhci_wait_dat0,
};
#else
static const struct mmc_ops sdhci_ops = {
priv->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
priv->mclkreg = &ccm->sd1_clk_cfg;
break;
+#ifdef SUNXI_MMC2_BASE
case 2:
priv->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
priv->mclkreg = &ccm->sd2_clk_cfg;
break;
+#endif
#ifdef SUNXI_MMC3_BASE
case 3:
priv->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
putc('\n');
instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
instr->state = MTD_ERASE_FAILED;
- mtd_erase_callback(instr);
return -EIO;
}
flash = pdata->base + addr;
writel(stat, ®s->isr); /* clear isr */
instr->fail_addr = addr;
instr->state = MTD_ERASE_FAILED;
- mtd_erase_callback(instr);
return -EIO;
}
if (flash_verbose)
addr += mtd->erasesize;
}
instr->state = MTD_ERASE_DONE;
- mtd_erase_callback(instr);
return 0;
}
}
instr->state = MTD_ERASE_DONE;
- mtd_erase_callback(instr);
return 0;
}
return -EINVAL;
}
-static void concat_erase_callback(struct erase_info *instr)
-{
- /* Nothing to do here in U-Boot */
-#ifndef __UBOOT__
- wake_up((wait_queue_head_t *) instr->priv);
-#endif
-}
-
static int concat_dev_erase(struct mtd_info *mtd, struct erase_info *erase)
{
int err;
init_waitqueue_head(&waitq);
erase->mtd = mtd;
- erase->callback = concat_erase_callback;
erase->priv = (unsigned long) &waitq;
/*
if (err)
return err;
- if (instr->callback)
- instr->callback(instr);
return 0;
}
}
EXPORT_SYMBOL_GPL(__put_mtd_device);
-/*
- * Erase is an asynchronous operation. Device drivers are supposed
- * to call instr->callback() whenever the operation completes, even
- * if it completes with a failure.
- * Callers are supposed to pass a callback function and wait for it
- * to be called before writing to the block.
- */
int mtd_erase(struct mtd_info *mtd, struct erase_info *instr)
{
if (instr->addr > mtd->size || instr->len > mtd->size - instr->addr)
instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
if (!instr->len) {
instr->state = MTD_ERASE_DONE;
- mtd_erase_callback(instr);
return 0;
}
return mtd->_erase(mtd, instr);
int ret;
instr->addr += mtd->offset;
+
ret = mtd->parent->_erase(mtd->parent, instr);
- if (ret) {
- if (instr->fail_addr != MTD_FAIL_ADDR_UNKNOWN)
- instr->fail_addr -= mtd->offset;
- instr->addr -= mtd->offset;
- }
- return ret;
-}
+ if (ret && instr->fail_addr != MTD_FAIL_ADDR_UNKNOWN)
+ instr->fail_addr -= mtd->offset;
-void mtd_erase_callback(struct erase_info *instr)
-{
- if (instr->mtd->_erase == part_erase) {
- if (instr->fail_addr != MTD_FAIL_ADDR_UNKNOWN)
- instr->fail_addr -= instr->mtd->offset;
- instr->addr -= instr->mtd->offset;
- }
- if (instr->callback)
- instr->callback(instr);
+ instr->addr -= mtd->offset;
+
+ return ret;
}
-EXPORT_SYMBOL_GPL(mtd_erase_callback);
static int part_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
{
imply CMD_NAND
help
This enables the NAND driver for the NAND flash controller on the
- i.MX27 / i.MX31 / i.MX5 rocessors.
+ i.MX27 / i.MX31 / i.MX5 processors.
config NAND_MXS
bool "MXS NAND support"
config SYS_NAND_BLOCK_SIZE
hex "NAND chip eraseblock size"
depends on ARCH_SUNXI || SPL_NAND_SUPPORT || TPL_NAND_SUPPORT
- depends on !NAND_MXS_DT && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
+ depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC && !NAND_FSL_IFC
help
Number of data bytes in one eraseblock for the NAND chip on the
board. This is the multiple of NAND_PAGE_SIZE and the number of
depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
(NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
- depends on !NAND_MXS_DT && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
+ depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
help
Number of data bytes in one page for the NAND chip on the
board, not including the OOB area.
depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
(NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
- depends on !NAND_MXS_DT && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
+ depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
help
Number of bytes in the Out-Of-Band area for the NAND chip on
the board.
void nand_deselect(void)
{
}
+
+u32 nand_spl_adjust_offset(u32 sector, u32 offs)
+{
+ /* Handle the offset adjust in nand_spl_load_image,*/
+ return offs;
+}
chip->select_chip(mtd, -1);
nand_release_device(mtd);
- /* Do call back function */
- if (!ret)
- mtd_erase_callback(instr);
-
/* Return more or less happy */
return ret;
}
#include <linux/mtd/spinand.h>
#define SPINAND_MFR_MACRONIX 0xC2
+#define MACRONIX_ECCSR_MASK 0x0F
+
static SPINAND_OP_VARIANTS(read_cache_variants,
SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
SPI_MEM_OP_DUMMY(1, 1),
SPI_MEM_OP_DATA_IN(1, eccsr, 1));
- return spi_mem_exec_op(spinand->slave, &op);
+ int ret = spi_mem_exec_op(spinand->slave, &op);
+
+ if (ret)
+ return ret;
+
+ *eccsr &= MACRONIX_ECCSR_MASK;
+ return 0;
}
static int mx35lf1ge4ab_ecc_get_status(struct spinand_device *spinand,
erase_exit:
ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
- /* Do call back function */
- if (!ret)
- mtd_erase_callback(instr);
/* Deselect and wake up anyone waiting on the device */
onenand_release_device(mtd);
}
instr->state = MTD_ERASE_DONE;
- mtd_erase_callback(instr);
return 0;
}
static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
{
struct spi_nor *nor = mtd_to_spi_nor(mtd);
+ bool addr_known = false;
u32 addr, len, rem;
- int ret;
+ int ret, err;
dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
(long long)instr->len);
- if (!instr->len)
- return 0;
-
div_u64_rem(instr->len, mtd->erasesize, &rem);
- if (rem)
- return -EINVAL;
+ if (rem) {
+ ret = -EINVAL;
+ goto err;
+ }
addr = instr->addr;
len = instr->len;
+ instr->state = MTD_ERASING;
+ addr_known = true;
+
while (len) {
WATCHDOG_RESET();
+ if (ctrlc()) {
+ addr_known = false;
+ ret = -EINTR;
+ goto erase_err;
+ }
#ifdef CONFIG_SPI_FLASH_BAR
ret = write_bar(nor, addr);
if (ret < 0)
- return ret;
+ goto erase_err;
#endif
- write_enable(nor);
+ ret = write_enable(nor);
+ if (ret < 0)
+ goto erase_err;
ret = spi_nor_erase_sector(nor, addr);
if (ret < 0)
goto erase_err;
}
+ addr_known = false;
erase_err:
#ifdef CONFIG_SPI_FLASH_BAR
- ret = clean_bar(nor);
+ err = clean_bar(nor);
+ if (!ret)
+ ret = err;
#endif
- write_disable(nor);
+ err = write_disable(nor);
+ if (!ret)
+ ret = err;
+
+err:
+ if (ret) {
+ instr->fail_addr = addr_known ? addr : MTD_FAIL_ADDR_UNKNOWN;
+ instr->state = MTD_ERASE_FAILED;
+ } else {
+ instr->state = MTD_ERASE_DONE;
+ }
return ret;
}
dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
- if (!len)
- return 0;
-
for (i = 0; i < len; ) {
ssize_t written;
loff_t addr = to + i;
.post_bfpt = s25hx_t_post_bfpt_fixup,
.post_sfdp = s25hx_t_post_sfdp_fixup,
};
+
+static int s25fl256l_setup(struct spi_nor *nor, const struct flash_info *info,
+ const struct spi_nor_flash_parameter *params)
+{
+ return -ENOTSUPP; /* Bank Address Register is not supported */
+}
+
+static void s25fl256l_default_init(struct spi_nor *nor)
+{
+ nor->setup = s25fl256l_setup;
+}
+
+static struct spi_nor_fixups s25fl256l_fixups = {
+ .default_init = s25fl256l_default_init,
+};
#endif
#ifdef CONFIG_SPI_FLASH_S28HS512T
break;
}
}
+
+ if (CONFIG_IS_ENABLED(SPI_FLASH_BAR) &&
+ !strcmp(nor->info->name, "s25fl256l"))
+ nor->fixups = &s25fl256l_fixups;
#endif
#ifdef CONFIG_SPI_FLASH_S28HS512T
SECT_4K | SPI_NOR_DUAL_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
+ {
+ INFO("gd25lq256d", 0xc86019, 0, 64 * 1024, 512,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+ },
#endif
#ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */
/* ISSI */
SECT_4K | SPI_NOR_DUAL_READ) },
{ INFO("is25lp256", 0x9d6019, 0, 64 * 1024, 512,
SECT_4K | SPI_NOR_DUAL_READ) },
+ { INFO("is25lp512", 0x9d601a, 0, 64 * 1024, 1024,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("is25wp032", 0x9d7016, 0, 64 * 1024, 64,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("is25wp064", 0x9d7017, 0, 64 * 1024, 128,
{ INFO("is25wp256", 0x9d7019, 0, 64 * 1024, 512,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_4B_OPCODES) },
+ { INFO("is25wp512", 0x9d701a, 0, 64 * 1024, 1024,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
#endif
#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
/* Macronix */
{ INFO6("mt25qu256a", 0x20bb19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) },
{ INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | USE_FSR) },
{ INFO6("mt25qu512a", 0x20bb20, 0x104400, 64 * 1024, 1024,
- SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
USE_FSR) },
{ INFO("n25q512a", 0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
{ INFO6("mt25ql512a", 0x20ba20, 0x104400, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ INFO("n25q00a", 0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
{ INFO("mt25ql01g", 0x21ba20, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
{ INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
+ { INFO("mt25ql02g", 0x20ba22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE | SPI_NOR_4B_OPCODES) },
#ifdef CONFIG_SPI_FLASH_MT35XU
{ INFO("mt35xu512aba", 0x2c5b1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) },
#endif /* CONFIG_SPI_FLASH_MT35XU */
{ INFO("s25fl208k", 0x014014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ) },
{ INFO("s25fl064l", 0x016017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ INFO("s25fl128l", 0x016018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+ { INFO("s25fl256l", 0x016019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ INFO6("s25hl512t", 0x342a1a, 0x0f0390, 256 * 1024, 256,
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
USE_CLSR) },
}
/**
- * erase_callback - MTD erasure call-back.
- * @ei: MTD erase information object.
- *
- * Note, even though MTD erase interface is asynchronous, all the current
- * implementations are synchronous anyway.
- */
-static void erase_callback(struct erase_info *ei)
-{
- wake_up_interruptible((wait_queue_head_t *)ei->priv);
-}
-
-/**
* do_sync_erase - synchronously erase a physical eraseblock.
* @ubi: UBI device description object
* @pnum: the physical eraseblock number to erase
ei.mtd = ubi->mtd;
ei.addr = (loff_t)pnum * ubi->peb_size;
ei.len = ubi->peb_size;
- ei.callback = erase_callback;
ei.priv = (unsigned long)&wq;
err = mtd_erase(ubi->mtd, &ei);
help
This driver support the Freescale FMan Ethernet controller
+config SYS_FMAN_FW_ADDR
+ hex "FMAN Firmware Address"
+ depends on FMAN_ENET
+ default 0x0
+
+config SYS_QE_FMAN_FW_LENGTH
+ hex "FMAN QE Firmware length"
+ depends on FMAN_ENET || QE || U_QE
+ default 0x10000
+
config FTMAC100
bool "Ftmac100 Ethernet Support"
help
config MACB
bool "Cadence MACB/GEM Ethernet Interface"
- depends on DM_ETH
select PHYLIB
help
The Cadence MACB ethernet interface is found on many Atmel
#include <image.h>
#include <log.h>
#include <malloc.h>
+#include <mapmem.h>
#include <asm/global_data.h>
#include <linux/bug.h>
#include <asm/io.h>
#define MC_BOOT_ENV_VAR "mcinitcmd"
#define MC_DRAM_BLOCK_DEFAULT_SIZE (512UL * 1024 * 1024)
+#define MC_BUFFER_SIZE (1024 * 1024 * 16)
+#define MAGIC_MC 0x4d430100
+#define MC_FW_ADDR_MASK_LOW 0xE0000000
+#define MC_FW_ADDR_MASK_HIGH 0X1FFFF
+#define MC_STRUCT_BUFFER_OFFSET 0x01000000
+#define MC_OFFSET_DELTA MC_STRUCT_BUFFER_OFFSET
+
+#define LOG_HEADER_FLAG_BUFFER_WRAPAROUND 0x80000000
+#define LAST_BYTE(a) ((a) & ~(LOG_HEADER_FLAG_BUFFER_WRAPAROUND))
+
DECLARE_GLOBAL_DATA_PTR;
static int mc_memset_resv_ram;
static struct mc_version mc_ver_info;
return err;
}
+static void print_k_bytes(const void *buf, ssize_t *size)
+{
+ while (*size > 0) {
+ int count = printf("%s", (char *)buf);
+
+ buf += count;
+ *size -= count;
+ }
+}
+
+static void mc_dump_log(void)
+{
+ struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR;
+ u64 high = in_le64(&mc_ccsr_regs->reg_mcfbahr) & MC_FW_ADDR_MASK_HIGH;
+ u64 low = in_le64(&mc_ccsr_regs->reg_mcfbalr) & MC_FW_ADDR_MASK_LOW;
+ u32 buf_len, wrapped, last_byte, magic, buf_start;
+ u64 mc_addr = (high << 32) | low;
+ struct log_header *header;
+ ssize_t size, bytes_end;
+ const void *end_of_data;
+ const void *map_addr;
+ const void *end_addr;
+ const void *cur_ptr;
+ const void *buf;
+
+ map_addr = map_sysmem(mc_addr + MC_STRUCT_BUFFER_OFFSET,
+ MC_BUFFER_SIZE);
+ header = (struct log_header *)map_addr;
+ last_byte = in_le32(&header->last_byte);
+ buf_len = in_le32(&header->buf_length);
+ magic = in_le32(&header->magic_word);
+ buf_start = in_le32(&header->buf_start);
+ buf = map_addr + buf_start - MC_OFFSET_DELTA;
+ end_addr = buf + buf_len;
+ wrapped = last_byte & LOG_HEADER_FLAG_BUFFER_WRAPAROUND;
+ end_of_data = buf + LAST_BYTE(last_byte);
+
+ if (magic != MAGIC_MC) {
+ puts("Magic number is not valid\n");
+ printf("expected = %08x, received = %08x\n", MAGIC_MC, magic);
+ goto err_magic;
+ }
+
+ if (wrapped && end_of_data != end_addr)
+ cur_ptr = end_of_data + 1;
+ else
+ cur_ptr = buf;
+
+ if (cur_ptr <= end_of_data)
+ size = end_of_data - cur_ptr;
+ else
+ size = (end_addr - cur_ptr) + (end_of_data - buf);
+
+ bytes_end = end_addr - cur_ptr;
+ if (size > bytes_end) {
+ print_k_bytes(cur_ptr, &bytes_end);
+
+ cur_ptr = buf;
+ size -= bytes_end;
+ }
+
+ print_k_bytes(buf, &size);
+
+err_magic:
+ unmap_sysmem(map_addr);
+}
+
static int do_fsl_mc(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
int err = 0;
- if (argc < 3)
+ if (argc < 2)
goto usage;
switch (argv[1][0]) {
#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
u64 aiop_fw_addr;
#endif
+ if (argc < 3)
+ goto usage;
sub_cmd = argv[2][0];
}
break;
}
+ case 'd':
+ if (argc > 2)
+ goto usage;
+
+ mc_dump_log();
+ break;
default:
printf("Invalid option: %s\n", argv[1]);
goto usage;
"fsl_mc lazyapply DPL [DPL_addr] - Apply DPL file on exit\n"
"fsl_mc apply spb [spb_addr] - Apply SPB Soft Parser Blob\n"
"fsl_mc start aiop [FW_addr] - Start AIOP\n"
+ "fsl_mc dump_log - Dump MC Log\n"
);
void mc_env_boot(void)
#ifdef CONFIG_DM_ETH
static int macb_sifive_clk_init(struct udevice *dev, ulong rate)
{
- fdt_addr_t addr;
void *gemgxl_regs;
- addr = dev_read_addr_index(dev, 1);
- if (addr == FDT_ADDR_T_NONE)
- return -ENODEV;
-
- gemgxl_regs = (void __iomem *)addr;
+ gemgxl_regs = dev_read_addr_index_ptr(dev, 1);
if (!gemgxl_regs)
return -ENODEV;
macb->phy_addr = ofnode_read_u32_default(phandle_args.node,
"reg", -1);
- macb->regs = (void *)pdata->iobase;
+ macb->regs = (void *)(uintptr_t)pdata->iobase;
macb->is_big_endian = (cpu_to_be32(0x12345678) == 0x12345678);
{
struct eth_pdata *pdata = dev_get_plat(dev);
- pdata->iobase = (phys_addr_t)dev_remap_addr(dev);
+ pdata->iobase = (uintptr_t)dev_remap_addr(dev);
if (!pdata->iobase)
return -EINVAL;
* for returning CRS, so that if U-Boot does support CRS in the future,
* it will work for Aardvark.
*/
- allow_crs = pcie->cfgcrssve;
+ allow_crs = (offset == PCI_VENDOR_ID) && (size == PCI_SIZE_32) && pcie->cfgcrssve;
if (advk_readl(pcie, PIO_START)) {
dev_err(pcie->dev,
advk_writel(pcie, reg, PIO_ADDR_LS);
advk_writel(pcie, 0, PIO_ADDR_MS);
+ /* Program the data strobe */
+ advk_writel(pcie, 0xf, PIO_WR_DATA_STRB);
+
retry_count = 0;
retry:
if (offset >= 0x10 && offset < 0x34) {
data = pcie->cfgcache[(offset - 0x10) / 4];
data = pci_conv_size_to_32(data, value, offset, size);
+ /* This PCI bridge does not have configurable bars */
+ if ((offset & ~3) == PCI_BASE_ADDRESS_0 ||
+ (offset & ~3) == PCI_BASE_ADDRESS_1)
+ data = 0x0;
pcie->cfgcache[(offset - 0x10) / 4] = data;
} else if ((offset & ~3) == PCI_ROM_ADDRESS1) {
data = advk_readl(pcie, PCIE_CORE_EXP_ROM_BAR_REG);
#define PCIE_DEV_REV_OFF 0x0008
#define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
#define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
+#define PCIE_EXP_ROM_BAR_OFF 0x0030
#define PCIE_CAPAB_OFF 0x0060
#define PCIE_CTRL_STAT_OFF 0x0068
#define PCIE_HEADER_LOG_4_OFF 0x0128
#define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8)
-#define PCIE_CONF_ADDR(dev, reg) \
- (PCIE_CONF_BUS(PCI_BUS(dev)) | PCIE_CONF_DEV(PCI_DEV(dev)) | \
- PCIE_CONF_FUNC(PCI_FUNC(dev)) | PCIE_CONF_REG(reg) | \
+#define PCIE_CONF_ADDR(b, d, f, reg) \
+ (PCIE_CONF_BUS(b) | PCIE_CONF_DEV(d) | \
+ PCIE_CONF_FUNC(f) | PCIE_CONF_REG(reg) | \
PCIE_CONF_ADDR_EN)
#define PCIE_CONF_DATA_OFF 0x18fc
#define PCIE_MASK_OFF 0x1910
#define PCIE_MASK_ENABLE_INTS (0xf << 24)
#define PCIE_CTRL_OFF 0x1a00
#define PCIE_CTRL_X1_MODE BIT(0)
+#define PCIE_CTRL_RC_MODE BIT(1)
#define PCIE_STAT_OFF 0x1a04
#define PCIE_STAT_BUS (0xff << 8)
#define PCIE_STAT_DEV (0x1f << 16)
int devfn;
u32 lane_mask;
int first_busno;
- int local_dev;
+ int sec_busno;
char name[16];
unsigned int mem_target;
unsigned int mem_attr;
unsigned int io_target;
unsigned int io_attr;
+ u32 cfgcache[0x34 - 0x10];
};
/*
* and 64K of I/O space when registered.
*/
static void __iomem *mvebu_pcie_membase = (void __iomem *)MBUS_PCI_MEM_BASE;
-#define PCIE_MEM_SIZE (128 << 20)
static void __iomem *mvebu_pcie_iobase = (void __iomem *)MBUS_PCI_IO_BASE;
static inline bool mvebu_pcie_link_up(struct mvebu_pcie *pcie)
writel(stat, pcie->base + PCIE_STAT_OFF);
}
-static int mvebu_pcie_get_local_bus_nr(struct mvebu_pcie *pcie)
-{
- u32 stat;
-
- stat = readl(pcie->base + PCIE_STAT_OFF);
- return (stat & PCIE_STAT_BUS) >> 8;
-}
-
-static int mvebu_pcie_get_local_dev_nr(struct mvebu_pcie *pcie)
-{
- u32 stat;
-
- stat = readl(pcie->base + PCIE_STAT_OFF);
- return (stat & PCIE_STAT_DEV) >> 16;
-}
-
static inline struct mvebu_pcie *hose_to_pcie(struct pci_controller *hose)
{
return container_of(hose, struct mvebu_pcie, hose);
}
-static int mvebu_pcie_valid_addr(struct mvebu_pcie *pcie, pci_dev_t bdf)
+static bool mvebu_pcie_valid_addr(struct mvebu_pcie *pcie,
+ int busno, int dev, int func)
{
- /*
- * There are two devices visible on local bus:
- * * on slot configured by function mvebu_pcie_set_local_dev_nr()
- * (by default this register is set to 0) there is a
- * "Marvell Memory controller", which isn't useful in root complex
- * mode,
- * * on all other slots the real PCIe card connected to the PCIe slot.
- *
- * We therefore allow access only to the real PCIe card.
- */
- if (PCI_BUS(bdf) == pcie->first_busno &&
- PCI_DEV(bdf) != !pcie->local_dev)
- return 0;
+ /* On primary bus is only one PCI Bridge */
+ if (busno == pcie->first_busno && (dev != 0 || func != 0))
+ return false;
- return 1;
+ /* Access to other buses is possible when link is up */
+ if (busno != pcie->first_busno && !mvebu_pcie_link_up(pcie))
+ return false;
+
+ /* On secondary bus can be only one PCIe device */
+ if (busno == pcie->sec_busno && dev != 0)
+ return false;
+
+ return true;
}
static int mvebu_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
enum pci_size_t size)
{
struct mvebu_pcie *pcie = dev_get_plat(bus);
- u32 data;
+ int busno = PCI_BUS(bdf) - dev_seq(bus);
+ u32 addr, data;
debug("PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ",
PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
- if (!mvebu_pcie_valid_addr(pcie, bdf)) {
+ if (!mvebu_pcie_valid_addr(pcie, busno, PCI_DEV(bdf), PCI_FUNC(bdf))) {
debug("- out of range\n");
*valuep = pci_get_ff(size);
return 0;
}
+ /*
+ * mvebu has different internal registers mapped into PCI config space
+ * in range 0x10-0x34 for PCI bridge, so do not access PCI config space
+ * for this range and instead read content from driver virtual cfgcache
+ */
+ if (busno == pcie->first_busno && offset >= 0x10 && offset < 0x34) {
+ data = pcie->cfgcache[(offset - 0x10) / 4];
+ debug("(addr,size,val)=(0x%04x, %d, 0x%08x) from cfgcache\n",
+ offset, size, data);
+ *valuep = pci_conv_32_to_size(data, offset, size);
+ return 0;
+ } else if (busno == pcie->first_busno &&
+ (offset & ~3) == PCI_ROM_ADDRESS1) {
+ /* mvebu has Expansion ROM Base Address (0x38) at offset 0x30 */
+ offset -= PCI_ROM_ADDRESS1 - PCIE_EXP_ROM_BAR_OFF;
+ }
+
+ /*
+ * PCI bridge is device 0 at primary bus but mvebu has it mapped on
+ * secondary bus with device number 1.
+ */
+ if (busno == pcie->first_busno)
+ addr = PCIE_CONF_ADDR(pcie->sec_busno, 1, 0, offset);
+ else
+ addr = PCIE_CONF_ADDR(busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset);
+
/* write address */
- writel(PCIE_CONF_ADDR(bdf, offset), pcie->base + PCIE_CONF_ADDR_OFF);
+ writel(addr, pcie->base + PCIE_CONF_ADDR_OFF);
/* read data */
- data = readl(pcie->base + PCIE_CONF_DATA_OFF);
+ switch (size) {
+ case PCI_SIZE_8:
+ data = readb(pcie->base + PCIE_CONF_DATA_OFF + (offset & 3));
+ break;
+ case PCI_SIZE_16:
+ data = readw(pcie->base + PCIE_CONF_DATA_OFF + (offset & 2));
+ break;
+ case PCI_SIZE_32:
+ data = readl(pcie->base + PCIE_CONF_DATA_OFF);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (busno == pcie->first_busno &&
+ (offset & ~3) == (PCI_HEADER_TYPE & ~3)) {
+ /*
+ * Change Header Type of PCI Bridge device to Type 1
+ * (0x01, used by PCI Bridges) because mvebu reports
+ * Type 0 (0x00, used by Upstream and Endpoint devices).
+ */
+ data = pci_conv_size_to_32(data, 0, offset, size);
+ data &= ~0x007f0000;
+ data |= PCI_HEADER_TYPE_BRIDGE << 16;
+ data = pci_conv_32_to_size(data, offset, size);
+ }
+
debug("(addr,size,val)=(0x%04x, %d, 0x%08x)\n", offset, size, data);
- *valuep = pci_conv_32_to_size(data, offset, size);
+ *valuep = data;
return 0;
}
enum pci_size_t size)
{
struct mvebu_pcie *pcie = dev_get_plat(bus);
- u32 data;
+ int busno = PCI_BUS(bdf) - dev_seq(bus);
+ u32 addr, data;
debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
debug("(addr,size,val)=(0x%04x, %d, 0x%08lx)\n", offset, size, value);
- if (!mvebu_pcie_valid_addr(pcie, bdf)) {
+ if (!mvebu_pcie_valid_addr(pcie, busno, PCI_DEV(bdf), PCI_FUNC(bdf))) {
debug("- out of range\n");
return 0;
}
+ /*
+ * mvebu has different internal registers mapped into PCI config space
+ * in range 0x10-0x34 for PCI bridge, so do not access PCI config space
+ * for this range and instead write content to driver virtual cfgcache
+ */
+ if (busno == pcie->first_busno && offset >= 0x10 && offset < 0x34) {
+ debug("Writing to cfgcache only\n");
+ data = pcie->cfgcache[(offset - 0x10) / 4];
+ data = pci_conv_size_to_32(data, value, offset, size);
+ /* mvebu PCI bridge does not have configurable bars */
+ if ((offset & ~3) == PCI_BASE_ADDRESS_0 ||
+ (offset & ~3) == PCI_BASE_ADDRESS_1)
+ data = 0x0;
+ pcie->cfgcache[(offset - 0x10) / 4] = data;
+ /* mvebu has its own way how to set PCI primary bus number */
+ if (offset == PCI_PRIMARY_BUS) {
+ pcie->first_busno = data & 0xff;
+ debug("Primary bus number was changed to %d\n",
+ pcie->first_busno);
+ }
+ /* mvebu has its own way how to set PCI secondary bus number */
+ if (offset == PCI_SECONDARY_BUS ||
+ (offset == PCI_PRIMARY_BUS && size != PCI_SIZE_8)) {
+ pcie->sec_busno = (data >> 8) & 0xff;
+ mvebu_pcie_set_local_bus_nr(pcie, pcie->sec_busno);
+ debug("Secondary bus number was changed to %d\n",
+ pcie->sec_busno);
+ }
+ return 0;
+ } else if (busno == pcie->first_busno &&
+ (offset & ~3) == PCI_ROM_ADDRESS1) {
+ /* mvebu has Expansion ROM Base Address (0x38) at offset 0x30 */
+ offset -= PCI_ROM_ADDRESS1 - PCIE_EXP_ROM_BAR_OFF;
+ }
+
+ /*
+ * PCI bridge is device 0 at primary bus but mvebu has it mapped on
+ * secondary bus with device number 1.
+ */
+ if (busno == pcie->first_busno)
+ addr = PCIE_CONF_ADDR(pcie->sec_busno, 1, 0, offset);
+ else
+ addr = PCIE_CONF_ADDR(busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset);
+
/* write address */
- writel(PCIE_CONF_ADDR(bdf, offset), pcie->base + PCIE_CONF_ADDR_OFF);
+ writel(addr, pcie->base + PCIE_CONF_ADDR_OFF);
/* write data */
- data = pci_conv_size_to_32(0, value, offset, size);
- writel(data, pcie->base + PCIE_CONF_DATA_OFF);
+ switch (size) {
+ case PCI_SIZE_8:
+ writeb(value, pcie->base + PCIE_CONF_DATA_OFF + (offset & 3));
+ break;
+ case PCI_SIZE_16:
+ writew(value, pcie->base + PCIE_CONF_DATA_OFF + (offset & 2));
+ break;
+ case PCI_SIZE_32:
+ writel(value, pcie->base + PCIE_CONF_DATA_OFF);
+ break;
+ default:
+ return -EINVAL;
+ }
return 0;
}
struct mvebu_pcie *pcie = dev_get_plat(dev);
struct udevice *ctlr = pci_get_controller(dev);
struct pci_controller *hose = dev_get_uclass_priv(ctlr);
- int bus = dev_seq(dev);
u32 reg;
- debug("%s: PCIe %d.%d - up, base %08x\n", __func__,
- pcie->port, pcie->lane, (u32)pcie->base);
-
- /* Read Id info and local bus/dev */
- debug("direct conf read %08x, local bus %d, local dev %d\n",
- readl(pcie->base), mvebu_pcie_get_local_bus_nr(pcie),
- mvebu_pcie_get_local_dev_nr(pcie));
+ /* Setup PCIe controller to Root Complex mode */
+ reg = readl(pcie->base + PCIE_CTRL_OFF);
+ reg |= PCIE_CTRL_RC_MODE;
+ writel(reg, pcie->base + PCIE_CTRL_OFF);
- pcie->first_busno = bus;
- pcie->local_dev = 1;
+ /*
+ * Change Class Code of PCI Bridge device to PCI Bridge (0x600400)
+ * because default value is Memory controller (0x508000) which
+ * U-Boot cannot recognize as P2P Bridge.
+ *
+ * Note that this mvebu PCI Bridge does not have compliant Type 1
+ * Configuration Space. Header Type is reported as Type 0 and in
+ * range 0x10-0x34 it has aliased internal mvebu registers 0x10-0x34
+ * (e.g. PCIE_BAR_LO_OFF) and register 0x38 is reserved.
+ *
+ * Driver for this range redirects access to virtual cfgcache[] buffer
+ * which avoids changing internal mvebu registers. And changes Header
+ * Type response value to Type 1.
+ */
+ reg = readl(pcie->base + PCIE_DEV_REV_OFF);
+ reg &= ~0xffffff00;
+ reg |= (PCI_CLASS_BRIDGE_PCI << 8) << 8;
+ writel(reg, pcie->base + PCIE_DEV_REV_OFF);
- mvebu_pcie_set_local_bus_nr(pcie, bus);
- mvebu_pcie_set_local_dev_nr(pcie, pcie->local_dev);
+ /*
+ * mvebu uses local bus number and local device number to determinate
+ * type of config request. Type 0 is used if target bus number equals
+ * local bus number and target device number differs from local device
+ * number. Type 1 is used if target bus number differs from local bus
+ * number. And when target bus number equals local bus number and
+ * target device equals local device number then request is routed to
+ * PCI Bridge which represent local PCIe Root Port.
+ *
+ * It means that PCI primary and secondary buses shares one bus number
+ * which is configured via local bus number. Determination if config
+ * request should go to primary or secondary bus is done based on local
+ * device number.
+ *
+ * PCIe is point-to-point bus, so at secondary bus is always exactly one
+ * device with number 0. So set local device number to 1, it would not
+ * conflict with any device on secondary bus number and will ensure that
+ * accessing secondary bus and all buses behind secondary would work
+ * automatically and correctly. Therefore this configuration of local
+ * device number implies that setting of local bus number configures
+ * secondary bus number. Set it to 0 as U-Boot CONFIG_PCI_PNP code will
+ * later configure it via config write requests to the correct value.
+ * mvebu_pcie_write_config() catches config write requests which tries
+ * to change primary/secondary bus number and correctly updates local
+ * bus number based on new secondary bus number.
+ *
+ * With this configuration is PCI Bridge available at secondary bus as
+ * device number 1. But it must be available at primary bus as device
+ * number 0. So in mvebu_pcie_read_config() and mvebu_pcie_write_config()
+ * functions rewrite address to the real one when accessing primary bus.
+ */
+ mvebu_pcie_set_local_bus_nr(pcie, 0);
+ mvebu_pcie_set_local_dev_nr(pcie, 1);
pcie->mem.start = (u32)mvebu_pcie_membase;
- pcie->mem.end = pcie->mem.start + PCIE_MEM_SIZE - 1;
- mvebu_pcie_membase += PCIE_MEM_SIZE;
+ pcie->mem.end = pcie->mem.start + MBUS_PCI_MEM_SIZE - 1;
+ mvebu_pcie_membase += MBUS_PCI_MEM_SIZE;
if (mvebu_mbus_add_window_by_id(pcie->mem_target, pcie->mem_attr,
(phys_addr_t)pcie->mem.start,
- PCIE_MEM_SIZE)) {
+ MBUS_PCI_MEM_SIZE)) {
printf("PCIe unable to add mbus window for mem at %08x+%08x\n",
- (u32)pcie->mem.start, PCIE_MEM_SIZE);
+ (u32)pcie->mem.start, MBUS_PCI_MEM_SIZE);
}
pcie->io.start = (u32)mvebu_pcie_iobase;
/* Setup windows and configure host bridge */
mvebu_pcie_setup_wins(pcie);
- /* Master + slave enable. */
- reg = readl(pcie->base + PCIE_CMD_OFF);
- reg |= PCI_COMMAND_MEMORY;
- reg |= PCI_COMMAND_IO;
- reg |= PCI_COMMAND_MASTER;
- reg |= BIT(10); /* disable interrupts */
- writel(reg, pcie->base + PCIE_CMD_OFF);
-
/* PCI memory space */
pci_set_region(hose->regions + 0, pcie->mem.start,
- pcie->mem.start, PCIE_MEM_SIZE, PCI_REGION_MEM);
+ pcie->mem.start, MBUS_PCI_MEM_SIZE, PCI_REGION_MEM);
pci_set_region(hose->regions + 1,
0, 0,
gd->ram_size,
writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0));
writel(0, pcie->base + PCIE_BAR_HI_OFF(0));
+ /* PCI Bridge support 32-bit I/O and 64-bit prefetch mem addressing */
+ pcie->cfgcache[(PCI_IO_BASE - 0x10) / 4] =
+ PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8);
+ pcie->cfgcache[(PCI_PREF_MEMORY_BASE - 0x10) / 4] =
+ PCI_PREF_RANGE_TYPE_64 | (PCI_PREF_RANGE_TYPE_64 << 16);
+
return 0;
}
if (ret < 0)
goto err;
- /* Check link and skip ports that have no link */
- if (!mvebu_pcie_link_up(pcie)) {
- debug("%s: %s - down\n", __func__, pcie->name);
- ret = -ENODEV;
- goto err;
- }
-
return 0;
err:
struct udevice *dev;
ofnode subnode;
- /* Lookup eth driver */
+ /* Lookup pci driver */
drv = lists_uclass_lookup(UCLASS_PCI);
if (!drv) {
puts("Cannot find PCI driver\n");
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2017-2020 NXP
+ * Copyright 2017-2021 NXP
* Copyright 2014-2015 Freescale Semiconductor, Inc.
* Layerscape PCIe driver
*/
#include "pcie_layerscape.h"
#include "pcie_layerscape_fixup_common.h"
+int next_stream_id;
+
static int fdt_pcie_get_nodeoffset(void *blob, struct ls_pcie_rc *pcie_rc)
{
int nodeoffset;
{
ft_pcie_ep_fix(blob, pcie_rc);
ft_pcie_rc_fix(blob, pcie_rc);
+
+ pcie_rc->stream_id_cur = 0;
+ pcie_rc->next_lut_index = 0;
}
/* Fixup Kernel DT for PCIe */
ft_pcie_ls_setup(blob, pcie_rc);
#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
+ next_stream_id = FSL_PEX_STREAM_ID_START;
fdt_fixup_pcie_ls(blob);
#endif
}
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2019-2020 NXP
+ * Copyright 2019-2021 NXP
*
* PCIe DT fixup for NXP Layerscape SoCs
* Author: Wasim Khan <wasim.khan@nxp.com>
#include <fdt_support.h>
#include "pcie_layerscape_fixup_common.h"
+extern int next_stream_id;
+
void ft_pci_setup(void *blob, struct bd_info *bd)
{
#if defined(CONFIG_PCIE_LAYERSCAPE_GEN4)
/* returns the next available streamid for pcie, -errno if failed */
int pcie_next_streamid(int currentid, int idx)
{
- static int next_stream_id = FSL_PEX_STREAM_ID_START;
-
if (next_stream_id > FSL_PEX_STREAM_ID_END)
return -EINVAL;
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
- * Copyright 2018-2020 NXP
+ * Copyright 2018-2021 NXP
*
* PCIe Gen4 driver for NXP Layerscape SoCs
* Author: Hou Zhiqiang <Minder.Hou@gmail.com>
ccsr_writel(pcie, PAB_AXI_PIO_CTRL(0), val);
ls_pcie_g4_setup_wins(pcie);
-
- pcie->stream_id_cur = 0;
}
static void ls_pcie_g4_ep_inbound_win_set(struct ls_pcie_g4 *pcie, int pf,
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
- * Copyright 2018-2020 NXP
+ * Copyright 2018-2021 NXP
*
* PCIe Gen4 driver for NXP Layerscape SoCs
* Author: Hou Zhiqiang <Minder.Hou@gmail.com>
{
ft_pcie_rc_layerscape_gen4_fix(blob, pcie);
ft_pcie_ep_layerscape_gen4_fix(blob, pcie);
+
+ pcie->stream_id_cur = 0;
+ pcie->next_lut_index = 0;
}
/* Fixup Kernel DT for PCIe */
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2020 NXP
+ * Copyright 2020,2021 NXP
* Layerscape PCIe driver
*/
DECLARE_GLOBAL_DATA_PTR;
+struct ls_pcie_drvdata {
+ u32 lut_offset;
+ u32 ctrl_offset;
+ bool big_endian;
+};
+
static void ls_pcie_cfg0_set_busdev(struct ls_pcie_rc *pcie_rc, u32 busdev)
{
struct ls_pcie *pcie = pcie_rc->pcie;
ls_pcie_dbi_ro_wr_dis(pcie);
ls_pcie_disable_bars(pcie_rc);
- pcie_rc->stream_id_cur = 0;
}
static int ls_pcie_probe(struct udevice *dev)
{
+ const struct ls_pcie_drvdata *drvdata = (void *)dev_get_driver_data(dev);
struct ls_pcie_rc *pcie_rc = dev_get_priv(dev);
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(dev);
pcie_rc->pcie = pcie;
+ /* try resource name of the official binding first */
ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
- "dbi", &pcie_rc->dbi_res);
+ "regs", &pcie_rc->dbi_res);
+ if (ret)
+ ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
+ "dbi", &pcie_rc->dbi_res);
if (ret) {
printf("ls-pcie: resource \"dbi\" not found\n");
return ret;
if (pcie->mode == PCI_HEADER_TYPE_NORMAL)
return 0;
- ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
- "lut", &pcie_rc->lut_res);
- if (!ret)
- pcie->lut = map_physmem(pcie_rc->lut_res.start,
- fdt_resource_size(&pcie_rc->lut_res),
- MAP_NOCACHE);
+ if (drvdata) {
+ pcie->lut = pcie->dbi + drvdata->lut_offset;
+ } else {
+ ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
+ "lut", &pcie_rc->lut_res);
+ if (!ret)
+ pcie->lut = map_physmem(pcie_rc->lut_res.start,
+ fdt_resource_size(&pcie_rc->lut_res),
+ MAP_NOCACHE);
+ }
- ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
- "ctrl", &pcie_rc->ctrl_res);
- if (!ret)
- pcie->ctrl = map_physmem(pcie_rc->ctrl_res.start,
- fdt_resource_size(&pcie_rc->ctrl_res),
- MAP_NOCACHE);
- if (!pcie->ctrl)
- pcie->ctrl = pcie->lut;
+ if (drvdata) {
+ pcie->ctrl = pcie->lut + drvdata->ctrl_offset;
+ } else {
+ ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
+ "ctrl", &pcie_rc->ctrl_res);
+ if (!ret)
+ pcie->ctrl = map_physmem(pcie_rc->ctrl_res.start,
+ fdt_resource_size(&pcie_rc->ctrl_res),
+ MAP_NOCACHE);
+ if (!pcie->ctrl)
+ pcie->ctrl = pcie->lut;
+ }
if (!pcie->ctrl) {
printf("%s: NOT find CTRL\n", dev->name);
pcie_rc->cfg1 = pcie_rc->cfg0 +
fdt_resource_size(&pcie_rc->cfg_res) / 2;
- pcie->big_endian = fdtdec_get_bool(fdt, node, "big-endian");
+ if (drvdata)
+ pcie->big_endian = drvdata->big_endian;
+ else
+ pcie->big_endian = fdtdec_get_bool(fdt, node, "big-endian");
debug("%s dbi:%lx lut:%lx ctrl:0x%lx cfg0:0x%lx, big-endian:%d\n",
dev->name, (unsigned long)pcie->dbi, (unsigned long)pcie->lut,
.write_config = ls_pcie_write_config,
};
+static const struct ls_pcie_drvdata ls1028a_drvdata = {
+ .lut_offset = 0x80000,
+ .ctrl_offset = 0x40000,
+ .big_endian = false,
+};
+
static const struct udevice_id ls_pcie_ids[] = {
{ .compatible = "fsl,ls-pcie" },
+ { .compatible = "fsl,ls1028a-pcie", .data = (ulong)&ls1028a_drvdata },
{ }
};
config PHY_SUN4I_USB
bool "Allwinner Sun4I USB PHY driver"
depends on ARCH_SUNXI
+ select DM_REGULATOR
select PHY
help
Enable this to support the transceiver that is part of Allwinner
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/err.h>
+#include <power/regulator.h>
#define REG_ISCR 0x00
#define REG_PHYCTL_A10 0x04
void __iomem *base;
const struct sun4i_usb_phy_cfg *cfg;
struct sun4i_usb_phy_plat *usb_phy;
+ struct udevice *vbus_power_supply;
};
static int initial_usb_scan_delay = CONFIG_INITIAL_USB_SCAN_DELAY;
{
struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
- int err, retries = 3;
+ int err = 1, retries = 3;
- debug("%s: id_det = %d\n", __func__, usb_phy->gpio_id_det);
-
- if (usb_phy->gpio_vbus_det < 0)
- return usb_phy->gpio_vbus_det;
-
- err = gpio_get_value(usb_phy->gpio_vbus_det);
- /*
- * Vbus may have been provided by the board and just been turned of
- * some milliseconds ago on reset, what we're measuring then is a
- * residual charge on Vbus, sleep a bit and try again.
- */
- while (err > 0 && retries--) {
- mdelay(100);
+ if (usb_phy->gpio_vbus_det >= 0) {
err = gpio_get_value(usb_phy->gpio_vbus_det);
+ /*
+ * Vbus may have been provided by the board and just turned off
+ * some milliseconds ago on reset. What we're measuring then is
+ * a residual charge on Vbus. Sleep a bit and try again.
+ */
+ while (err > 0 && retries--) {
+ mdelay(100);
+ err = gpio_get_value(usb_phy->gpio_vbus_det);
+ }
+ } else if (data->vbus_power_supply) {
+ err = regulator_get_enable(data->vbus_power_supply);
}
return err;
struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
- debug("%s: id_det = %d\n", __func__, usb_phy->gpio_id_det);
-
if (usb_phy->gpio_id_det < 0)
return usb_phy->gpio_id_det;
if (IS_ERR(data->base))
return PTR_ERR(data->base);
+ device_get_supply_regulator(dev, "usb0_vbus_power-supply",
+ &data->vbus_power_supply);
+
data->usb_phy = plat;
for (i = 0; i < data->cfg->num_phys; i++) {
struct sun4i_usb_phy_plat *phy = &plat[i];
help
Support pin multiplexing and pin configuration control on
Samsung's Exynos7420 SoC.
+
+config PINCTRL_EXYNOS78x0
+ bool "Samsung Exynos78x0 pinctrl driver"
+ depends on ARCH_EXYNOS && PINCTRL_FULL
+ select PINCTRL_EXYNOS
+ help
+ Support pin multiplexing and pin configuration control on
+ Samsung's Exynos78x0 SoC.
obj-$(CONFIG_PINCTRL_EXYNOS) += pinctrl-exynos.o
obj-$(CONFIG_PINCTRL_EXYNOS7420) += pinctrl-exynos7420.o
+obj-$(CONFIG_PINCTRL_EXYNOS78x0) += pinctrl-exynos78x0.o
* Thomas Abraham <thomas.ab@samsung.com>
*/
+#include <log.h>
#include <common.h>
#include <dm.h>
#include <errno.h>
u32 *pin)
{
struct exynos_pinctrl_priv *priv = dev_get_priv(dev);
- const struct samsung_pin_ctrl *pin_ctrl = priv->pin_ctrl;
- const struct samsung_pin_bank_data *bank_data = pin_ctrl->pin_banks;
- u32 nr_banks = pin_ctrl->nr_banks, idx = 0;
+ const struct samsung_pin_ctrl *pin_ctrl_array = priv->pin_ctrl;
+ const struct samsung_pin_bank_data *bank_data;
+ u32 nr_banks, pin_ctrl_idx = 0, idx = 0, bank_base;
char bank[10];
/*
*pin = pin_name[++idx] - '0';
/* lookup the pin bank data using the pin bank name */
- for (idx = 0; idx < nr_banks; idx++)
- if (!strcmp(bank, bank_data[idx].name))
+ while (true) {
+ const struct samsung_pin_ctrl *pin_ctrl = &pin_ctrl_array[pin_ctrl_idx];
+
+ nr_banks = pin_ctrl->nr_banks;
+ if (!nr_banks)
break;
- return priv->base + bank_data[idx].offset;
+ bank_data = pin_ctrl->pin_banks;
+ for (idx = 0; idx < nr_banks; idx++) {
+ debug("pinctrl[%d] bank_data[%d] name is: %s\n",
+ pin_ctrl_idx, idx, bank_data[idx].name);
+ if (!strcmp(bank, bank_data[idx].name)) {
+ bank_base = priv->base + bank_data[idx].offset;
+ break;
+ }
+ }
+ pin_ctrl_idx++;
+ }
+
+ return bank_base;
}
/**
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Exynos78x0 pinctrl driver.
+ *
+ * Copyright (c) 2020 Dzmitry Sankouski (dsankouski@gmail.com)
+ *
+ * based on drivers/pinctrl/exynos/pinctrl-exynos7420.c :
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <thomas.ab@samsung.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <dm/pinctrl.h>
+#include <dm/root.h>
+#include <fdtdec.h>
+#include <asm/arch/pinmux.h>
+#include "pinctrl-exynos.h"
+
+static const struct pinctrl_ops exynos78x0_pinctrl_ops = {
+ .set_state = exynos_pinctrl_set_state
+};
+
+/* pin banks of exynos78x0 pin-controller 0 (ALIVE) */
+static const struct samsung_pin_bank_data exynos78x0_pin_banks0[] = {
+ EXYNOS_PIN_BANK(6, 0x000, "etc0"),
+ EXYNOS_PIN_BANK(3, 0x020, "etc1"),
+ EXYNOS_PIN_BANK(8, 0x040, "gpa0"),
+ EXYNOS_PIN_BANK(8, 0x060, "gpa1"),
+ EXYNOS_PIN_BANK(8, 0x080, "gpa2"),
+ EXYNOS_PIN_BANK(5, 0x0a0, "gpa3"),
+ EXYNOS_PIN_BANK(2, 0x0c0, "gpq0"),
+};
+
+/* pin banks of exynos78x0 pin-controller 1 (CCORE) */
+static const struct samsung_pin_bank_data exynos78x0_pin_banks1[] = {
+ EXYNOS_PIN_BANK(2, 0x000, "gpm0"),
+};
+
+/* pin banks of exynos78x0 pin-controller 2 (DISPAUD) */
+static const struct samsung_pin_bank_data exynos78x0_pin_banks2[] = {
+ EXYNOS_PIN_BANK(4, 0x000, "gpz0"),
+ EXYNOS_PIN_BANK(6, 0x020, "gpz1"),
+ EXYNOS_PIN_BANK(4, 0x040, "gpz2"),
+};
+
+/* pin banks of exynos78x0 pin-controller 4 (FSYS) */
+static const struct samsung_pin_bank_data exynos78x0_pin_banks4[] = {
+ EXYNOS_PIN_BANK(3, 0x000, "gpr0"),
+ EXYNOS_PIN_BANK(8, 0x020, "gpr1"),
+ EXYNOS_PIN_BANK(2, 0x040, "gpr2"),
+ EXYNOS_PIN_BANK(4, 0x060, "gpr3"),
+ EXYNOS_PIN_BANK(6, 0x080, "gpr4"),
+};
+
+/* pin banks of exynos78x0 pin-controller 6 (TOP) */
+static const struct samsung_pin_bank_data exynos78x0_pin_banks6[] = {
+ EXYNOS_PIN_BANK(4, 0x000, "gpb0"),
+ EXYNOS_PIN_BANK(3, 0x020, "gpc0"),
+ EXYNOS_PIN_BANK(4, 0x040, "gpc1"),
+ EXYNOS_PIN_BANK(4, 0x060, "gpc4"),
+ EXYNOS_PIN_BANK(2, 0x080, "gpc5"),
+ EXYNOS_PIN_BANK(4, 0x0a0, "gpc6"),
+ EXYNOS_PIN_BANK(2, 0x0c0, "gpc8"),
+ EXYNOS_PIN_BANK(2, 0x0e0, "gpc9"),
+ EXYNOS_PIN_BANK(7, 0x100, "gpd1"),
+ EXYNOS_PIN_BANK(6, 0x120, "gpd2"),
+ EXYNOS_PIN_BANK(8, 0x140, "gpd3"),
+ EXYNOS_PIN_BANK(7, 0x160, "gpd4"),
+ EXYNOS_PIN_BANK(5, 0x180, "gpd5"),
+ EXYNOS_PIN_BANK(3, 0x1a0, "gpe0"),
+ EXYNOS_PIN_BANK(4, 0x1c0, "gpf0"),
+ EXYNOS_PIN_BANK(2, 0x1e0, "gpf1"),
+ EXYNOS_PIN_BANK(2, 0x200, "gpf2"),
+ EXYNOS_PIN_BANK(4, 0x220, "gpf3"),
+ EXYNOS_PIN_BANK(5, 0x240, "gpf4"),
+};
+
+const struct samsung_pin_ctrl exynos78x0_pin_ctrl[] = {
+ {
+ /* pin-controller instance 0 Alive data */
+ .pin_banks = exynos78x0_pin_banks0,
+ .nr_banks = ARRAY_SIZE(exynos78x0_pin_banks0),
+ }, {
+ /* pin-controller instance 1 CCORE data */
+ .pin_banks = exynos78x0_pin_banks1,
+ .nr_banks = ARRAY_SIZE(exynos78x0_pin_banks1),
+ }, {
+ /* pin-controller instance 2 DISPAUD data */
+ .pin_banks = exynos78x0_pin_banks2,
+ .nr_banks = ARRAY_SIZE(exynos78x0_pin_banks2),
+ }, {
+ /* pin-controller instance 4 FSYS data */
+ .pin_banks = exynos78x0_pin_banks4,
+ .nr_banks = ARRAY_SIZE(exynos78x0_pin_banks4),
+ }, {
+ /* pin-controller instance 6 TOP data */
+ .pin_banks = exynos78x0_pin_banks6,
+ .nr_banks = ARRAY_SIZE(exynos78x0_pin_banks6),
+ },
+ {/* list terminator */}
+};
+
+static const struct udevice_id exynos78x0_pinctrl_ids[] = {
+ { .compatible = "samsung,exynos78x0-pinctrl",
+ .data = (ulong)exynos78x0_pin_ctrl },
+ { }
+};
+
+U_BOOT_DRIVER(pinctrl_exynos78x0) = {
+ .name = "pinctrl_exynos78x0",
+ .id = UCLASS_PINCTRL,
+ .of_match = exynos78x0_pinctrl_ids,
+ .priv_auto = sizeof(struct exynos_pinctrl_priv),
+ .ops = &exynos78x0_pinctrl_ops,
+ .probe = exynos_pinctrl_probe,
+};
#include <hwspinlock.h>
#include <log.h>
#include <malloc.h>
-#include <asm/arch/gpio.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <dm/device_compat.h>
#include <linux/err.h>
#include <linux/libfdt.h>
+#include "../gpio/stm32_gpio_priv.h"
+
#define MAX_PINS_ONE_IP 70
#define MODE_BITS_MASK 3
#define OSPEED_MASK 3
return 0;
}
+#if !IS_ENABLED(CONFIG_SYSRESET_CMD_POWEROFF)
int do_poweroff(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
pmic_bus_write(AXP152_SHUTDOWN, AXP152_POWEROFF);
/* not reached */
return 0;
}
+#endif
return 0;
}
+#if !IS_ENABLED(CONFIG_SYSRESET_CMD_POWEROFF)
int do_poweroff(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
pmic_bus_write(AXP209_SHUTDOWN, AXP209_POWEROFF);
/* not reached */
return 0;
}
+#endif
return 0;
}
+#if !IS_ENABLED(CONFIG_SYSRESET_CMD_POWEROFF)
int do_poweroff(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
pmic_bus_write(AXP221_SHUTDOWN, AXP221_SHUTDOWN_POWEROFF);
/* not reached */
return 0;
}
+#endif
return ret;
}
-#ifndef CONFIG_PSCI_RESET
+#if !CONFIG_IS_ENABLED(ARM_PSCI_FW) && !IS_ENABLED(CONFIG_SYSRESET_CMD_POWEROFF)
int do_poweroff(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
pmic_bus_write(AXP305_SHUTDOWN, AXP305_POWEROFF);
return pmic_bus_init();
}
+#if !IS_ENABLED(CONFIG_SYSRESET_CMD_POWEROFF)
int do_poweroff(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
pmic_bus_write(AXP809_SHUTDOWN, AXP809_SHUTDOWN_POWEROFF);
/* not reached */
return 0;
}
+#endif
return 0;
}
+#if !IS_ENABLED(CONFIG_SYSRESET_CMD_POWEROFF)
int do_poweroff(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
pmic_bus_write(AXP818_SHUTDOWN, AXP818_SHUTDOWN_POWEROFF);
/* not reached */
return 0;
}
+#endif
config PMIC_AXP
bool "Enable Driver Model for X-Powers AXP PMICs"
depends on DM_I2C
+ select SYSRESET_CMD_POWEROFF if SYSRESET && CMD_POWEROFF
+ imply CMD_POWEROFF if SYSRESET
help
This config enables driver-model PMIC uclass features for
X-Powers AXP152, AXP2xx, and AXP8xx PMICs.
// SPDX-License-Identifier: GPL-2.0+
+#include <axp_pmic.h>
#include <dm.h>
+#include <dm/lists.h>
#include <i2c.h>
#include <power/pmic.h>
+#include <sysreset.h>
+
+#if CONFIG_IS_ENABLED(SYSRESET)
+static int axp_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+ int ret;
+
+ if (type != SYSRESET_POWER_OFF)
+ return -EPROTONOSUPPORT;
+
+ ret = pmic_clrsetbits(dev->parent, AXP152_SHUTDOWN, 0, AXP152_POWEROFF);
+ if (ret < 0)
+ return ret;
+
+ return -EINPROGRESS;
+}
+
+static struct sysreset_ops axp_sysreset_ops = {
+ .request = axp_sysreset_request,
+};
+
+U_BOOT_DRIVER(axp_sysreset) = {
+ .name = "axp_sysreset",
+ .id = UCLASS_SYSRESET,
+ .ops = &axp_sysreset_ops,
+};
+#endif
static int axp_pmic_reg_count(struct udevice *dev)
{
.write = dm_i2c_write,
};
+static int axp_pmic_bind(struct udevice *dev)
+{
+ int ret;
+
+ ret = dm_scan_fdt_dev(dev);
+ if (ret)
+ return ret;
+
+ if (CONFIG_IS_ENABLED(SYSRESET)) {
+ ret = device_bind_driver_to_node(dev, "axp_sysreset", "axp_sysreset",
+ dev_ofnode(dev), NULL);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
static const struct udevice_id axp_pmic_ids[] = {
{ .compatible = "x-powers,axp152" },
{ .compatible = "x-powers,axp202" },
.name = "axp_pmic",
.id = UCLASS_PMIC,
.of_match = axp_pmic_ids,
- .bind = dm_scan_fdt_dev,
+ .bind = axp_pmic_bind,
.ops = &axp_pmic_ops,
};
tcnt = period_ns / rate_ns;
tcmp = duty_ns / rate_ns;
debug("%s: tcnt %u, tcmp %u\n", __func__, tcnt, tcmp);
+
+ /* Ensure that the comparitor will actually hit the target */
+ if (tcmp == tcnt)
+ tcmp = tcnt - 1;
offset = channel * 3;
writel(tcnt, ®s->tcntb0 + offset);
writel(tcmp, ®s->tcmpb0 + offset);
help
Choose this option to add support for U QUICC Engine.
+config SYS_QE_FW_ADDR
+ hex "QE Firmware Address"
+ depends on FMAN_ENET || QE || U_QE
+ default 0x0
choice
prompt "QUICC Engine FMan ethernet firmware location"
depends on FMAN_ENET || QE
sifive_ddr_phy_fixup(denali_phy);
/* check size */
- priv->info.size = get_ram_size((long *)priv->info.base,
+ priv->info.size = get_ram_size((long *)(uintptr_t)priv->info.base,
ddr_size);
debug("%s : %lx\n", __func__, (uintptr_t)priv->info.size);
return ret;
}
- priv->ctl = (struct sifive_ddrctl *)dev_read_addr_index(dev, 0);
- priv->phy = (struct sifive_ddrphy *)dev_read_addr_index(dev, 1);
- priv->physical_filter_ctrl = (u32 *)dev_read_addr_index(dev, 2);
+ priv->ctl = (struct sifive_ddrctl *)dev_read_addr_index_ptr(dev, 0);
+ priv->phy = (struct sifive_ddrphy *)dev_read_addr_index_ptr(dev, 1);
+ priv->physical_filter_ctrl = (u32 *)dev_read_addr_index_ptr(dev, 2);
return sifive_ddr_setup(dev);
#endif
priv->info.base = STM32_DDR_BASE;
-#if !defined(CONFIG_TFABOOT) && \
- (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
- priv->info.size = 0;
- ret = stm32mp1_ddr_setup(dev);
+ if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+ priv->info.size = 0;
+ ret = stm32mp1_ddr_setup(dev);
+
+ return log_ret(ret);
+ }
- return log_ret(ret);
-#else
ofnode node = stm32mp1_ddr_get_ofnode(dev);
priv->info.size = ofnode_read_u32_default(node, "st,mem-size", 0);
return 0;
-#endif
}
static int stm32mp1_ddr_get_info(struct udevice *dev, struct ram_info *info)
static const struct udevice_id ds1337_rtc_ids[] = {
{ .compatible = "ds1337" },
{ .compatible = "ds1338" },
- { .compatible = "ds1338" },
+ { .compatible = "ds1339" },
{ }
};
static const struct udevice_id rv8803_rtc_ids[] = {
{ .compatible = "microcrystal,rv8803", },
+ { .compatible = "epson,rx8803" },
+ { .compatible = "epson,rx8900" },
{ }
};
config DEBUG_UART_S5P
bool "Samsung S5P"
- depends on ARCH_EXYNOS || ARCH_S5PC1XX
+ depends on ARCH_APPLE || ARCH_EXYNOS || ARCH_S5PC1XX
help
Select this to enable a debug UART using the serial_s5p driver. You
will need to provide parameters to make this work. The driver will
be available until the real driver-model serial is running.
+config DEBUG_UART_MSM_GENI
+ bool "Qualcomm snapdragon"
+ depends on ARCH_SNAPDRAGON
+ help
+ Select this to enable a debug UART using the serial_msm driver. You
+ will need to provide parameters to make this work. The driver will
+ be available until the real driver-model serial is running.
+
config DEBUG_UART_MESON
bool "Amlogic Meson"
depends on MESON_SERIAL
config S5P_SERIAL
bool "Support for Samsung S5P UART"
- depends on ARCH_EXYNOS || ARCH_S5PC1XX
+ depends on ARCH_APPLE || ARCH_EXYNOS || ARCH_S5PC1XX
default y
help
Select this to enable Samsung S5P UART support.
for example APQ8016 and MSM8916.
Single baudrate is supported in current implementation (115200).
+config MSM_GENI_SERIAL
+ bool "Qualcomm on-chip GENI UART"
+ help
+ Support UART based on Generic Interface (GENI) Serial Engine (SE),
+ used on Qualcomm Snapdragon SoCs. Should support all qualcomm SOCs
+ with Qualcomm Universal Peripheral (QUP) Wrapper cores,
+ i.e. newer ones, starting from SDM845.
+ Driver works in FIFO mode.
+ Multiple baudrates supported.
+
config OCTEON_SERIAL_BOOTCMD
bool "MIPS Octeon PCI remote bootcmd input"
depends on ARCH_OCTEON
obj-$(CONFIG_BCM283X_MU_SERIAL) += serial_bcm283x_mu.o
obj-$(CONFIG_BCM283X_PL011_SERIAL) += serial_bcm283x_pl011.o
obj-$(CONFIG_MSM_SERIAL) += serial_msm.o
+obj-$(CONFIG_MSM_GENI_SERIAL) += serial_msm_geni.o
obj-$(CONFIG_MVEBU_A3700_UART) += serial_mvebu_a3700.o
obj-$(CONFIG_MPC8XX_CONS) += serial_mpc8xx.o
obj-$(CONFIG_NULLDEV_SERIAL) += serial_nulldev.o
static const struct udevice_id lpuart_serial_ids[] = {
{ .compatible = "fsl,ls1021a-lpuart", .data =
LPUART_FLAG_REGMAP_32BIT_REG | LPUART_FLAG_REGMAP_ENDIAN_BIG },
+ { .compatible = "fsl,ls1028a-lpuart",
+ .data = LPUART_FLAG_REGMAP_32BIT_REG },
{ .compatible = "fsl,imx7ulp-lpuart",
.data = LPUART_FLAG_REGMAP_32BIT_REG },
{ .compatible = "fsl,vf610-lpuart"},
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm GENI serial engine UART driver
+ *
+ * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
+ *
+ * Based on Linux driver.
+ */
+
+#include <asm/io.h>
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <errno.h>
+#include <linux/compiler.h>
+#include <log.h>
+#include <linux/delay.h>
+#include <malloc.h>
+#include <serial.h>
+#include <watchdog.h>
+#include <linux/bug.h>
+
+#define UART_OVERSAMPLING 32
+#define STALE_TIMEOUT 160
+
+#define USEC_PER_SEC 1000000L
+
+/* Registers*/
+#define GENI_FORCE_DEFAULT_REG 0x20
+#define GENI_SER_M_CLK_CFG 0x48
+#define GENI_SER_S_CLK_CFG 0x4C
+#define SE_HW_PARAM_0 0xE24
+#define SE_GENI_STATUS 0x40
+#define SE_GENI_S_CMD0 0x630
+#define SE_GENI_S_CMD_CTRL_REG 0x634
+#define SE_GENI_S_IRQ_CLEAR 0x648
+#define SE_GENI_S_IRQ_STATUS 0x640
+#define SE_GENI_S_IRQ_EN 0x644
+#define SE_GENI_M_CMD0 0x600
+#define SE_GENI_M_CMD_CTRL_REG 0x604
+#define SE_GENI_M_IRQ_CLEAR 0x618
+#define SE_GENI_M_IRQ_STATUS 0x610
+#define SE_GENI_M_IRQ_EN 0x614
+#define SE_GENI_TX_FIFOn 0x700
+#define SE_GENI_RX_FIFOn 0x780
+#define SE_GENI_TX_FIFO_STATUS 0x800
+#define SE_GENI_RX_FIFO_STATUS 0x804
+#define SE_GENI_TX_WATERMARK_REG 0x80C
+#define SE_GENI_TX_PACKING_CFG0 0x260
+#define SE_GENI_TX_PACKING_CFG1 0x264
+#define SE_GENI_RX_PACKING_CFG0 0x284
+#define SE_GENI_RX_PACKING_CFG1 0x288
+#define SE_UART_RX_STALE_CNT 0x294
+#define SE_UART_TX_TRANS_LEN 0x270
+#define SE_UART_TX_STOP_BIT_LEN 0x26c
+#define SE_UART_TX_WORD_LEN 0x268
+#define SE_UART_RX_WORD_LEN 0x28c
+#define SE_UART_TX_TRANS_CFG 0x25c
+#define SE_UART_TX_PARITY_CFG 0x2a4
+#define SE_UART_RX_TRANS_CFG 0x280
+#define SE_UART_RX_PARITY_CFG 0x2a8
+
+#define M_TX_FIFO_WATERMARK_EN (BIT(30))
+#define DEF_TX_WM 2
+/* GENI_FORCE_DEFAULT_REG fields */
+#define FORCE_DEFAULT (BIT(0))
+
+#define S_CMD_ABORT_EN (BIT(5))
+
+#define UART_START_READ 0x1
+
+/* GENI_M_CMD_CTRL_REG */
+#define M_GENI_CMD_CANCEL (BIT(2))
+#define M_GENI_CMD_ABORT (BIT(1))
+#define M_GENI_DISABLE (BIT(0))
+
+#define M_CMD_ABORT_EN (BIT(5))
+#define M_CMD_DONE_EN (BIT(0))
+#define M_CMD_DONE_DISABLE_MASK (~M_CMD_DONE_EN)
+
+#define S_GENI_CMD_ABORT (BIT(1))
+
+/* GENI_S_CMD0 fields */
+#define S_OPCODE_MSK (GENMASK(31, 27))
+#define S_PARAMS_MSK (GENMASK(26, 0))
+
+/* GENI_STATUS fields */
+#define M_GENI_CMD_ACTIVE (BIT(0))
+#define S_GENI_CMD_ACTIVE (BIT(12))
+#define M_CMD_DONE_EN (BIT(0))
+#define S_CMD_DONE_EN (BIT(0))
+
+#define M_OPCODE_SHIFT 27
+#define S_OPCODE_SHIFT 27
+#define M_TX_FIFO_WATERMARK_EN (BIT(30))
+#define UART_START_TX 0x1
+#define UART_CTS_MASK (BIT(1))
+#define M_SEC_IRQ_EN (BIT(31))
+#define TX_FIFO_WC_MSK (GENMASK(27, 0))
+#define RX_FIFO_WC_MSK (GENMASK(24, 0))
+
+#define S_RX_FIFO_WATERMARK_EN (BIT(26))
+#define S_RX_FIFO_LAST_EN (BIT(27))
+#define M_RX_FIFO_WATERMARK_EN (BIT(26))
+#define M_RX_FIFO_LAST_EN (BIT(27))
+
+/* GENI_SER_M_CLK_CFG/GENI_SER_S_CLK_CFG */
+#define SER_CLK_EN (BIT(0))
+#define CLK_DIV_MSK (GENMASK(15, 4))
+#define CLK_DIV_SHFT 4
+
+/* SE_HW_PARAM_0 fields */
+#define TX_FIFO_WIDTH_MSK (GENMASK(29, 24))
+#define TX_FIFO_WIDTH_SHFT 24
+#define TX_FIFO_DEPTH_MSK (GENMASK(21, 16))
+#define TX_FIFO_DEPTH_SHFT 16
+
+/*
+ * Predefined packing configuration of the serial engine (CFG0, CFG1 regs)
+ * for uart mode.
+ *
+ * Defines following configuration:
+ * - Bits of data per transfer word 8
+ * - Number of words per fifo element 4
+ * - Transfer from MSB to LSB or vice-versa false
+ */
+#define UART_PACKING_CFG0 0xf
+#define UART_PACKING_CFG1 0x0
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct msm_serial_data {
+ phys_addr_t base;
+ u32 baud;
+};
+
+unsigned long root_freq[] = {7372800, 14745600, 19200000, 29491200,
+ 32000000, 48000000, 64000000, 80000000,
+ 96000000, 100000000};
+
+/**
+ * get_clk_cfg() - Get clock rate to apply on clock supplier.
+ * @clk_freq: Desired clock frequency after build-in divider.
+ *
+ * Return: frequency, supported by clock supplier, multiple of clk_freq.
+ */
+static int get_clk_cfg(unsigned long clk_freq)
+{
+ for (int i = 0; i < ARRAY_SIZE(root_freq); i++) {
+ if (!(root_freq[i] % clk_freq))
+ return root_freq[i];
+ }
+ return 0;
+}
+
+/**
+ * get_clk_div_rate() - Find clock supplier frequency, and calculate divisor.
+ * @baud: Baudrate.
+ * @sampling_rate: Clock ticks per character.
+ * @clk_div: Pointer to calculated divisor.
+ *
+ * This function searches for suitable frequency for clock supplier,
+ * calculates divisor for internal divider, based on found frequency,
+ * and stores divisor under clk_div pointer.
+ *
+ * Return: frequency, supported by clock supplier, multiple of clk_freq.
+ */
+static int get_clk_div_rate(u32 baud,
+ u64 sampling_rate, u32 *clk_div)
+{
+ unsigned long ser_clk;
+ unsigned long desired_clk;
+
+ desired_clk = baud * sampling_rate;
+ ser_clk = get_clk_cfg(desired_clk);
+ if (!ser_clk) {
+ pr_err("%s: Can't find matching DFS entry for baud %d\n",
+ __func__, baud);
+ return ser_clk;
+ }
+
+ *clk_div = ser_clk / desired_clk;
+ return ser_clk;
+}
+
+static int geni_serial_set_clock_rate(struct udevice *dev, u64 rate)
+{
+ struct clk *clk;
+ int ret;
+
+ clk = devm_clk_get(dev, "se-clk");
+ if (!clk)
+ return -EINVAL;
+
+ ret = clk_set_rate(clk, rate);
+ return ret;
+}
+
+/**
+ * geni_se_get_tx_fifo_depth() - Get the TX fifo depth of the serial engine
+ * @base: Pointer to the concerned serial engine.
+ *
+ * This function is used to get the depth i.e. number of elements in the
+ * TX fifo of the serial engine.
+ *
+ * Return: TX fifo depth in units of FIFO words.
+ */
+static inline u32 geni_se_get_tx_fifo_depth(long base)
+{
+ u32 tx_fifo_depth;
+
+ tx_fifo_depth = ((readl(base + SE_HW_PARAM_0) & TX_FIFO_DEPTH_MSK) >>
+ TX_FIFO_DEPTH_SHFT);
+ return tx_fifo_depth;
+}
+
+/**
+ * geni_se_get_tx_fifo_width() - Get the TX fifo width of the serial engine
+ * @base: Pointer to the concerned serial engine.
+ *
+ * This function is used to get the width i.e. word size per element in the
+ * TX fifo of the serial engine.
+ *
+ * Return: TX fifo width in bits
+ */
+static inline u32 geni_se_get_tx_fifo_width(long base)
+{
+ u32 tx_fifo_width;
+
+ tx_fifo_width = ((readl(base + SE_HW_PARAM_0) & TX_FIFO_WIDTH_MSK) >>
+ TX_FIFO_WIDTH_SHFT);
+ return tx_fifo_width;
+}
+
+static inline void geni_serial_baud(phys_addr_t base_address, u32 clk_div,
+ int baud)
+{
+ u32 s_clk_cfg = 0;
+
+ s_clk_cfg |= SER_CLK_EN;
+ s_clk_cfg |= (clk_div << CLK_DIV_SHFT);
+
+ writel(s_clk_cfg, base_address + GENI_SER_M_CLK_CFG);
+ writel(s_clk_cfg, base_address + GENI_SER_S_CLK_CFG);
+}
+
+int msm_serial_setbrg(struct udevice *dev, int baud)
+{
+ struct msm_serial_data *priv = dev_get_priv(dev);
+
+ priv->baud = baud;
+ u32 clk_div;
+ u64 clk_rate;
+
+ clk_rate = get_clk_div_rate(baud, UART_OVERSAMPLING, &clk_div);
+ geni_serial_set_clock_rate(dev, clk_rate);
+ geni_serial_baud(priv->base, clk_div, baud);
+
+ return 0;
+}
+
+/**
+ * qcom_geni_serial_poll_bit() - Poll reg bit until desired value or timeout.
+ * @base: Pointer to the concerned serial engine.
+ * @offset: Offset to register address.
+ * @field: AND bitmask for desired bit.
+ * @set: Desired bit value.
+ *
+ * This function is used to get the width i.e. word size per element in the
+ * TX fifo of the serial engine.
+ *
+ * Return: true, when register bit equals desired value, false, when timeout
+ * reached.
+ */
+static bool qcom_geni_serial_poll_bit(const struct udevice *dev, int offset,
+ int field, bool set)
+{
+ u32 reg;
+ struct msm_serial_data *priv = dev_get_priv(dev);
+ unsigned int baud;
+ unsigned int tx_fifo_depth;
+ unsigned int tx_fifo_width;
+ unsigned int fifo_bits;
+ unsigned long timeout_us = 10000;
+
+ baud = 115200;
+
+ if (priv) {
+ baud = priv->baud;
+ if (!baud)
+ baud = 115200;
+ tx_fifo_depth = geni_se_get_tx_fifo_depth(priv->base);
+ tx_fifo_width = geni_se_get_tx_fifo_width(priv->base);
+ fifo_bits = tx_fifo_depth * tx_fifo_width;
+ /*
+ * Total polling iterations based on FIFO worth of bytes to be
+ * sent at current baud. Add a little fluff to the wait.
+ */
+ timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500;
+ }
+
+ timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10;
+ while (timeout_us) {
+ reg = readl(priv->base + offset);
+ if ((bool)(reg & field) == set)
+ return true;
+ udelay(10);
+ timeout_us -= 10;
+ }
+ return false;
+}
+
+static void qcom_geni_serial_setup_tx(u64 base, u32 xmit_size)
+{
+ u32 m_cmd;
+
+ writel(xmit_size, base + SE_UART_TX_TRANS_LEN);
+ m_cmd = UART_START_TX << M_OPCODE_SHIFT;
+ writel(m_cmd, base + SE_GENI_M_CMD0);
+}
+
+static inline void qcom_geni_serial_poll_tx_done(const struct udevice *dev)
+{
+ struct msm_serial_data *priv = dev_get_priv(dev);
+ int done = 0;
+ u32 irq_clear = M_CMD_DONE_EN;
+
+ done = qcom_geni_serial_poll_bit(dev, SE_GENI_M_IRQ_STATUS,
+ M_CMD_DONE_EN, true);
+ if (!done) {
+ writel(M_GENI_CMD_ABORT, priv->base + SE_GENI_M_CMD_CTRL_REG);
+ irq_clear |= M_CMD_ABORT_EN;
+ qcom_geni_serial_poll_bit(dev, SE_GENI_M_IRQ_STATUS,
+ M_CMD_ABORT_EN, true);
+ }
+ writel(irq_clear, priv->base + SE_GENI_M_IRQ_CLEAR);
+}
+
+static u32 qcom_geni_serial_tx_empty(u64 base)
+{
+ return !readl(base + SE_GENI_TX_FIFO_STATUS);
+}
+
+/**
+ * geni_se_setup_s_cmd() - Setup the secondary sequencer
+ * @se: Pointer to the concerned serial engine.
+ * @cmd: Command/Operation to setup in the secondary sequencer.
+ * @params: Parameter for the sequencer command.
+ *
+ * This function is used to configure the secondary sequencer with the
+ * command and its associated parameters.
+ */
+static inline void geni_se_setup_s_cmd(u64 base, u32 cmd, u32 params)
+{
+ u32 s_cmd;
+
+ s_cmd = readl(base + SE_GENI_S_CMD0);
+ s_cmd &= ~(S_OPCODE_MSK | S_PARAMS_MSK);
+ s_cmd |= (cmd << S_OPCODE_SHIFT);
+ s_cmd |= (params & S_PARAMS_MSK);
+ writel(s_cmd, base + SE_GENI_S_CMD0);
+}
+
+static void qcom_geni_serial_start_tx(u64 base)
+{
+ u32 irq_en;
+ u32 status;
+
+ status = readl(base + SE_GENI_STATUS);
+ if (status & M_GENI_CMD_ACTIVE)
+ return;
+
+ if (!qcom_geni_serial_tx_empty(base))
+ return;
+
+ irq_en = readl(base + SE_GENI_M_IRQ_EN);
+ irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN;
+
+ writel(DEF_TX_WM, base + SE_GENI_TX_WATERMARK_REG);
+ writel(irq_en, base + SE_GENI_M_IRQ_EN);
+}
+
+static void qcom_geni_serial_start_rx(struct udevice *dev)
+{
+ u32 status;
+ struct msm_serial_data *priv = dev_get_priv(dev);
+
+ status = readl(priv->base + SE_GENI_STATUS);
+
+ geni_se_setup_s_cmd(priv->base, UART_START_READ, 0);
+
+ setbits_le32(priv->base + SE_GENI_S_IRQ_EN, S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);
+ setbits_le32(priv->base + SE_GENI_M_IRQ_EN, M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
+}
+
+static void qcom_geni_serial_abort_rx(struct udevice *dev)
+{
+ struct msm_serial_data *priv = dev_get_priv(dev);
+
+ u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN;
+
+ writel(S_GENI_CMD_ABORT, priv->base + SE_GENI_S_CMD_CTRL_REG);
+ qcom_geni_serial_poll_bit(dev, SE_GENI_S_CMD_CTRL_REG,
+ S_GENI_CMD_ABORT, false);
+ writel(irq_clear, priv->base + SE_GENI_S_IRQ_CLEAR);
+ writel(FORCE_DEFAULT, priv->base + GENI_FORCE_DEFAULT_REG);
+}
+
+static void msm_geni_serial_setup_rx(struct udevice *dev)
+{
+ struct msm_serial_data *priv = dev_get_priv(dev);
+
+ qcom_geni_serial_abort_rx(dev);
+
+ writel(UART_PACKING_CFG0, priv->base + SE_GENI_RX_PACKING_CFG0);
+ writel(UART_PACKING_CFG1, priv->base + SE_GENI_RX_PACKING_CFG1);
+
+ geni_se_setup_s_cmd(priv->base, UART_START_READ, 0);
+
+ setbits_le32(priv->base + SE_GENI_S_IRQ_EN, S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);
+ setbits_le32(priv->base + SE_GENI_M_IRQ_EN, M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
+}
+
+static int msm_serial_putc(struct udevice *dev, const char ch)
+{
+ struct msm_serial_data *priv = dev_get_priv(dev);
+
+ writel(DEF_TX_WM, priv->base + SE_GENI_TX_WATERMARK_REG);
+ qcom_geni_serial_setup_tx(priv->base, 1);
+
+ qcom_geni_serial_poll_bit(dev, SE_GENI_M_IRQ_STATUS,
+ M_TX_FIFO_WATERMARK_EN, true);
+
+ writel(ch, priv->base + SE_GENI_TX_FIFOn);
+ writel(M_TX_FIFO_WATERMARK_EN, priv->base + SE_GENI_M_IRQ_CLEAR);
+
+ qcom_geni_serial_poll_tx_done(dev);
+
+ return 0;
+}
+
+static int msm_serial_getc(struct udevice *dev)
+{
+ struct msm_serial_data *priv = dev_get_priv(dev);
+ u32 rx_fifo;
+ u32 m_irq_status;
+ u32 s_irq_status;
+
+ writel(1 << S_OPCODE_SHIFT, priv->base + SE_GENI_S_CMD0);
+
+ qcom_geni_serial_poll_bit(dev, SE_GENI_M_IRQ_STATUS, M_SEC_IRQ_EN,
+ true);
+
+ m_irq_status = readl(priv->base + SE_GENI_M_IRQ_STATUS);
+ s_irq_status = readl(priv->base + SE_GENI_S_IRQ_STATUS);
+ writel(m_irq_status, priv->base + SE_GENI_M_IRQ_CLEAR);
+ writel(s_irq_status, priv->base + SE_GENI_S_IRQ_CLEAR);
+ qcom_geni_serial_poll_bit(dev, SE_GENI_RX_FIFO_STATUS, RX_FIFO_WC_MSK,
+ true);
+
+ if (!readl(priv->base + SE_GENI_RX_FIFO_STATUS))
+ return 0;
+
+ rx_fifo = readl(priv->base + SE_GENI_RX_FIFOn);
+ return rx_fifo & 0xff;
+}
+
+static int msm_serial_pending(struct udevice *dev, bool input)
+{
+ struct msm_serial_data *priv = dev_get_priv(dev);
+
+ if (input)
+ return readl(priv->base + SE_GENI_RX_FIFO_STATUS) &
+ RX_FIFO_WC_MSK;
+ else
+ return readl(priv->base + SE_GENI_TX_FIFO_STATUS) &
+ TX_FIFO_WC_MSK;
+
+ return 0;
+}
+
+static const struct dm_serial_ops msm_serial_ops = {
+ .putc = msm_serial_putc,
+ .pending = msm_serial_pending,
+ .getc = msm_serial_getc,
+ .setbrg = msm_serial_setbrg,
+};
+
+static inline void geni_serial_init(struct udevice *dev)
+{
+ struct msm_serial_data *priv = dev_get_priv(dev);
+ phys_addr_t base_address = priv->base;
+ u32 tx_trans_cfg;
+ u32 tx_parity_cfg = 0; /* Disable Tx Parity */
+ u32 rx_trans_cfg = 0;
+ u32 rx_parity_cfg = 0; /* Disable Rx Parity */
+ u32 stop_bit_len = 0; /* Default stop bit length - 1 bit */
+ u32 bits_per_char;
+
+ /*
+ * Ignore Flow control.
+ * n = 8.
+ */
+ tx_trans_cfg = UART_CTS_MASK;
+ bits_per_char = BITS_PER_BYTE;
+
+ /*
+ * Make an unconditional cancel on the main sequencer to reset
+ * it else we could end up in data loss scenarios.
+ */
+ qcom_geni_serial_poll_tx_done(dev);
+ qcom_geni_serial_abort_rx(dev);
+
+ writel(UART_PACKING_CFG0, base_address + SE_GENI_TX_PACKING_CFG0);
+ writel(UART_PACKING_CFG1, base_address + SE_GENI_TX_PACKING_CFG1);
+ writel(UART_PACKING_CFG0, base_address + SE_GENI_RX_PACKING_CFG0);
+ writel(UART_PACKING_CFG1, base_address + SE_GENI_RX_PACKING_CFG1);
+
+ writel(tx_trans_cfg, base_address + SE_UART_TX_TRANS_CFG);
+ writel(tx_parity_cfg, base_address + SE_UART_TX_PARITY_CFG);
+ writel(rx_trans_cfg, base_address + SE_UART_RX_TRANS_CFG);
+ writel(rx_parity_cfg, base_address + SE_UART_RX_PARITY_CFG);
+ writel(bits_per_char, base_address + SE_UART_TX_WORD_LEN);
+ writel(bits_per_char, base_address + SE_UART_RX_WORD_LEN);
+ writel(stop_bit_len, base_address + SE_UART_TX_STOP_BIT_LEN);
+}
+
+static int msm_serial_probe(struct udevice *dev)
+{
+ struct msm_serial_data *priv = dev_get_priv(dev);
+
+ /* No need to reinitialize the UART after relocation */
+ if (gd->flags & GD_FLG_RELOC)
+ return 0;
+
+ geni_serial_init(dev);
+ msm_geni_serial_setup_rx(dev);
+ qcom_geni_serial_start_rx(dev);
+ qcom_geni_serial_start_tx(priv->base);
+
+ return 0;
+}
+
+static int msm_serial_ofdata_to_platdata(struct udevice *dev)
+{
+ struct msm_serial_data *priv = dev_get_priv(dev);
+
+ priv->base = dev_read_addr(dev);
+ if (priv->base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ return 0;
+}
+
+static const struct udevice_id msm_serial_ids[] = {
+ {.compatible = "qcom,msm-geni-uart"}, {}};
+
+U_BOOT_DRIVER(serial_msm_geni) = {
+ .name = "serial_msm_geni",
+ .id = UCLASS_SERIAL,
+ .of_match = msm_serial_ids,
+ .of_to_plat = msm_serial_ofdata_to_platdata,
+ .priv_auto = sizeof(struct msm_serial_data),
+ .probe = msm_serial_probe,
+ .ops = &msm_serial_ops,
+};
+
+#ifdef CONFIG_DEBUG_UART_MSM_GENI
+
+static struct msm_serial_data init_serial_data = {
+ .base = CONFIG_DEBUG_UART_BASE
+};
+
+/* Serial dumb device, to reuse driver code */
+static struct udevice init_dev = {
+ .priv_ = &init_serial_data,
+};
+
+#include <debug_uart.h>
+
+#define CLK_DIV (CONFIG_DEBUG_UART_CLOCK / \
+ (CONFIG_BAUDRATE * UART_OVERSAMPLING))
+#if (CONFIG_DEBUG_UART_CLOCK % (CONFIG_BAUDRATE * UART_OVERSAMPLING) > 0)
+#error Clocks cannot be set at early debug. Change CONFIG_BAUDRATE
+#endif
+
+static inline void _debug_uart_init(void)
+{
+ phys_addr_t base = CONFIG_DEBUG_UART_BASE;
+
+ geni_serial_init(&init_dev);
+ geni_serial_baud(base, CLK_DIV, CONFIG_BAUDRATE);
+ qcom_geni_serial_start_tx(base);
+}
+
+static inline void _debug_uart_putc(int ch)
+{
+ phys_addr_t base = CONFIG_DEBUG_UART_BASE;
+
+ writel(DEF_TX_WM, base + SE_GENI_TX_WATERMARK_REG);
+ qcom_geni_serial_setup_tx(base, 1);
+ qcom_geni_serial_poll_bit(&init_dev, SE_GENI_M_IRQ_STATUS,
+ M_TX_FIFO_WATERMARK_EN, true);
+
+ writel(ch, base + SE_GENI_TX_FIFOn);
+ writel(M_TX_FIFO_WATERMARK_EN, base + SE_GENI_M_IRQ_CLEAR);
+ qcom_geni_serial_poll_tx_done(&init_dev);
+}
+
+DEBUG_UART_FUNCS
+
+#endif
#include <asm/global_data.h>
#include <linux/compiler.h>
#include <asm/io.h>
+#if !CONFIG_IS_ENABLED(ARCH_APPLE)
#include <asm/arch/clk.h>
+#endif
#include <asm/arch/uart.h>
#include <serial.h>
#include <clk.h>
DECLARE_GLOBAL_DATA_PTR;
-#define RX_FIFO_COUNT_SHIFT 0
-#define RX_FIFO_COUNT_MASK (0xff << RX_FIFO_COUNT_SHIFT)
-#define RX_FIFO_FULL (1 << 8)
-#define TX_FIFO_COUNT_SHIFT 16
-#define TX_FIFO_COUNT_MASK (0xff << TX_FIFO_COUNT_SHIFT)
-#define TX_FIFO_FULL (1 << 24)
+enum {
+ PORT_S5P = 0,
+ PORT_S5L
+};
+
+#define S5L_RX_FIFO_COUNT_SHIFT 0
+#define S5L_RX_FIFO_COUNT_MASK (0xf << S5L_RX_FIFO_COUNT_SHIFT)
+#define S5L_RX_FIFO_FULL (1 << 8)
+#define S5L_TX_FIFO_COUNT_SHIFT 4
+#define S5L_TX_FIFO_COUNT_MASK (0xf << S5L_TX_FIFO_COUNT_SHIFT)
+#define S5L_TX_FIFO_FULL (1 << 9)
+
+#define S5P_RX_FIFO_COUNT_SHIFT 0
+#define S5P_RX_FIFO_COUNT_MASK (0xff << S5P_RX_FIFO_COUNT_SHIFT)
+#define S5P_RX_FIFO_FULL (1 << 8)
+#define S5P_TX_FIFO_COUNT_SHIFT 16
+#define S5P_TX_FIFO_COUNT_MASK (0xff << S5P_TX_FIFO_COUNT_SHIFT)
+#define S5P_TX_FIFO_FULL (1 << 24)
/* Information about a serial port */
struct s5p_serial_plat {
struct s5p_uart *reg; /* address of registers in physical memory */
+ u8 reg_width; /* register width */
u8 port_id; /* uart port number */
+ u8 rx_fifo_count_shift;
+ u8 tx_fifo_count_shift;
+ u32 rx_fifo_count_mask;
+ u32 tx_fifo_count_mask;
+ u32 rx_fifo_full;
+ u32 tx_fifo_full;
};
/*
writel(0x245, &uart->ucon);
}
-static void __maybe_unused s5p_serial_baud(struct s5p_uart *uart, uint uclk,
- int baudrate)
+static void __maybe_unused s5p_serial_baud(struct s5p_uart *uart, u8 reg_width,
+ uint uclk, int baudrate)
{
u32 val;
if (s5p_uart_divslot())
writew(udivslot[val % 16], &uart->rest.slot);
+ else if (reg_width == 4)
+ writel(val % 16, &uart->rest.value);
else
writeb(val % 16, &uart->rest.value);
}
struct s5p_uart *const uart = plat->reg;
u32 uclk;
-#ifdef CONFIG_CLK_EXYNOS
+#if CONFIG_IS_ENABLED(CLK_EXYNOS) || CONFIG_IS_ENABLED(ARCH_APPLE)
struct clk clk;
u32 ret;
uclk = get_uart_clk(plat->port_id);
#endif
- s5p_serial_baud(uart, uclk, baudrate);
+ s5p_serial_baud(uart, plat->reg_width, uclk, baudrate);
return 0;
}
struct s5p_serial_plat *plat = dev_get_plat(dev);
struct s5p_uart *const uart = plat->reg;
- if (!(readl(&uart->ufstat) & RX_FIFO_COUNT_MASK))
+ if (!(readl(&uart->ufstat) & plat->rx_fifo_count_mask))
return -EAGAIN;
serial_err_check(uart, 0);
- return (int)(readb(&uart->urxh) & 0xff);
+ if (plat->reg_width == 4)
+ return (int)(readl(&uart->urxh) & 0xff);
+ else
+ return (int)(readb(&uart->urxh) & 0xff);
}
static int s5p_serial_putc(struct udevice *dev, const char ch)
struct s5p_serial_plat *plat = dev_get_plat(dev);
struct s5p_uart *const uart = plat->reg;
- if (readl(&uart->ufstat) & TX_FIFO_FULL)
+ if (readl(&uart->ufstat) & plat->tx_fifo_full)
return -EAGAIN;
- writeb(ch, &uart->utxh);
+ if (plat->reg_width == 4)
+ writel(ch, &uart->utxh);
+ else
+ writeb(ch, &uart->utxh);
serial_err_check(uart, 1);
return 0;
struct s5p_uart *const uart = plat->reg;
uint32_t ufstat = readl(&uart->ufstat);
- if (input)
- return (ufstat & RX_FIFO_COUNT_MASK) >> RX_FIFO_COUNT_SHIFT;
- else
- return (ufstat & TX_FIFO_COUNT_MASK) >> TX_FIFO_COUNT_SHIFT;
+ if (input) {
+ return (ufstat & plat->rx_fifo_count_mask) >>
+ plat->rx_fifo_count_shift;
+ } else {
+ return (ufstat & plat->tx_fifo_count_mask) >>
+ plat->tx_fifo_count_shift;
+ }
}
static int s5p_serial_of_to_plat(struct udevice *dev)
{
struct s5p_serial_plat *plat = dev_get_plat(dev);
+ const ulong port_type = dev_get_driver_data(dev);
fdt_addr_t addr;
addr = dev_read_addr(dev);
return -EINVAL;
plat->reg = (struct s5p_uart *)addr;
+ plat->reg_width = dev_read_u32_default(dev, "reg-io-width", 1);
plat->port_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"id", dev_seq(dev));
+
+ if (port_type == PORT_S5L) {
+ plat->rx_fifo_count_shift = S5L_RX_FIFO_COUNT_SHIFT;
+ plat->rx_fifo_count_mask = S5L_RX_FIFO_COUNT_MASK;
+ plat->rx_fifo_full = S5L_RX_FIFO_FULL;
+ plat->tx_fifo_count_shift = S5L_TX_FIFO_COUNT_SHIFT;
+ plat->tx_fifo_count_mask = S5L_TX_FIFO_COUNT_MASK;
+ plat->tx_fifo_full = S5L_TX_FIFO_FULL;
+ } else {
+ plat->rx_fifo_count_shift = S5P_RX_FIFO_COUNT_SHIFT;
+ plat->rx_fifo_count_mask = S5P_RX_FIFO_COUNT_MASK;
+ plat->rx_fifo_full = S5P_RX_FIFO_FULL;
+ plat->tx_fifo_count_shift = S5P_TX_FIFO_COUNT_SHIFT;
+ plat->tx_fifo_count_mask = S5P_TX_FIFO_COUNT_MASK;
+ plat->tx_fifo_full = S5P_TX_FIFO_FULL;
+ }
+
return 0;
}
};
static const struct udevice_id s5p_serial_ids[] = {
- { .compatible = "samsung,exynos4210-uart" },
+ { .compatible = "samsung,exynos4210-uart", .data = PORT_S5P },
+ { .compatible = "apple,s5l-uart", .data = PORT_S5L },
{ }
};
static inline void _debug_uart_init(void)
{
+ if (IS_ENABLED(CONFIG_DEBUG_UART_SKIP_INIT))
+ return;
+
struct s5p_uart *uart = (struct s5p_uart *)CONFIG_DEBUG_UART_BASE;
s5p_serial_init(uart);
- s5p_serial_baud(uart, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
+#if CONFIG_IS_ENABLED(ARCH_APPLE)
+ s5p_serial_baud(uart, 4, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
+#else
+ s5p_serial_baud(uart, 1, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
+#endif
}
static inline void _debug_uart_putc(int ch)
{
struct s5p_uart *uart = (struct s5p_uart *)CONFIG_DEBUG_UART_BASE;
- while (readl(&uart->ufstat) & TX_FIFO_FULL);
-
+#if CONFIG_IS_ENABLED(ARCH_APPLE)
+ while (readl(&uart->ufstat) & S5L_TX_FIFO_FULL);
+ writel(ch, &uart->utxh);
+#else
+ while (readl(&uart->ufstat) & S5P_TX_FIFO_FULL);
writeb(ch, &uart->utxh);
+#endif
}
DEBUG_UART_FUNCS
if (fdtdec_get_bool(blob, node, "big-endian"))
plat->flags |= DSPI_FLAG_REGMAP_ENDIAN_BIG;
- plat->num_chipselect =
- fdtdec_get_int(blob, node, "num-cs", FSL_DSPI_MAX_CHIPSELECT);
+ plat->num_chipselect = fdtdec_get_int(blob, node,
+ "spi-num-chipselects",
+ FSL_DSPI_MAX_CHIPSELECT);
addr = dev_read_addr(bus);
if (addr == FDT_ADDR_T_NONE) {
static const struct udevice_id fsl_dspi_ids[] = {
{ .compatible = "fsl,vf610-dspi" },
+ { .compatible = "fsl,ls1021a-v1.0-dspi" },
{ }
};
#include <spi.h>
#include <spi-mem.h>
#include <asm/io.h>
+#ifdef CONFIG_FSL_LAYERSCAPE
+#include <asm/arch/clock.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/speed.h>
+#endif
#include <linux/bitops.h>
#include <linux/kernel.h>
#include <linux/sizes.h>
#define POLL_TOUT 5000
#define NXP_FSPI_MAX_CHIPSELECT 4
+/* Access flash memory using IP bus only */
+#define FSPI_QUIRK_USE_IP_ONLY BIT(0)
+
struct nxp_fspi_devtype_data {
unsigned int rxfifo;
unsigned int txfifo;
bool little_endian;
};
-static const struct nxp_fspi_devtype_data lx2160a_data = {
+static struct nxp_fspi_devtype_data lx2160a_data = {
.rxfifo = SZ_512, /* (64 * 64 bits) */
.txfifo = SZ_1K, /* (128 * 64 bits) */
.ahb_buf_size = SZ_2K, /* (256 * 64 bits) */
.little_endian = true, /* little-endian */
};
-static const struct nxp_fspi_devtype_data imx8mm_data = {
+static struct nxp_fspi_devtype_data imx8mm_data = {
.rxfifo = SZ_512, /* (64 * 64 bits) */
.txfifo = SZ_1K, /* (128 * 64 bits) */
.ahb_buf_size = SZ_2K, /* (256 * 64 bits) */
u32 memmap_phy;
u32 memmap_phy_size;
struct clk clk, clk_en;
- const struct nxp_fspi_devtype_data *devtype_data;
+ struct nxp_fspi_devtype_data *devtype_data;
};
+static inline int needs_ip_only(struct nxp_fspi *f)
+{
+ return f->devtype_data->quirks & FSPI_QUIRK_USE_IP_ONLY;
+}
+
/*
* R/W functions for big- or little-endian registers:
* The FSPI controller's endianness is independent of
for (i = 0; i < ARRAY_SIZE(lutval); i++)
fspi_writel(f, lutval[i], base + FSPI_LUT_REG(i));
- dev_dbg(f->dev, "CMD[%x] lutval[0:%x \t 1:%x \t 2:%x \t 3:%x]\n",
- op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3]);
+ dev_dbg(f->dev, "CMD[%x] lutval[0:%x \t 1:%x \t 2:%x \t 3:%x], size: 0x%08x\n",
+ op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3], op->data.nbytes);
/* lock LUT */
fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY);
nxp_fspi_prepare_lut(f, op);
/*
- * If we have large chunks of data, we read them through the AHB bus
- * by accessing the mapped memory. In all other cases we use
- * IP commands to access the flash.
+ * If we have large chunks of data, we read them through the AHB bus by
+ * accessing the mapped memory. In all other cases we use IP commands
+ * to access the flash. Read via AHB bus may be corrupted due to
+ * existence of an errata and therefore discard AHB read in such cases.
*/
if (op->data.nbytes > (f->devtype_data->rxfifo - 4) &&
- op->data.dir == SPI_MEM_DATA_IN) {
+ op->data.dir == SPI_MEM_DATA_IN &&
+ !needs_ip_only(f)) {
nxp_fspi_read_ahb(f, op);
} else {
if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8);
}
+ /* Limit data bytes to RX FIFO in case of IP read only */
+ if (needs_ip_only(f) &&
+ op->data.dir == SPI_MEM_DATA_IN &&
+ op->data.nbytes > f->devtype_data->rxfifo)
+ op->data.nbytes = f->devtype_data->rxfifo;
+
return 0;
}
+#ifdef CONFIG_FSL_LAYERSCAPE
+static void erratum_err050568(struct nxp_fspi *f)
+{
+ struct sys_info sysinfo;
+ u32 svr = 0, freq = 0;
+
+ /* Check for LS1028A variants */
+ svr = SVR_SOC_VER(get_svr());
+ if (svr != SVR_LS1017A ||
+ svr != SVR_LS1018A ||
+ svr != SVR_LS1027A ||
+ svr != SVR_LS1028A) {
+ dev_dbg(f->dev, "Errata applicable only for LS1028A variants\n");
+ return;
+ }
+
+ /* Read PLL frequency */
+ get_sys_info(&sysinfo);
+ freq = sysinfo.freq_systembus / 1000000; /* Convert to MHz */
+ dev_dbg(f->dev, "svr: %08x, Frequency: %dMhz\n", svr, freq);
+
+ /* Use IP bus only if PLL is 300MHz */
+ if (freq == 300)
+ f->devtype_data->quirks |= FSPI_QUIRK_USE_IP_ONLY;
+}
+#endif
+
static int nxp_fspi_default_setup(struct nxp_fspi *f)
{
void __iomem *base = f->iobase;
return ret;
#endif
+#ifdef CONFIG_FSL_LAYERSCAPE
+ /*
+ * ERR050568: Flash access by FlexSPI AHB command may not work with
+ * platform frequency equal to 300 MHz on LS1028A.
+ * LS1028A reuses LX2160A compatible entry. Make errata applicable for
+ * Layerscape LS1028A platform family.
+ */
+ if (device_is_compatible(f->dev, "nxp,lx2160a-fspi"))
+ erratum_err050568(f);
+#endif
+
/* Reset the module */
/* w1c register, wait unit clear */
ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0,
DECLARE_GLOBAL_DATA_PTR;
/* PMIC Arbiter configuration registers */
-#define PMIC_ARB_VERSION 0x0000
-#define PMIC_ARB_VERSION_V2_MIN 0x20010000
-
-#define ARB_CHANNEL_OFFSET(n) (0x4 * (n))
-#define SPMI_CH_OFFSET(chnl) ((chnl) * 0x8000)
-
-#define SPMI_REG_CMD0 0x0
-#define SPMI_REG_CONFIG 0x4
-#define SPMI_REG_STATUS 0x8
-#define SPMI_REG_WDATA 0x10
-#define SPMI_REG_RDATA 0x18
-
-#define SPMI_CMD_OPCODE_SHIFT 27
-#define SPMI_CMD_SLAVE_ID_SHIFT 20
-#define SPMI_CMD_ADDR_SHIFT 12
-#define SPMI_CMD_ADDR_OFFSET_SHIFT 4
-#define SPMI_CMD_BYTE_CNT_SHIFT 0
-
-#define SPMI_CMD_EXT_REG_WRITE_LONG 0x00
-#define SPMI_CMD_EXT_REG_READ_LONG 0x01
-
-#define SPMI_STATUS_DONE 0x1
+#define PMIC_ARB_VERSION 0x0000
+#define PMIC_ARB_VERSION_V2_MIN 0x20010000
+#define PMIC_ARB_VERSION_V3_MIN 0x30000000
+#define PMIC_ARB_VERSION_V5_MIN 0x50000000
+
+#define APID_MAP_OFFSET_V1_V2_V3 (0x800)
+#define APID_MAP_OFFSET_V5 (0x900)
+#define ARB_CHANNEL_OFFSET(n) (0x4 * (n))
+#define SPMI_CH_OFFSET(chnl) ((chnl) * 0x8000)
+#define SPMI_V5_OBS_CH_OFFSET(chnl) ((chnl) * 0x80)
+#define SPMI_V5_RW_CH_OFFSET(chnl) ((chnl) * 0x10000)
+
+#define SPMI_REG_CMD0 0x0
+#define SPMI_REG_CONFIG 0x4
+#define SPMI_REG_STATUS 0x8
+#define SPMI_REG_WDATA 0x10
+#define SPMI_REG_RDATA 0x18
+
+#define SPMI_CMD_OPCODE_SHIFT 27
+#define SPMI_CMD_SLAVE_ID_SHIFT 20
+#define SPMI_CMD_ADDR_SHIFT 12
+#define SPMI_CMD_ADDR_OFFSET_SHIFT 4
+#define SPMI_CMD_BYTE_CNT_SHIFT 0
+
+#define SPMI_CMD_EXT_REG_WRITE_LONG 0x00
+#define SPMI_CMD_EXT_REG_READ_LONG 0x01
+
+#define SPMI_STATUS_DONE 0x1
+
+#define SPMI_MAX_CHANNELS 128
+#define SPMI_MAX_SLAVES 16
+#define SPMI_MAX_PERIPH 256
+
+enum arb_ver {
+ V1 = 1,
+ V2,
+ V3,
+ V5 = 5
+};
-#define SPMI_MAX_CHANNELS 128
-#define SPMI_MAX_SLAVES 16
-#define SPMI_MAX_PERIPH 256
+/*
+ * PMIC arbiter version 5 uses different register offsets for read/write vs
+ * observer channels.
+ */
+enum pmic_arb_channel {
+ PMIC_ARB_CHANNEL_RW,
+ PMIC_ARB_CHANNEL_OBS,
+};
struct msm_spmi_priv {
- phys_addr_t arb_chnl; /* ARB channel mapping base */
+ phys_addr_t arb_chnl; /* ARB channel mapping base */
phys_addr_t spmi_core; /* SPMI core */
- phys_addr_t spmi_obs; /* SPMI observer */
+ phys_addr_t spmi_obs; /* SPMI observer */
/* SPMI channel map */
uint8_t channel_map[SPMI_MAX_SLAVES][SPMI_MAX_PERIPH];
+ /* SPMI bus arbiter version */
+ u32 arb_ver;
};
static int msm_spmi_write(struct udevice *dev, int usid, int pid, int off,
{
struct msm_spmi_priv *priv = dev_get_priv(dev);
unsigned channel;
+ unsigned int ch_offset;
uint32_t reg = 0;
if (usid >= SPMI_MAX_SLAVES)
channel = priv->channel_map[usid][pid];
/* Disable IRQ mode for the current channel*/
- writel(0x0, priv->spmi_core + SPMI_CH_OFFSET(channel) +
- SPMI_REG_CONFIG);
+ writel(0x0,
+ priv->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_CONFIG);
/* Write single byte */
writel(val, priv->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_WDATA);
reg |= (off << SPMI_CMD_ADDR_OFFSET_SHIFT);
reg |= 1; /* byte count */
+ if (priv->arb_ver == V5)
+ ch_offset = SPMI_V5_RW_CH_OFFSET(channel);
+ else
+ ch_offset = SPMI_CH_OFFSET(channel);
+
/* Send write command */
writel(reg, priv->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_CMD0);
{
struct msm_spmi_priv *priv = dev_get_priv(dev);
unsigned channel;
+ unsigned int ch_offset;
uint32_t reg = 0;
if (usid >= SPMI_MAX_SLAVES)
channel = priv->channel_map[usid][pid];
+ if (priv->arb_ver == V5)
+ ch_offset = SPMI_V5_OBS_CH_OFFSET(channel);
+ else
+ ch_offset = SPMI_CH_OFFSET(channel);
+
/* Disable IRQ mode for the current channel*/
- writel(0x0, priv->spmi_obs + SPMI_CH_OFFSET(channel) + SPMI_REG_CONFIG);
+ writel(0x0, priv->spmi_obs + ch_offset + SPMI_REG_CONFIG);
/* Prepare read command */
reg |= SPMI_CMD_EXT_REG_READ_LONG << SPMI_CMD_OPCODE_SHIFT;
reg |= 1; /* byte count */
/* Request read */
- writel(reg, priv->spmi_obs + SPMI_CH_OFFSET(channel) + SPMI_REG_CMD0);
+ writel(reg, priv->spmi_obs + ch_offset + SPMI_REG_CMD0);
/* Wait till CMD DONE status */
reg = 0;
while (!reg) {
- reg = readl(priv->spmi_obs + SPMI_CH_OFFSET(channel) +
- SPMI_REG_STATUS);
+ reg = readl(priv->spmi_obs + ch_offset + SPMI_REG_STATUS);
}
if (reg ^ SPMI_STATUS_DONE) {
}
/* Read the data */
- return readl(priv->spmi_obs + SPMI_CH_OFFSET(channel) +
- SPMI_REG_RDATA) & 0xFF;
+ return readl(priv->spmi_obs + ch_offset +
+ SPMI_REG_RDATA) & 0xFF;
}
static struct dm_spmi_ops msm_spmi_ops = {
static int msm_spmi_probe(struct udevice *dev)
{
- struct udevice *parent = dev->parent;
struct msm_spmi_priv *priv = dev_get_priv(dev);
- int node = dev_of_offset(dev);
+ phys_addr_t config_addr;
u32 hw_ver;
- bool is_v1;
+ u32 version;
int i;
+ int err;
+
+ config_addr = dev_read_addr_index(dev, 0);
+ priv->spmi_core = dev_read_addr_index(dev, 1);
+ priv->spmi_obs = dev_read_addr_index(dev, 2);
+
+ hw_ver = readl(config_addr + PMIC_ARB_VERSION);
+
+ if (hw_ver < PMIC_ARB_VERSION_V3_MIN) {
+ priv->arb_ver = V2;
+ version = 2;
+ priv->arb_chnl = config_addr + APID_MAP_OFFSET_V1_V2_V3;
+ } else if (hw_ver < PMIC_ARB_VERSION_V5_MIN) {
+ priv->arb_ver = V3;
+ version = 3;
+ priv->arb_chnl = config_addr + APID_MAP_OFFSET_V1_V2_V3;
+ } else {
+ priv->arb_ver = V5;
+ version = 5;
+ priv->arb_chnl = config_addr + APID_MAP_OFFSET_V5;
+
+ if (err) {
+ dev_err(dev, "could not read APID->PPID mapping table, rc= %d\n", err);
+ return -1;
+ }
+ }
- priv->arb_chnl = dev_read_addr(dev);
- priv->spmi_core = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
- dev_of_offset(parent), node, "reg", 1, NULL, false);
- priv->spmi_obs = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
- dev_of_offset(parent), node, "reg", 2, NULL, false);
-
- hw_ver = readl(priv->arb_chnl + PMIC_ARB_VERSION - 0x800);
- is_v1 = (hw_ver < PMIC_ARB_VERSION_V2_MIN);
-
- dev_dbg(dev, "PMIC Arb Version-%d (0x%x)\n", (is_v1 ? 1 : 2), hw_ver);
+ dev_dbg(dev, "PMIC Arb Version-%d (0x%x)\n", version, hw_ver);
if (priv->arb_chnl == FDT_ADDR_T_NONE ||
priv->spmi_core == FDT_ADDR_T_NONE ||
priv->spmi_obs == FDT_ADDR_T_NONE)
return -EINVAL;
+ dev_dbg(dev, "priv->arb_chnl address (%llu)\n", priv->arb_chnl);
+ dev_dbg(dev, "priv->spmi_core address (%llu)\n", priv->spmi_core);
+ dev_dbg(dev, "priv->spmi_obs address (%llu)\n", priv->spmi_obs);
/* Scan peripherals connected to each SPMI channel */
- for (i = 0; i < SPMI_MAX_PERIPH ; i++) {
+ for (i = 0; i < SPMI_MAX_PERIPH; i++) {
uint32_t periph = readl(priv->arb_chnl + ARB_CHANNEL_OFFSET(i));
uint8_t slave_id = (periph & 0xf0000) >> 16;
uint8_t pid = (periph & 0xff00) >> 8;
.of_match = msm_spmi_ids,
.ops = &msm_spmi_ops,
.probe = msm_spmi_probe,
- .priv_auto = sizeof(struct msm_spmi_priv),
+ .priv_auto = sizeof(struct msm_spmi_priv),
};
This enables the system reset driver support over TI System Control
Interface available on some new TI's SoCs.
-endif
-
config SYSRESET_SYSCON
bool "Enable support for mfd syscon reboot driver"
select REGMAP
help
Reboot support for generic watchdog reset.
+config SYSRESET_WATCHDOG_AUTO
+ bool "Automatically register first watchdog with sysreset"
+ depends on SYSRESET_WATCHDOG
+ help
+ If enabled, the first watchdog (as selected by the watchdog uclass)
+ will automatically be registered with the watchdog reboot driver.
+
config SYSRESET_RESETCTL
bool "Enable support for reset controller reboot driver"
select DM_RESET
help
Reboot support for NXP MPC83xx SoCs.
+endif
+
endmenu
.request = gpio_reboot_request,
};
-int gpio_reboot_probe(struct udevice *dev)
+static int gpio_reboot_probe(struct udevice *dev)
{
struct gpio_reboot_priv *priv = dev_get_priv(dev);
.request = resetctl_reboot_request,
};
-int resetctl_reboot_probe(struct udevice *dev)
+static int resetctl_reboot_probe(struct udevice *dev)
{
struct resetctl_reboot_priv *priv = dev_get_priv(dev);
.request = syscon_reboot_request,
};
-int syscon_reboot_probe(struct udevice *dev)
+static int syscon_reboot_probe(struct udevice *dev)
{
struct syscon_reboot_priv *priv = dev_get_priv(dev);
int err;
#include <common.h>
#include <dm.h>
+#include <dm/device-internal.h>
#include <errno.h>
+#include <malloc.h>
#include <sysreset.h>
#include <wdt.h>
-struct wdt_reboot_priv {
+struct wdt_reboot_plat {
struct udevice *wdt;
};
static int wdt_reboot_request(struct udevice *dev, enum sysreset_t type)
{
- struct wdt_reboot_priv *priv = dev_get_priv(dev);
+ struct wdt_reboot_plat *plat = dev_get_plat(dev);
int ret;
- ret = wdt_expire_now(priv->wdt, 0);
+ ret = wdt_expire_now(plat->wdt, 0);
if (ret)
return ret;
.request = wdt_reboot_request,
};
-int wdt_reboot_probe(struct udevice *dev)
+static int wdt_reboot_of_to_plat(struct udevice *dev)
{
- struct wdt_reboot_priv *priv = dev_get_priv(dev);
+ struct wdt_reboot_plat *plat = dev_get_plat(dev);
int err;
err = uclass_get_device_by_phandle(UCLASS_WDT, dev,
- "wdt", &priv->wdt);
+ "wdt", &plat->wdt);
if (err) {
pr_err("unable to find wdt device\n");
return err;
.name = "wdt_reboot",
.id = UCLASS_SYSRESET,
.of_match = wdt_reboot_ids,
+ .of_to_plat = wdt_reboot_of_to_plat,
+ .plat_auto = sizeof(struct wdt_reboot_plat),
.ops = &wdt_reboot_ops,
- .priv_auto = sizeof(struct wdt_reboot_priv),
- .probe = wdt_reboot_probe,
};
+
+#if IS_ENABLED(CONFIG_SYSRESET_WATCHDOG_AUTO)
+int sysreset_register_wdt(struct udevice *dev)
+{
+ struct wdt_reboot_plat *plat = malloc(sizeof(*plat));
+ int ret;
+
+ if (!plat)
+ return -ENOMEM;
+
+ plat->wdt = dev;
+
+ ret = device_bind(dev, DM_DRIVER_GET(wdt_reboot),
+ dev->name, plat, ofnode_null(), NULL);
+ if (ret) {
+ free(plat);
+ return ret;
+ }
+
+ return 0;
+}
+#endif
help
This driver supports firmware TPM running in TEE.
+config TPM2_MMIO
+ bool "MMIO based TPM2 Interface"
+ depends on TPM_V2
+ help
+ This driver supports firmware TPM2.0 MMIO interface.
+ The usual TPM operations and the 'tpm' command can be used to talk
+ to the device using the standard TPM Interface Specification (TIS)
+ protocol.
+
endif # TPM_V2
endmenu
obj-$(CONFIG_$(SPL_TPL_)TPM2_CR50_I2C) += cr50_i2c.o
obj-$(CONFIG_TPM2_TIS_SANDBOX) += tpm2_tis_sandbox.o sandbox_common.o
-obj-$(CONFIG_TPM2_TIS_SPI) += tpm2_tis_spi.o
+obj-$(CONFIG_TPM2_TIS_SPI) += tpm2_tis_core.o tpm2_tis_spi.o
obj-$(CONFIG_TPM2_FTPM_TEE) += tpm2_ftpm_tee.o
+obj-$(CONFIG_TPM2_MMIO) += tpm2_tis_core.o tpm2_tis_mmio.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020, Linaro Limited
+ *
+ * Based on the Linux TIS core interface and U-Boot original SPI TPM driver
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <tpm-v2.h>
+#include <linux/delay.h>
+#include <linux/unaligned/be_byteshift.h>
+#include "tpm_tis.h"
+
+int tpm_tis_get_desc(struct udevice *dev, char *buf, int size)
+{
+ struct tpm_chip *chip = dev_get_priv(dev);
+
+ if (size < 80)
+ return -ENOSPC;
+
+ return snprintf(buf, size,
+ "%s v2.0: VendorID 0x%04x, DeviceID 0x%04x, RevisionID 0x%02x [%s]",
+ dev->name, chip->vend_dev & 0xFFFF,
+ chip->vend_dev >> 16, chip->rid,
+ (chip->is_open ? "open" : "closed"));
+}
+
+/**
+ * tpm_tis_check_locality - Check the current TPM locality
+ *
+ * @dev: TPM device
+ * @loc: locality
+ *
+ * Return: True if the tested locality matches
+ */
+static bool tpm_tis_check_locality(struct udevice *dev, int loc)
+{
+ struct tpm_chip *chip = dev_get_priv(dev);
+ struct tpm_tis_phy_ops *phy_ops = chip->phy_ops;
+ u8 locality;
+
+ phy_ops->read_bytes(dev, TPM_ACCESS(loc), 1, &locality);
+ if ((locality & (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID |
+ TPM_ACCESS_REQUEST_USE)) ==
+ (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) {
+ chip->locality = loc;
+ return true;
+ }
+
+ return false;
+}
+
+/**
+ * tpm_tis_request_locality - Request a locality from the TPM
+ *
+ * @dev: TPM device
+ * @loc: requested locality
+ *
+ * Return: 0 on success -1 on failure
+ */
+int tpm_tis_request_locality(struct udevice *dev, int loc)
+{
+ struct tpm_chip *chip = dev_get_priv(dev);
+ struct tpm_tis_phy_ops *phy_ops = chip->phy_ops;
+ u8 buf = TPM_ACCESS_REQUEST_USE;
+ unsigned long start, stop;
+
+ if (tpm_tis_check_locality(dev, loc))
+ return 0;
+
+ phy_ops->write_bytes(dev, TPM_ACCESS(loc), 1, &buf);
+ start = get_timer(0);
+ stop = chip->timeout_a;
+ do {
+ if (tpm_tis_check_locality(dev, loc))
+ return 0;
+ mdelay(TPM_TIMEOUT_MS);
+ } while (get_timer(start) < stop);
+
+ return -1;
+}
+
+/**
+ * tpm_tis_status - Check the current device status
+ *
+ * @dev: TPM device
+ * @status: return value of status
+ *
+ * Return: 0 on success, negative on failure
+ */
+static int tpm_tis_status(struct udevice *dev, u8 *status)
+{
+ struct tpm_chip *chip = dev_get_priv(dev);
+ struct tpm_tis_phy_ops *phy_ops = chip->phy_ops;
+
+ if (chip->locality < 0)
+ return -EINVAL;
+
+ phy_ops->read_bytes(dev, TPM_STS(chip->locality), 1, status);
+
+ if ((*status & TPM_STS_READ_ZERO)) {
+ log_err("TPM returned invalid status\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+/**
+ * tpm_tis_release_locality - Release the requested locality
+ *
+ * @dev: TPM device
+ * @loc: requested locality
+ *
+ * Return: 0 on success, negative on failure
+ */
+int tpm_tis_release_locality(struct udevice *dev, int loc)
+{
+ struct tpm_chip *chip = dev_get_priv(dev);
+ struct tpm_tis_phy_ops *phy_ops = chip->phy_ops;
+ u8 buf = TPM_ACCESS_ACTIVE_LOCALITY;
+ int ret;
+
+ if (chip->locality < 0)
+ return 0;
+
+ ret = phy_ops->write_bytes(dev, TPM_ACCESS(loc), 1, &buf);
+ chip->locality = -1;
+
+ return ret;
+}
+
+/**
+ * tpm_tis_wait_for_stat - Wait for TPM to become ready
+ *
+ * @dev: TPM device
+ * @mask: mask to match
+ * @timeout: timeout for retries
+ * @status: current status
+ *
+ * Return: 0 on success, negative on failure
+ */
+static int tpm_tis_wait_for_stat(struct udevice *dev, u8 mask,
+ unsigned long timeout, u8 *status)
+{
+ unsigned long start = get_timer(0);
+ unsigned long stop = timeout;
+ int ret;
+
+ do {
+ mdelay(TPM_TIMEOUT_MS);
+ ret = tpm_tis_status(dev, status);
+ if (ret)
+ return ret;
+
+ if ((*status & mask) == mask)
+ return 0;
+ } while (get_timer(start) < stop);
+
+ return -ETIMEDOUT;
+}
+
+/**
+ * tpm_tis_get_burstcount - Get the burstcount for the data FIFO
+ *
+ * @dev: TPM device
+ * @burstcount: current burstcount
+ *
+ * Return: 0 on success, negative on failure
+ */
+static int tpm_tis_get_burstcount(struct udevice *dev, size_t *burstcount)
+{
+ struct tpm_chip *chip = dev_get_priv(dev);
+ struct tpm_tis_phy_ops *phy_ops = chip->phy_ops;
+ unsigned long start, stop;
+ u32 burst;
+
+ if (chip->locality < 0)
+ return -EINVAL;
+
+ /* wait for burstcount */
+ start = get_timer(0);
+ /*
+ * This is the TPMv2 defined timeout. Change this in case you want to
+ * make the driver compatile to TPMv1
+ */
+ stop = chip->timeout_a;
+ do {
+ phy_ops->read32(dev, TPM_STS(chip->locality), &burst);
+ *burstcount = (burst >> 8) & 0xFFFF;
+ if (*burstcount)
+ return 0;
+
+ mdelay(TPM_TIMEOUT_MS);
+ } while (get_timer(start) < stop);
+
+ return -ETIMEDOUT;
+}
+
+/**
+ * tpm_tis_ready - Cancel pending comands and get the device on a ready state
+ *
+ * @dev: TPM device
+ *
+ * Return: 0 on success, negative on failure
+ */
+static int tpm_tis_ready(struct udevice *dev)
+{
+ struct tpm_chip *chip = dev_get_priv(dev);
+ struct tpm_tis_phy_ops *phy_ops = chip->phy_ops;
+ u8 data = TPM_STS_COMMAND_READY;
+
+ /* This will cancel any pending commands */
+ return phy_ops->write_bytes(dev, TPM_STS(chip->locality), 1, &data);
+}
+
+int tpm_tis_send(struct udevice *dev, const u8 *buf, size_t len)
+{
+ struct tpm_chip *chip = dev_get_priv(dev);
+ struct tpm_tis_phy_ops *phy_ops = chip->phy_ops;
+ size_t burstcnt, wr_size, sent = 0;
+ u8 data = TPM_STS_GO;
+ u8 status;
+ int ret;
+
+ if (!chip)
+ return -ENODEV;
+
+ ret = tpm_tis_request_locality(dev, 0);
+ if (ret < 0)
+ return -EBUSY;
+
+ ret = tpm_tis_status(dev, &status);
+ if (ret)
+ goto release_locality;
+
+ if (!(status & TPM_STS_COMMAND_READY)) {
+ ret = tpm_tis_ready(dev);
+ if (ret) {
+ log_err("Can't cancel previous TPM operation\n");
+ goto release_locality;
+ }
+ ret = tpm_tis_wait_for_stat(dev, TPM_STS_COMMAND_READY,
+ chip->timeout_b, &status);
+ if (ret) {
+ log_err("TPM not ready\n");
+ goto release_locality;
+ }
+ }
+
+ while (len > 0) {
+ ret = tpm_tis_get_burstcount(dev, &burstcnt);
+ if (ret)
+ goto release_locality;
+
+ wr_size = min(len, burstcnt);
+ ret = phy_ops->write_bytes(dev, TPM_DATA_FIFO(chip->locality),
+ wr_size, buf + sent);
+ if (ret < 0)
+ goto release_locality;
+
+ ret = tpm_tis_wait_for_stat(dev, TPM_STS_VALID,
+ chip->timeout_c, &status);
+ if (ret)
+ goto release_locality;
+
+ sent += wr_size;
+ len -= wr_size;
+ /* make sure the TPM expects more data */
+ if (len && !(status & TPM_STS_DATA_EXPECT)) {
+ ret = -EIO;
+ goto release_locality;
+ }
+ }
+
+ /*
+ * Make a final check ensuring everything is ok and the TPM expects no
+ * more data
+ */
+ ret = tpm_tis_wait_for_stat(dev, TPM_STS_VALID, chip->timeout_c,
+ &status);
+ if (ret)
+ goto release_locality;
+
+ if (status & TPM_STS_DATA_EXPECT) {
+ ret = -EIO;
+ goto release_locality;
+ }
+
+ ret = phy_ops->write_bytes(dev, TPM_STS(chip->locality), 1, &data);
+ if (ret)
+ goto release_locality;
+
+ return sent;
+
+release_locality:
+ tpm_tis_ready(dev);
+ tpm_tis_release_locality(dev, chip->locality);
+
+ return ret;
+}
+
+static int tpm_tis_recv_data(struct udevice *dev, u8 *buf, size_t count)
+{
+ struct tpm_chip *chip = dev_get_priv(dev);
+ struct tpm_tis_phy_ops *phy_ops = chip->phy_ops;
+ int size = 0, len, ret;
+ size_t burstcnt;
+ u8 status;
+
+ while (size < count &&
+ tpm_tis_wait_for_stat(dev, TPM_STS_DATA_AVAIL | TPM_STS_VALID,
+ chip->timeout_c, &status) == 0) {
+ ret = tpm_tis_get_burstcount(dev, &burstcnt);
+ if (ret)
+ return ret;
+
+ len = min_t(int, burstcnt, count - size);
+ ret = phy_ops->read_bytes(dev, TPM_DATA_FIFO(chip->locality),
+ len, buf + size);
+ if (ret < 0)
+ return ret;
+
+ size += len;
+ }
+
+ return size;
+}
+
+/**
+ * tpm_tis_recv - Receive data from a device
+ *
+ * @dev: TPM device
+ * @buf: buffer to copy data
+ * @size: buffer size
+ *
+ * Return: bytes read or negative on failure
+ */
+int tpm_tis_recv(struct udevice *dev, u8 *buf, size_t count)
+{
+ struct tpm_chip *chip = dev_get_priv(dev);
+ int size, expected;
+
+ if (count < TPM_HEADER_SIZE)
+ return -E2BIG;
+
+ size = tpm_tis_recv_data(dev, buf, TPM_HEADER_SIZE);
+ if (size < TPM_HEADER_SIZE) {
+ log_err("TPM error, unable to read header\n");
+ goto out;
+ }
+
+ expected = get_unaligned_be32(buf + TPM_CMD_COUNT_OFFSET);
+ if (expected > count) {
+ size = -EIO;
+ log_warning("Too much data: %d > %zu\n", expected, count);
+ goto out;
+ }
+
+ size += tpm_tis_recv_data(dev, &buf[TPM_HEADER_SIZE],
+ expected - TPM_HEADER_SIZE);
+ if (size < expected) {
+ log(LOGC_NONE, LOGL_ERR,
+ "TPM error, unable to read remaining bytes of result\n");
+ size = -EIO;
+ goto out;
+ }
+
+out:
+ tpm_tis_ready(dev);
+ /* acquired in tpm_tis_send */
+ tpm_tis_release_locality(dev, chip->locality);
+
+ return size;
+}
+
+int tpm_tis_cleanup(struct udevice *dev)
+{
+ struct tpm_chip *chip = dev_get_priv(dev);
+
+ tpm_tis_ready(dev);
+ tpm_tis_release_locality(dev, chip->locality);
+
+ return 0;
+}
+
+int tpm_tis_open(struct udevice *dev)
+{
+ struct tpm_chip *chip = dev_get_priv(dev);
+ int ret;
+
+ if (chip->is_open)
+ return -EBUSY;
+
+ ret = tpm_tis_request_locality(dev, 0);
+ if (!ret)
+ chip->is_open = 1;
+
+ return ret;
+}
+
+void tpm_tis_ops_register(struct udevice *dev, struct tpm_tis_phy_ops *ops)
+{
+ struct tpm_chip *chip = dev_get_priv(dev);
+
+ chip->phy_ops = ops;
+}
+
+static bool tis_check_ops(struct tpm_tis_phy_ops *phy_ops)
+{
+ if (!phy_ops || !phy_ops->read_bytes || !phy_ops->write_bytes ||
+ !phy_ops->read32 || !phy_ops->write32)
+ return false;
+
+ return true;
+}
+
+int tpm_tis_init(struct udevice *dev)
+{
+ struct tpm_chip *chip = dev_get_priv(dev);
+ struct tpm_tis_phy_ops *phy_ops = chip->phy_ops;
+ int ret;
+ u32 tmp;
+
+ if (!tis_check_ops(phy_ops)) {
+ log_err("Driver bug. No bus ops defined\n");
+ return -1;
+ }
+ ret = tpm_tis_request_locality(dev, 0);
+ if (ret)
+ return ret;
+
+ chip->timeout_a = TIS_SHORT_TIMEOUT_MS;
+ chip->timeout_b = TIS_LONG_TIMEOUT_MS;
+ chip->timeout_c = TIS_SHORT_TIMEOUT_MS;
+ chip->timeout_d = TIS_SHORT_TIMEOUT_MS;
+
+ /* Disable interrupts */
+ phy_ops->read32(dev, TPM_INT_ENABLE(chip->locality), &tmp);
+ tmp |= TPM_INTF_CMD_READY_INT | TPM_INTF_LOCALITY_CHANGE_INT |
+ TPM_INTF_DATA_AVAIL_INT | TPM_INTF_STS_VALID_INT;
+ tmp &= ~TPM_GLOBAL_INT_ENABLE;
+ phy_ops->write32(dev, TPM_INT_ENABLE(chip->locality), tmp);
+
+ phy_ops->read_bytes(dev, TPM_RID(chip->locality), 1, &chip->rid);
+ phy_ops->read32(dev, TPM_DID_VID(chip->locality), &chip->vend_dev);
+
+ return tpm_tis_release_locality(dev, chip->locality);
+}
+
+int tpm_tis_close(struct udevice *dev)
+{
+ struct tpm_chip *chip = dev_get_priv(dev);
+ int ret = 0;
+
+ if (chip->is_open) {
+ ret = tpm_tis_release_locality(dev, chip->locality);
+ chip->is_open = 0;
+ }
+
+ return ret;
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * driver for mmio TCG/TIS TPM (trusted platform module).
+ *
+ * Specifications at www.trustedcomputinggroup.org
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <tpm-v2.h>
+#include <linux/bitops.h>
+#include <linux/compiler.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/types.h>
+#include <linux/io.h>
+#include <linux/unaligned/be_byteshift.h>
+#include "tpm_tis.h"
+#include "tpm_internal.h"
+
+/**
+ * struct tpm_tis_chip_data - Information about an MMIO TPM
+ * @pcr_count: Number of PCR per bank
+ * @pcr_select_min: Minimum size in bytes of the pcrSelect array
+ * @iobase: Base address
+ */
+struct tpm_tis_chip_data {
+ unsigned int pcr_count;
+ unsigned int pcr_select_min;
+ void __iomem *iobase;
+};
+
+static int mmio_read_bytes(struct udevice *dev, u32 addr, u16 len,
+ u8 *result)
+{
+ struct tpm_tis_chip_data *drv_data = (void *)dev_get_driver_data(dev);
+
+ while (len--)
+ *result++ = ioread8(drv_data->iobase + addr);
+
+ return 0;
+}
+
+static int mmio_write_bytes(struct udevice *dev, u32 addr, u16 len,
+ const u8 *value)
+{
+ struct tpm_tis_chip_data *drv_data = (void *)dev_get_driver_data(dev);
+
+ while (len--)
+ iowrite8(*value++, drv_data->iobase + addr);
+
+ return 0;
+}
+
+static int mmio_read32(struct udevice *dev, u32 addr, u32 *result)
+{
+ struct tpm_tis_chip_data *drv_data = (void *)dev_get_driver_data(dev);
+
+ *result = ioread32(drv_data->iobase + addr);
+
+ return 0;
+}
+
+static int mmio_write32(struct udevice *dev, u32 addr, u32 value)
+{
+ struct tpm_tis_chip_data *drv_data = (void *)dev_get_driver_data(dev);
+
+ iowrite32(value, drv_data->iobase + addr);
+
+ return 0;
+}
+
+static struct tpm_tis_phy_ops phy_ops = {
+ .read_bytes = mmio_read_bytes,
+ .write_bytes = mmio_write_bytes,
+ .read32 = mmio_read32,
+ .write32 = mmio_write32,
+};
+
+static int tpm_tis_probe(struct udevice *dev)
+{
+ struct tpm_tis_chip_data *drv_data = (void *)dev_get_driver_data(dev);
+ struct tpm_chip_priv *priv = dev_get_uclass_priv(dev);
+ int ret = 0;
+ fdt_addr_t ioaddr;
+ u64 sz;
+
+ ioaddr = dev_read_addr(dev);
+ if (ioaddr == FDT_ADDR_T_NONE)
+ return log_msg_ret("ioaddr", -EINVAL);
+
+ ret = dev_read_u64(dev, "reg", &sz);
+ if (ret)
+ return -EINVAL;
+
+ drv_data->iobase = ioremap(ioaddr, sz);
+ tpm_tis_ops_register(dev, &phy_ops);
+ ret = tpm_tis_init(dev);
+ if (ret)
+ goto iounmap;
+
+ priv->pcr_count = drv_data->pcr_count;
+ priv->pcr_select_min = drv_data->pcr_select_min;
+ /*
+ * Although the driver probably works with a TPMv1 our Kconfig
+ * limits the driver to TPMv2 only
+ */
+ priv->version = TPM_V2;
+
+ return ret;
+iounmap:
+ iounmap(drv_data->iobase);
+
+ return -EINVAL;
+}
+
+static int tpm_tis_remove(struct udevice *dev)
+{
+ struct tpm_tis_chip_data *drv_data = (void *)dev_get_driver_data(dev);
+
+ iounmap(drv_data->iobase);
+
+ return tpm_tis_cleanup(dev);
+}
+
+static const struct tpm_ops tpm_tis_ops = {
+ .open = tpm_tis_open,
+ .close = tpm_tis_close,
+ .get_desc = tpm_tis_get_desc,
+ .send = tpm_tis_send,
+ .recv = tpm_tis_recv,
+ .cleanup = tpm_tis_cleanup,
+};
+
+static const struct tpm_tis_chip_data tpm_tis_std_chip_data = {
+ .pcr_count = 24,
+ .pcr_select_min = 3,
+};
+
+static const struct udevice_id tpm_tis_ids[] = {
+ {
+ .compatible = "tcg,tpm-tis-mmio",
+ .data = (ulong)&tpm_tis_std_chip_data,
+ },
+ { }
+};
+
+U_BOOT_DRIVER(tpm_tis_mmio) = {
+ .name = "tpm_tis_mmio",
+ .id = UCLASS_TPM,
+ .of_match = tpm_tis_ids,
+ .ops = &tpm_tis_ops,
+ .probe = tpm_tis_probe,
+ .remove = tpm_tis_remove,
+ .priv_auto = sizeof(struct tpm_chip),
+};
#include "tpm_tis.h"
#include "tpm_internal.h"
-#define TPM_ACCESS(l) (0x0000 | ((l) << 12))
-#define TPM_INT_ENABLE(l) (0x0008 | ((l) << 12))
-#define TPM_STS(l) (0x0018 | ((l) << 12))
-#define TPM_DATA_FIFO(l) (0x0024 | ((l) << 12))
-#define TPM_DID_VID(l) (0x0F00 | ((l) << 12))
-#define TPM_RID(l) (0x0F04 | ((l) << 12))
-
#define MAX_SPI_FRAMESIZE 64
/* Number of wait states to wait for */
return ret;
}
-static int tpm_tis_spi_read(struct udevice *dev, u16 addr, u8 *in, u16 len)
+static int tpm_tis_spi_read(struct udevice *dev, u32 addr, u16 len, u8 *in)
{
return tpm_tis_spi_xfer(dev, addr, NULL, in, len);
}
__le32 result_le;
int ret;
- ret = tpm_tis_spi_read(dev, addr, (u8 *)&result_le, sizeof(u32));
+ ret = tpm_tis_spi_read(dev, addr, sizeof(u32), (u8 *)&result_le);
if (!ret)
*result = le32_to_cpu(result_le);
return ret;
}
-static int tpm_tis_spi_write(struct udevice *dev, u16 addr, const u8 *out,
- u16 len)
-{
- return tpm_tis_spi_xfer(dev, addr, out, NULL, len);
-}
-
-static int tpm_tis_spi_check_locality(struct udevice *dev, int loc)
-{
- const u8 mask = TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID;
- struct tpm_chip *chip = dev_get_priv(dev);
- u8 buf;
- int ret;
-
- ret = tpm_tis_spi_read(dev, TPM_ACCESS(loc), &buf, 1);
- if (ret)
- return ret;
-
- if ((buf & mask) == mask) {
- chip->locality = loc;
- return 0;
- }
-
- return -ENOENT;
-}
-
-static void tpm_tis_spi_release_locality(struct udevice *dev, int loc,
- bool force)
-{
- const u8 mask = TPM_ACCESS_REQUEST_PENDING | TPM_ACCESS_VALID;
- u8 buf;
- if (tpm_tis_spi_read(dev, TPM_ACCESS(loc), &buf, 1) < 0)
- return;
-
- if (force || (buf & mask) == mask) {
- buf = TPM_ACCESS_ACTIVE_LOCALITY;
- tpm_tis_spi_write(dev, TPM_ACCESS(loc), &buf, 1);
- }
-}
-
-static int tpm_tis_spi_request_locality(struct udevice *dev, int loc)
+static int tpm_tis_spi_write(struct udevice *dev, u32 addr, u16 len, const u8 *out)
{
- struct tpm_chip *chip = dev_get_priv(dev);
- unsigned long start, stop;
- u8 buf = TPM_ACCESS_REQUEST_USE;
- int ret;
-
- ret = tpm_tis_spi_check_locality(dev, loc);
- if (!ret)
- return 0;
-
- if (ret != -ENOENT) {
- log(LOGC_NONE, LOGL_ERR, "%s: Failed to get locality: %d\n",
- __func__, ret);
- return ret;
- }
-
- ret = tpm_tis_spi_write(dev, TPM_ACCESS(loc), &buf, 1);
- if (ret) {
- log(LOGC_NONE, LOGL_ERR, "%s: Failed to write to TPM: %d\n",
- __func__, ret);
- return ret;
- }
-
- start = get_timer(0);
- stop = chip->timeout_a;
- do {
- ret = tpm_tis_spi_check_locality(dev, loc);
- if (!ret)
- return 0;
-
- if (ret != -ENOENT) {
- log(LOGC_NONE, LOGL_ERR,
- "%s: Failed to get locality: %d\n", __func__, ret);
- return ret;
- }
-
- mdelay(TPM_TIMEOUT_MS);
- } while (get_timer(start) < stop);
-
- log(LOGC_NONE, LOGL_ERR, "%s: Timeout getting locality: %d\n", __func__,
- ret);
-
- return ret;
-}
-
-static u8 tpm_tis_spi_status(struct udevice *dev, u8 *status)
-{
- struct tpm_chip *chip = dev_get_priv(dev);
-
- return tpm_tis_spi_read(dev, TPM_STS(chip->locality), status, 1);
-}
-
-static int tpm_tis_spi_wait_for_stat(struct udevice *dev, u8 mask,
- unsigned long timeout, u8 *status)
-{
- unsigned long start = get_timer(0);
- unsigned long stop = timeout;
- int ret;
-
- do {
- mdelay(TPM_TIMEOUT_MS);
- ret = tpm_tis_spi_status(dev, status);
- if (ret)
- return ret;
-
- if ((*status & mask) == mask)
- return 0;
- } while (get_timer(start) < stop);
-
- return -ETIMEDOUT;
-}
-
-static u8 tpm_tis_spi_valid_status(struct udevice *dev, u8 *status)
-{
- struct tpm_chip *chip = dev_get_priv(dev);
-
- return tpm_tis_spi_wait_for_stat(dev, TPM_STS_VALID,
- chip->timeout_c, status);
-}
-
-static int tpm_tis_spi_get_burstcount(struct udevice *dev)
-{
- struct tpm_chip *chip = dev_get_priv(dev);
- unsigned long start, stop;
- u32 burstcount, ret;
-
- /* wait for burstcount */
- start = get_timer(0);
- stop = chip->timeout_d;
- do {
- ret = tpm_tis_spi_read32(dev, TPM_STS(chip->locality),
- &burstcount);
- if (ret)
- return -EBUSY;
-
- burstcount = (burstcount >> 8) & 0xFFFF;
- if (burstcount)
- return burstcount;
-
- mdelay(TPM_TIMEOUT_MS);
- } while (get_timer(start) < stop);
-
- return -EBUSY;
-}
-
-static int tpm_tis_spi_cancel(struct udevice *dev)
-{
- struct tpm_chip *chip = dev_get_priv(dev);
- u8 data = TPM_STS_COMMAND_READY;
-
- return tpm_tis_spi_write(dev, TPM_STS(chip->locality), &data, 1);
-}
-
-static int tpm_tis_spi_recv_data(struct udevice *dev, u8 *buf, size_t count)
-{
- struct tpm_chip *chip = dev_get_priv(dev);
- int size = 0, burstcnt, len, ret;
- u8 status;
-
- while (size < count &&
- tpm_tis_spi_wait_for_stat(dev,
- TPM_STS_DATA_AVAIL | TPM_STS_VALID,
- chip->timeout_c, &status) == 0) {
- burstcnt = tpm_tis_spi_get_burstcount(dev);
- if (burstcnt < 0)
- return burstcnt;
-
- len = min_t(int, burstcnt, count - size);
- ret = tpm_tis_spi_read(dev, TPM_DATA_FIFO(chip->locality),
- buf + size, len);
- if (ret < 0)
- return ret;
-
- size += len;
- }
-
- return size;
-}
-
-static int tpm_tis_spi_recv(struct udevice *dev, u8 *buf, size_t count)
-{
- struct tpm_chip *chip = dev_get_priv(dev);
- int size, expected;
-
- if (!chip)
- return -ENODEV;
-
- if (count < TPM_HEADER_SIZE) {
- size = -EIO;
- goto out;
- }
-
- size = tpm_tis_spi_recv_data(dev, buf, TPM_HEADER_SIZE);
- if (size < TPM_HEADER_SIZE) {
- log(LOGC_NONE, LOGL_ERR, "TPM error, unable to read header\n");
- goto out;
- }
-
- expected = get_unaligned_be32(buf + 2);
- if (expected > count) {
- size = -EIO;
- goto out;
- }
-
- size += tpm_tis_spi_recv_data(dev, &buf[TPM_HEADER_SIZE],
- expected - TPM_HEADER_SIZE);
- if (size < expected) {
- log(LOGC_NONE, LOGL_ERR,
- "TPM error, unable to read remaining bytes of result\n");
- size = -EIO;
- goto out;
- }
-
-out:
- tpm_tis_spi_cancel(dev);
- tpm_tis_spi_release_locality(dev, chip->locality, false);
-
- return size;
-}
-
-static int tpm_tis_spi_send(struct udevice *dev, const u8 *buf, size_t len)
-{
- struct tpm_chip *chip = dev_get_priv(dev);
- u32 i, size;
- u8 status;
- int burstcnt, ret;
- u8 data;
-
- if (!chip)
- return -ENODEV;
-
- if (len > TPM_DEV_BUFSIZE)
- return -E2BIG; /* Command is too long for our tpm, sorry */
-
- ret = tpm_tis_spi_request_locality(dev, 0);
- if (ret < 0)
- return -EBUSY;
-
- /*
- * Check if the TPM is ready. If not, if not, cancel the pending command
- * and poll on the status to be finally ready.
- */
- ret = tpm_tis_spi_status(dev, &status);
- if (ret)
- return ret;
-
- if (!(status & TPM_STS_COMMAND_READY)) {
- /* Force the transition, usually this will be done at startup */
- ret = tpm_tis_spi_cancel(dev);
- if (ret) {
- log(LOGC_NONE, LOGL_ERR,
- "%s: Could not cancel previous operation\n",
- __func__);
- goto out_err;
- }
-
- ret = tpm_tis_spi_wait_for_stat(dev, TPM_STS_COMMAND_READY,
- chip->timeout_b, &status);
- if (ret < 0 || !(status & TPM_STS_COMMAND_READY)) {
- log(LOGC_NONE, LOGL_ERR,
- "status %d after wait for stat returned %d\n",
- status, ret);
- goto out_err;
- }
- }
-
- for (i = 0; i < len - 1;) {
- burstcnt = tpm_tis_spi_get_burstcount(dev);
- if (burstcnt < 0)
- return burstcnt;
-
- size = min_t(int, len - i - 1, burstcnt);
- ret = tpm_tis_spi_write(dev, TPM_DATA_FIFO(chip->locality),
- buf + i, size);
- if (ret < 0)
- goto out_err;
-
- i += size;
- }
-
- ret = tpm_tis_spi_valid_status(dev, &status);
- if (ret)
- goto out_err;
-
- if ((status & TPM_STS_DATA_EXPECT) == 0) {
- ret = -EIO;
- goto out_err;
- }
-
- ret = tpm_tis_spi_write(dev, TPM_DATA_FIFO(chip->locality),
- buf + len - 1, 1);
- if (ret)
- goto out_err;
-
- ret = tpm_tis_spi_valid_status(dev, &status);
- if (ret)
- goto out_err;
-
- if ((status & TPM_STS_DATA_EXPECT) != 0) {
- ret = -EIO;
- goto out_err;
- }
-
- data = TPM_STS_GO;
- ret = tpm_tis_spi_write(dev, TPM_STS(chip->locality), &data, 1);
- if (ret)
- goto out_err;
-
- return len;
-
-out_err:
- tpm_tis_spi_cancel(dev);
- tpm_tis_spi_release_locality(dev, chip->locality, false);
-
- return ret;
-}
-
-static int tpm_tis_spi_cleanup(struct udevice *dev)
-{
- struct tpm_chip *chip = dev_get_priv(dev);
-
- tpm_tis_spi_cancel(dev);
- /*
- * The TPM needs some time to clean up here,
- * so we sleep rather than keeping the bus busy
- */
- mdelay(2);
- tpm_tis_spi_release_locality(dev, chip->locality, false);
-
- return 0;
-}
-
-static int tpm_tis_spi_open(struct udevice *dev)
-{
- struct tpm_chip *chip = dev_get_priv(dev);
-
- if (chip->is_open)
- return -EBUSY;
-
- chip->is_open = 1;
-
- return 0;
-}
-
-static int tpm_tis_spi_close(struct udevice *dev)
-{
- struct tpm_chip *chip = dev_get_priv(dev);
-
- if (chip->is_open) {
- tpm_tis_spi_release_locality(dev, chip->locality, true);
- chip->is_open = 0;
- }
-
- return 0;
+ return tpm_tis_spi_xfer(dev, addr, out, NULL, len);
}
-static int tpm_tis_get_desc(struct udevice *dev, char *buf, int size)
+static int tpm_tis_spi_write32(struct udevice *dev, u32 addr, u32 value)
{
- struct tpm_chip *chip = dev_get_priv(dev);
-
- if (size < 80)
- return -ENOSPC;
+ __le32 value_le = cpu_to_le32(value);
- return snprintf(buf, size,
- "%s v2.0: VendorID 0x%04x, DeviceID 0x%04x, RevisionID 0x%02x [%s]",
- dev->name, chip->vend_dev & 0xFFFF,
- chip->vend_dev >> 16, chip->rid,
- (chip->is_open ? "open" : "closed"));
+ return tpm_tis_spi_write(dev, addr, sizeof(value), (u8 *)&value_le);
}
static int tpm_tis_wait_init(struct udevice *dev, int loc)
do {
mdelay(TPM_TIMEOUT_MS);
- ret = tpm_tis_spi_read(dev, TPM_ACCESS(loc), &status, 1);
+ ret = tpm_tis_spi_read(dev, TPM_ACCESS(loc), 1, &status);
if (ret)
break;
return -EIO;
}
+static struct tpm_tis_phy_ops phy_ops = {
+ .read_bytes = tpm_tis_spi_read,
+ .write_bytes = tpm_tis_spi_write,
+ .read32 = tpm_tis_spi_read32,
+ .write32 = tpm_tis_spi_write32,
+};
+
static int tpm_tis_spi_probe(struct udevice *dev)
{
struct tpm_tis_chip_data *drv_data = (void *)dev_get_driver_data(dev);
/* Ensure a minimum amount of time elapsed since reset of the TPM */
mdelay(drv_data->time_before_first_cmd_ms);
- chip->locality = 0;
- chip->timeout_a = TIS_SHORT_TIMEOUT_MS;
- chip->timeout_b = TIS_LONG_TIMEOUT_MS;
- chip->timeout_c = TIS_SHORT_TIMEOUT_MS;
- chip->timeout_d = TIS_SHORT_TIMEOUT_MS;
- priv->pcr_count = drv_data->pcr_count;
- priv->pcr_select_min = drv_data->pcr_select_min;
-
ret = tpm_tis_wait_init(dev, chip->locality);
if (ret) {
log(LOGC_DM, LOGL_ERR, "%s: no device found\n", __func__);
return ret;
}
- ret = tpm_tis_spi_request_locality(dev, chip->locality);
- if (ret) {
- log(LOGC_NONE, LOGL_ERR, "%s: could not request locality %d\n",
- __func__, chip->locality);
- return ret;
- }
-
- ret = tpm_tis_spi_read32(dev, TPM_DID_VID(chip->locality),
- &chip->vend_dev);
- if (ret) {
- log(LOGC_NONE, LOGL_ERR,
- "%s: could not retrieve VendorID/DeviceID\n", __func__);
- return ret;
- }
-
- ret = tpm_tis_spi_read(dev, TPM_RID(chip->locality), &chip->rid, 1);
- if (ret) {
- log(LOGC_NONE, LOGL_ERR, "%s: could not retrieve RevisionID\n",
- __func__);
- return ret;
- }
+ tpm_tis_ops_register(dev, &phy_ops);
+ ret = tpm_tis_init(dev);
+ if (ret)
+ goto err;
- log(LOGC_NONE, LOGL_ERR,
- "SPI TPMv2.0 found (vid:%04x, did:%04x, rid:%02x)\n",
- chip->vend_dev & 0xFFFF, chip->vend_dev >> 16, chip->rid);
+ priv->pcr_count = drv_data->pcr_count;
+ priv->pcr_select_min = drv_data->pcr_select_min;
+ priv->version = TPM_V2;
return 0;
+err:
+ return -EINVAL;
}
-static int tpm_tis_spi_remove(struct udevice *dev)
+static int tpm_tis_spi_remove(struct udevice *udev)
{
- struct tpm_chip *chip = dev_get_priv(dev);
-
- tpm_tis_spi_release_locality(dev, chip->locality, true);
-
- return 0;
+ return tpm_tis_cleanup(udev);
}
static const struct tpm_ops tpm_tis_spi_ops = {
- .open = tpm_tis_spi_open,
- .close = tpm_tis_spi_close,
+ .open = tpm_tis_open,
+ .close = tpm_tis_close,
.get_desc = tpm_tis_get_desc,
- .send = tpm_tis_spi_send,
- .recv = tpm_tis_spi_recv,
- .cleanup = tpm_tis_spi_cleanup,
+ .send = tpm_tis_send,
+ .recv = tpm_tis_recv,
+ .cleanup = tpm_tis_cleanup,
};
static const struct tpm_tis_chip_data tpm_tis_std_chip_data = {
#include <linux/compiler.h>
#include <linux/types.h>
+/**
+ * struct tpm_tis_phy_ops - low-level TPM bus operations
+ */
+struct tpm_tis_phy_ops {
+ /* read_bytes() - Read a number of bytes from the device
+ *
+ * @udev: TPM device
+ * @addr: offset from device base
+ * @len: len to read
+ * @result: data read
+ *
+ * @return: 0 on success, negative on failure
+ */
+ int (*read_bytes)(struct udevice *udev, u32 addr, u16 len,
+ u8 *result);
+ /* write_bytes() - Read a number of bytes from the device
+ *
+ * @udev: TPM device
+ * @addr: offset from device base
+ * @len: len to read
+ * @value: data to write
+ *
+ * @return: 0 on success, negative on failure
+ */
+ int (*write_bytes)(struct udevice *udev, u32 addr, u16 len,
+ const u8 *value);
+ /* read32() - Read a 32bit value of the device
+ *
+ * @udev: TPM device
+ * @addr: offset from device base
+ * @result: data read
+ *
+ * @return: 0 on success, negative on failure
+ */
+ int (*read32)(struct udevice *udev, u32 addr, u32 *result);
+ /* write32() - write a 32bit value to the device
+ *
+ * @udev: TPM device
+ * @addr: offset from device base
+ * @src: data to write
+ *
+ * @return: 0 on success, negative on failure
+ */
+ int (*write32)(struct udevice *udev, u32 addr, u32 src);
+};
+
+enum tis_int_flags {
+ TPM_GLOBAL_INT_ENABLE = 0x80000000,
+ TPM_INTF_BURST_COUNT_STATIC = 0x100,
+ TPM_INTF_CMD_READY_INT = 0x080,
+ TPM_INTF_INT_EDGE_FALLING = 0x040,
+ TPM_INTF_INT_EDGE_RISING = 0x020,
+ TPM_INTF_INT_LEVEL_LOW = 0x010,
+ TPM_INTF_INT_LEVEL_HIGH = 0x008,
+ TPM_INTF_LOCALITY_CHANGE_INT = 0x004,
+ TPM_INTF_STS_VALID_INT = 0x002,
+ TPM_INTF_DATA_AVAIL_INT = 0x001,
+};
+
+#define TPM_ACCESS(l) (0x0000 | ((l) << 12))
+#define TPM_INT_ENABLE(l) (0x0008 | ((l) << 12))
+#define TPM_STS(l) (0x0018 | ((l) << 12))
+#define TPM_DATA_FIFO(l) (0x0024 | ((l) << 12))
+#define TPM_DID_VID(l) (0x0f00 | ((l) << 12))
+#define TPM_RID(l) (0x0f04 | ((l) << 12))
+#define TPM_INTF_CAPS(l) (0x0014 | ((l) << 12))
+
enum tpm_timeout {
TPM_TIMEOUT_MS = 5,
TIS_SHORT_TIMEOUT_MS = 750,
u8 rid;
unsigned long timeout_a, timeout_b, timeout_c, timeout_d; /* msec */
ulong chip_type;
+ struct tpm_tis_phy_ops *phy_ops;
};
struct tpm_input_header {
};
#endif
+/**
+ * tpm_tis_open - Open the device and request locality 0
+ *
+ * @dev: TPM device
+ *
+ * @return: 0 on success, negative on failure
+ */
+int tpm_tis_open(struct udevice *udev);
+/**
+ * tpm_tis_close - Close the device and release locality
+ *
+ * @dev: TPM device
+ *
+ * @return: 0 on success, negative on failure
+ */
+int tpm_tis_close(struct udevice *udev);
+/** tpm_tis_cleanup - Get the device in ready state and release locality
+ *
+ * @dev: TPM device
+ *
+ * @return: always 0
+ */
+int tpm_tis_cleanup(struct udevice *udev);
+/**
+ * tpm_tis_send - send data to the device
+ *
+ * @dev: TPM device
+ * @buf: buffer to send
+ * @len: size of the buffer
+ *
+ * @return: number of bytes sent or negative on failure
+ */
+int tpm_tis_send(struct udevice *udev, const u8 *buf, size_t len);
+/**
+ * tpm_tis_recv_data - Receive data from a device. Wrapper for tpm_tis_recv
+ *
+ * @dev: TPM device
+ * @buf: buffer to copy data
+ * @size: buffer size
+ *
+ * @return: bytes read or negative on failure
+ */
+int tpm_tis_recv(struct udevice *udev, u8 *buf, size_t count);
+/**
+ * tpm_tis_get_desc - Get the TPM description
+ *
+ * @dev: TPM device
+ * @buf: buffer to fill data
+ * @size: buffer size
+ *
+ * @return: Number of characters written (or would have been written) in buffer
+ */
+int tpm_tis_get_desc(struct udevice *udev, char *buf, int size);
+/**
+ * tpm_tis_init - inititalize the device
+ *
+ * @dev: TPM device
+ *
+ * @return: 0 on success, negative on failure
+ */
+int tpm_tis_init(struct udevice *udev);
+/**
+ * tpm_tis_ops_register - register the PHY ops for the device
+ *
+ * @dev: TPM device
+ * @ops: tpm_tis_phy_ops ops for the device
+ */
+void tpm_tis_ops_register(struct udevice *udev, struct tpm_tis_phy_ops *ops);
#endif
[UNKNOWN] = "unknown/fallback to slb9635",
};
-#define TPM_ACCESS(l) (0x0000 | ((l) << 4))
-#define TPM_STS(l) (0x0001 | ((l) << 4))
-#define TPM_DATA_FIFO(l) (0x0005 | ((l) << 4))
-#define TPM_DID_VID(l) (0x0006 | ((l) << 4))
+#define TPM_INFINEON_ACCESS(l) (0x0000 | ((l) << 4))
+#define TPM_INFINEON_STS(l) (0x0001 | ((l) << 4))
+#define TPM_INFINEON_DATA_FIFO(l) (0x0005 | ((l) << 4))
+#define TPM_INFINEON_DID_VID(l) (0x0006 | ((l) << 4))
/*
* tpm_tis_i2c_read() - read from TPM register
u8 buf;
int rc;
- rc = tpm_tis_i2c_read(dev, TPM_ACCESS(loc), &buf, 1);
+ rc = tpm_tis_i2c_read(dev, TPM_INFINEON_ACCESS(loc), &buf, 1);
if (rc < 0)
return rc;
const u8 mask = TPM_ACCESS_REQUEST_PENDING | TPM_ACCESS_VALID;
u8 buf;
- if (tpm_tis_i2c_read(dev, TPM_ACCESS(loc), &buf, 1) < 0)
+ if (tpm_tis_i2c_read(dev, TPM_INFINEON_ACCESS(loc), &buf, 1) < 0)
return;
if (force || (buf & mask) == mask) {
buf = TPM_ACCESS_ACTIVE_LOCALITY;
- tpm_tis_i2c_write(dev, TPM_ACCESS(loc), &buf, 1);
+ tpm_tis_i2c_write(dev, TPM_INFINEON_ACCESS(loc), &buf, 1);
}
}
return rc;
}
- rc = tpm_tis_i2c_write(dev, TPM_ACCESS(loc), &buf, 1);
+ rc = tpm_tis_i2c_write(dev, TPM_INFINEON_ACCESS(loc), &buf, 1);
if (rc) {
debug("%s: Failed to write to TPM: %d\n", __func__, rc);
return rc;
/* NOTE: Since i2c read may fail, return 0 in this case --> time-out */
u8 buf;
- if (tpm_tis_i2c_read(dev, TPM_STS(chip->locality), &buf, 1) < 0)
+ if (tpm_tis_i2c_read(dev, TPM_INFINEON_STS(chip->locality), &buf, 1) < 0)
return 0;
else
return buf;
u8 buf = TPM_STS_COMMAND_READY;
debug("%s\n", __func__);
- rc = tpm_tis_i2c_write_long(dev, TPM_STS(chip->locality), &buf, 1);
+ rc = tpm_tis_i2c_write_long(dev, TPM_INFINEON_STS(chip->locality), &buf, 1);
if (rc)
debug("%s: rc=%d\n", __func__, rc);
stop = chip->timeout_d;
do {
/* Note: STS is little endian */
- addr = TPM_STS(chip->locality) + 1;
+ addr = TPM_INFINEON_STS(chip->locality) + 1;
if (tpm_tis_i2c_read(dev, addr, buf, 3) < 0)
burstcnt = 0;
else
if (burstcnt > (count - size))
burstcnt = count - size;
- rc = tpm_tis_i2c_read(dev, TPM_DATA_FIFO(chip->locality),
+ rc = tpm_tis_i2c_read(dev, TPM_INFINEON_DATA_FIFO(chip->locality),
&(buf[size]), burstcnt);
if (rc == 0)
size += burstcnt;
burstcnt = CONFIG_TPM_TIS_I2C_BURST_LIMITATION_LEN;
#endif /* CONFIG_TPM_TIS_I2C_BURST_LIMITATION */
- rc = tpm_tis_i2c_write(dev, TPM_DATA_FIFO(chip->locality),
+ rc = tpm_tis_i2c_write(dev, TPM_INFINEON_DATA_FIFO(chip->locality),
&(buf[count]), burstcnt);
if (rc == 0)
count += burstcnt;
}
/* Go and do it */
- rc = tpm_tis_i2c_write(dev, TPM_STS(chip->locality), &sts, 1);
+ rc = tpm_tis_i2c_write(dev, TPM_INFINEON_STS(chip->locality), &sts, 1);
if (rc < 0)
return rc;
debug("%s: done, rc=%d\n", __func__, rc);
return rc;
/* Read four bytes from DID_VID register */
- if (tpm_tis_i2c_read(dev, TPM_DID_VID(0), (uchar *)&vendor, 4) < 0) {
+ if (tpm_tis_i2c_read(dev, TPM_INFINEON_DID_VID(0), (uchar *)&vendor, 4) < 0) {
tpm_tis_i2c_release_locality(dev, 0, 1);
return -EIO;
}
return 0;
}
-static int tpm_tis_get_desc(struct udevice *dev, char *buf, int size)
+static int tpm_tis_i2c_get_desc(struct udevice *dev, char *buf, int size)
{
struct tpm_chip *chip = dev_get_priv(dev);
static const struct tpm_ops tpm_tis_i2c_ops = {
.open = tpm_tis_i2c_open,
.close = tpm_tis_i2c_close,
- .get_desc = tpm_tis_get_desc,
+ .get_desc = tpm_tis_i2c_get_desc,
.send = tpm_tis_i2c_send,
.recv = tpm_tis_i2c_recv,
.cleanup = tpm_tis_i2c_cleanup,
return 0;
}
-static int tpm_tis_get_desc(struct udevice *dev, char *buf, int size)
+static int tpm_tis_lpc_get_desc(struct udevice *dev, char *buf, int size)
{
ulong chip_type = dev_get_driver_data(dev);
static const struct tpm_ops tpm_tis_lpc_ops = {
.open = tpm_tis_lpc_open,
.close = tpm_tis_lpc_close,
- .get_desc = tpm_tis_get_desc,
+ .get_desc = tpm_tis_lpc_get_desc,
.send = tis_senddata,
.recv = tis_readresponse,
};
dr_mode = ofnode_read_string(node, "dr_mode");
if (!dr_mode) {
- pr_err("usb dr_mode not found\n");
+ pr_debug("usb dr_mode not found\n");
return USB_DR_MODE_UNKNOWN;
}
max_speed = ofnode_read_string(node, "maximum-speed");
if (!max_speed) {
- pr_err("usb maximum-speed not found\n");
+ pr_debug("usb maximum-speed not found\n");
return USB_SPEED_UNKNOWN;
}
Support of USB2/3 functionality in Socionext UniPhier platforms.
Say 'Y' here if you have one such device.
+config USB_DWC3_LAYERSCAPE
+ bool "Freescale Layerscape platform support"
+ depends on DM_USB && USB_DWC3
+ depends on !USB_XHCI_FSL
+ help
+ Select this for Freescale Layerscape Platforms.
+
+ Host and Peripheral operation modes are supported. OTG is not
+ supported.
+
menu "PHY Subsystem"
config USB_DWC3_PHY_OMAP
obj-$(CONFIG_USB_DWC3_MESON_GXL) += dwc3-meson-gxl.o
obj-$(CONFIG_USB_DWC3_GENERIC) += dwc3-generic.o
obj-$(CONFIG_USB_DWC3_UNIPHIER) += dwc3-uniphier.o
+obj-$(CONFIG_USB_DWC3_LAYERSCAPE) += dwc3-layerscape.o
obj-$(CONFIG_USB_DWC3_PHY_OMAP) += ti_usb_phy.o
obj-$(CONFIG_USB_DWC3_PHY_SAMSUNG) += samsung_usb_phy.o
return 0;
}
+/*
+ * dwc3_frame_length_adjustment - Adjusts frame length if required
+ * @dwc3: Pointer to our controller context structure
+ * @fladj: Value of GFLADJ_30MHZ to adjust frame length
+ */
+static void dwc3_frame_length_adjustment(struct dwc3 *dwc, u32 fladj)
+{
+ u32 reg;
+
+ if (dwc->revision < DWC3_REVISION_250A)
+ return;
+
+ if (fladj == 0)
+ return;
+
+ reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
+ reg &= ~DWC3_GFLADJ_30MHZ_MASK;
+ reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | fladj;
+ dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
+}
+
/**
* dwc3_free_one_event_buffer - Frees one event buffer
* @dwc: Pointer to our controller context structure
mdelay(100);
}
+/* set global incr burst type configuration registers */
+static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
+{
+ struct udevice *dev = dwc->dev;
+ u32 cfg;
+
+ if (!dwc->incrx_size)
+ return;
+
+ cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
+
+ /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
+ cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
+ if (dwc->incrx_mode)
+ cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
+ switch (dwc->incrx_size) {
+ case 256:
+ cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
+ break;
+ case 128:
+ cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
+ break;
+ case 64:
+ cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
+ break;
+ case 32:
+ cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
+ break;
+ case 16:
+ cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
+ break;
+ case 8:
+ cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
+ break;
+ case 4:
+ cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
+ break;
+ case 1:
+ break;
+ default:
+ dev_err(dev, "Invalid property\n");
+ break;
+ }
+
+ dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
+}
+
/**
* dwc3_core_init - Low-level initialization of DWC3 Core
* @dwc: Pointer to our controller context structure
if (ret)
goto err1;
+ /* Adjust Frame Length */
+ dwc3_frame_length_adjustment(dwc, dwc->fladj);
+
+ dwc3_set_incr_burst_type(dwc);
+
return 0;
err1:
u8 lpm_nyet_threshold;
u8 tx_de_emphasis;
u8 hird_threshold;
+ u32 val;
+ int i;
/* default to highest possible threshold */
lpm_nyet_threshold = 0xff;
dwc->hird_threshold = hird_threshold
| (dwc->is_utmi_l1_suspend << 4);
+
+ dev_read_u32(dev, "snps,quirk-frame-length-adjustment", &dwc->fladj);
+
+ /*
+ * Handle property "snps,incr-burst-type-adjustment".
+ * Get the number of value from this property:
+ * result <= 0, means this property is not supported.
+ * result = 1, means INCRx burst mode supported.
+ * result > 1, means undefined length burst mode supported.
+ */
+ dwc->incrx_mode = INCRX_BURST_MODE;
+ dwc->incrx_size = 0;
+ for (i = 0; i < 8; i++) {
+ if (dev_read_u32_index(dev, "snps,incr-burst-type-adjustment",
+ i, &val))
+ break;
+
+ dwc->incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
+ dwc->incrx_size = max(dwc->incrx_size, val);
+ }
}
int dwc3_init(struct dwc3 *dwc)
#define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10))
#define DWC3_GHWPARAMS8 0xc600
+#define DWC3_GFLADJ 0xc630
/* Device Registers */
#define DWC3_DCFG 0xc700
/* Bit fields */
+/* Global SoC Bus Configuration INCRx Register 0 */
+#define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7) /* INCR256 burst */
+#define DWC3_GSBUSCFG0_INCR128BRSTENA (1 << 6) /* INCR128 burst */
+#define DWC3_GSBUSCFG0_INCR64BRSTENA (1 << 5) /* INCR64 burst */
+#define DWC3_GSBUSCFG0_INCR32BRSTENA (1 << 4) /* INCR32 burst */
+#define DWC3_GSBUSCFG0_INCR16BRSTENA (1 << 3) /* INCR16 burst */
+#define DWC3_GSBUSCFG0_INCR8BRSTENA (1 << 2) /* INCR8 burst */
+#define DWC3_GSBUSCFG0_INCR4BRSTENA (1 << 1) /* INCR4 burst */
+#define DWC3_GSBUSCFG0_INCRBRSTENA (1 << 0) /* undefined length enable */
+#define DWC3_GSBUSCFG0_INCRBRST_MASK 0xff
+
/* Global Configuration Register */
#define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
#define DWC3_GCTL_U2RSTECN (1 << 16)
/* Global HWPARAMS6 Register */
#define DWC3_GHWPARAMS6_EN_FPGA (1 << 7)
+/* Global Frame Length Adjustment Register */
+#define DWC3_GFLADJ_30MHZ_SDBND_SEL (1 << 7)
+#define DWC3_GFLADJ_30MHZ_MASK 0x3f
+
/* Device Configuration Register */
#define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
#define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
u8 test_mode_nr;
u8 lpm_nyet_threshold;
u8 hird_threshold;
+ u32 fladj;
+ u8 incrx_mode;
+ u32 incrx_size;
unsigned delayed_status:1;
unsigned ep0_bounced:1;
struct list_head list;
};
+#define INCRX_BURST_MODE 0
+#define INCRX_UNDEF_LENGTH_BURST_MODE 1
+
/* -------------------------------------------------------------------------- */
/* -------------------------------------------------------------------------- */
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Layerscape DWC3 Glue layer
+ *
+ * Copyright (C) 2021 Michael Walle <michael@walle.cc>
+ *
+ * Based on dwc3-generic.c.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dwc3-uboot.h>
+#include <linux/usb/gadget.h>
+#include <usb.h>
+#include "core.h"
+#include "gadget.h"
+#include <usb/xhci.h>
+
+struct dwc3_layerscape_plat {
+ fdt_addr_t base;
+ u32 maximum_speed;
+ enum usb_dr_mode dr_mode;
+};
+
+struct dwc3_layerscape_priv {
+ void *base;
+ struct dwc3 dwc3;
+ struct phy_bulk phys;
+};
+
+struct dwc3_layerscape_host_priv {
+ struct xhci_ctrl xhci_ctrl;
+ struct dwc3_layerscape_priv gen_priv;
+};
+
+static int dwc3_layerscape_probe(struct udevice *dev,
+ struct dwc3_layerscape_priv *priv)
+{
+ int rc;
+ struct dwc3_layerscape_plat *plat = dev_get_plat(dev);
+ struct dwc3 *dwc3 = &priv->dwc3;
+
+ dwc3->dev = dev;
+ dwc3->maximum_speed = plat->maximum_speed;
+ dwc3->dr_mode = plat->dr_mode;
+ if (CONFIG_IS_ENABLED(OF_CONTROL))
+ dwc3_of_parse(dwc3);
+
+ rc = dwc3_setup_phy(dev, &priv->phys);
+ if (rc && rc != -ENOTSUPP)
+ return rc;
+
+ priv->base = map_physmem(plat->base, DWC3_OTG_REGS_END, MAP_NOCACHE);
+ dwc3->regs = priv->base + DWC3_GLOBALS_REGS_START;
+
+ rc = dwc3_init(dwc3);
+ if (rc) {
+ unmap_physmem(priv->base, MAP_NOCACHE);
+ return rc;
+ }
+
+ return 0;
+}
+
+static int dwc3_layerscape_remove(struct udevice *dev,
+ struct dwc3_layerscape_priv *priv)
+{
+ struct dwc3 *dwc3 = &priv->dwc3;
+
+ dwc3_remove(dwc3);
+ dwc3_shutdown_phy(dev, &priv->phys);
+ unmap_physmem(dwc3->regs, MAP_NOCACHE);
+
+ return 0;
+}
+
+static int dwc3_layerscape_of_to_plat(struct udevice *dev)
+{
+ struct dwc3_layerscape_plat *plat = dev_get_plat(dev);
+ ofnode node = dev_ofnode(dev);
+
+ plat->base = dev_read_addr(dev);
+
+ plat->maximum_speed = usb_get_maximum_speed(node);
+ if (plat->maximum_speed == USB_SPEED_UNKNOWN) {
+ dev_dbg(dev, "No USB maximum speed specified. Using super speed\n");
+ plat->maximum_speed = USB_SPEED_SUPER;
+ }
+
+ plat->dr_mode = usb_get_dr_mode(node);
+ if (plat->dr_mode == USB_DR_MODE_UNKNOWN) {
+ dev_err(dev, "Invalid usb mode setup\n");
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+#if CONFIG_IS_ENABLED(DM_USB_GADGET)
+int dm_usb_gadget_handle_interrupts(struct udevice *dev)
+{
+ struct dwc3_layerscape_priv *priv = dev_get_priv(dev);
+
+ dwc3_gadget_uboot_handle_interrupt(&priv->dwc3);
+
+ return 0;
+}
+
+static int dwc3_layerscape_peripheral_probe(struct udevice *dev)
+{
+ struct dwc3_layerscape_priv *priv = dev_get_priv(dev);
+
+ return dwc3_layerscape_probe(dev, priv);
+}
+
+static int dwc3_layerscape_peripheral_remove(struct udevice *dev)
+{
+ struct dwc3_layerscape_priv *priv = dev_get_priv(dev);
+
+ return dwc3_layerscape_remove(dev, priv);
+}
+
+U_BOOT_DRIVER(dwc3_layerscape_peripheral) = {
+ .name = "dwc3-layerscape-peripheral",
+ .id = UCLASS_USB_GADGET_GENERIC,
+ .of_to_plat = dwc3_layerscape_of_to_plat,
+ .probe = dwc3_layerscape_peripheral_probe,
+ .remove = dwc3_layerscape_peripheral_remove,
+ .priv_auto = sizeof(struct dwc3_layerscape_priv),
+ .plat_auto = sizeof(struct dwc3_layerscape_plat),
+};
+#endif
+
+#if defined(CONFIG_SPL_USB_HOST_SUPPORT) || \
+ !defined(CONFIG_SPL_BUILD) && defined(CONFIG_USB_HOST)
+static int dwc3_layerscape_host_probe(struct udevice *dev)
+{
+ struct xhci_hcor *hcor;
+ struct xhci_hccr *hccr;
+ struct dwc3_layerscape_host_priv *priv = dev_get_priv(dev);
+ int rc;
+
+ rc = dwc3_layerscape_probe(dev, &priv->gen_priv);
+ if (rc)
+ return rc;
+
+ hccr = priv->gen_priv.base;
+ hcor = priv->gen_priv.base + HC_LENGTH(xhci_readl(&hccr->cr_capbase));
+
+ return xhci_register(dev, hccr, hcor);
+}
+
+static int dwc3_layerscape_host_remove(struct udevice *dev)
+{
+ struct dwc3_layerscape_host_priv *priv = dev_get_priv(dev);
+ int rc;
+
+ rc = xhci_deregister(dev);
+ if (rc)
+ return rc;
+
+ return dwc3_layerscape_remove(dev, &priv->gen_priv);
+}
+
+U_BOOT_DRIVER(dwc3_layerscape_host) = {
+ .name = "dwc3-layerscape-host",
+ .id = UCLASS_USB,
+ .of_to_plat = dwc3_layerscape_of_to_plat,
+ .probe = dwc3_layerscape_host_probe,
+ .remove = dwc3_layerscape_host_remove,
+ .priv_auto = sizeof(struct dwc3_layerscape_host_priv),
+ .plat_auto = sizeof(struct dwc3_layerscape_plat),
+ .ops = &xhci_usb_ops,
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
+#endif
+
+static int dwc3_layerscape_bind(struct udevice *dev)
+{
+ ofnode node = dev_ofnode(dev);
+ const char *name = ofnode_get_name(node);
+ enum usb_dr_mode dr_mode;
+ char *driver;
+
+ dr_mode = usb_get_dr_mode(node);
+
+ switch (dr_mode) {
+#if CONFIG_IS_ENABLED(DM_USB_GADGET)
+ case USB_DR_MODE_PERIPHERAL:
+ dev_dbg(dev, "Using peripheral mode\n");
+ driver = "dwc3-layerscape-peripheral";
+ break;
+#endif
+#if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD)
+ case USB_DR_MODE_HOST:
+ dev_dbg(dev, "Using host mode\n");
+ driver = "dwc3-layerscape-host";
+ break;
+#endif
+ default:
+ dev_dbg(dev, "Unsupported dr_mode\n");
+ return -ENODEV;
+ };
+
+ return device_bind_driver_to_node(dev, driver, name, node, NULL);
+}
+
+static const struct udevice_id dwc3_layerscape_ids[] = {
+ { .compatible = "fsl,layerscape-dwc3" },
+ { .compatible = "fsl,ls1028a-dwc3" },
+ { }
+};
+
+U_BOOT_DRIVER(dwc3_layerscape_wrapper) = {
+ .name = "dwc3-layerscape-wrapper",
+ .id = UCLASS_NOP,
+ .of_match = dwc3_layerscape_ids,
+ .bind = dwc3_layerscape_bind,
+};
#include <fdtdec.h>
#include <usb.h>
#include <asm/io.h>
+#include <dm/device_compat.h>
#include <usb/xhci.h>
#define DRD2U3H_XHC_REGS_AXIWRA 0xC08
static const struct udevice_id xhci_usb_ids[] = {
{ .compatible = "fsl,layerscape-dwc3", },
+ { .compatible = "fsl,ls1028a-dwc3", },
{ }
};
memset(gpd, 0, QMU_GPD_RING_SIZE);
ring->dma = (dma_addr_t)gpd;
gpd_ring_init(ring, gpd);
+ mtu3_flush_cache((uintptr_t)gpd, sizeof(*gpd));
return 0;
}
config USB_MUSB_SUNXI
bool "Enable sunxi OTG / DRC USB controller"
depends on ARCH_SUNXI
+ select USB_MUSB_PIO_ONLY
default y
---help---
Say y here to enable support for the sunxi OTG / DRC USB controller
config VIDEO_EFI
bool "Enable EFI framebuffer driver support"
- depends on EFI_STUB
+ depends on EFI_STUB || EFI_APP
help
Turn on this option to enable a framebuffeer driver when U-Boot is
loaded as a payload (see README.u-boot_on_efi) by an EFI BIOS where
#include <panel.h>
#include <video.h>
#include <asm/io.h>
-#include <asm/arch/gpio.h>
#include <dm/device-internal.h>
#include <dm/device_compat.h>
#include <linux/bitops.h>
*size = len;
}
+static int get_mode_info(struct vesa_mode_info *vesa)
+{
+ efi_guid_t efi_gop_guid = EFI_GRAPHICS_OUTPUT_PROTOCOL_GUID;
+ struct efi_boot_services *boot = efi_get_boot();
+ struct efi_gop_mode *mode;
+ struct efi_gop *gop;
+ int ret;
+
+ if (!boot)
+ return log_msg_ret("sys", -ENOSYS);
+ ret = boot->locate_protocol(&efi_gop_guid, NULL, (void **)&gop);
+ if (ret)
+ return log_msg_ret("prot", -ENOTSUPP);
+
+ mode = gop->mode;
+ vesa->phys_base_ptr = mode->fb_base;
+ vesa->x_resolution = mode->info->width;
+ vesa->y_resolution = mode->info->height;
+
+ return 0;
+}
+
static int save_vesa_mode(struct vesa_mode_info *vesa)
{
struct efi_entry_gopmode *mode;
int size;
int ret;
- ret = efi_info_get(EFIET_GOP_MODE, (void **)&mode, &size);
- if (ret == -ENOENT) {
- debug("efi graphics output protocol mode not found\n");
- return -ENXIO;
+ if (IS_ENABLED(CONFIG_EFI_APP)) {
+ ret = get_mode_info(vesa);
+ if (ret) {
+ printf("EFI graphics output protocol not found\n");
+ return -ENXIO;
+ }
+ } else {
+ ret = efi_info_get(EFIET_GOP_MODE, (void **)&mode, &size);
+ if (ret == -ENOENT) {
+ printf("EFI graphics output protocol mode not found\n");
+ return -ENXIO;
+ }
+ vesa->phys_base_ptr = mode->fb_base;
+ vesa->x_resolution = mode->info->width;
+ vesa->y_resolution = mode->info->height;
}
- vesa->phys_base_ptr = mode->fb_base;
- vesa->x_resolution = mode->info->width;
- vesa->y_resolution = mode->info->height;
-
if (mode->info->pixel_format < EFI_GOT_BITMASK) {
fbinfo = &efi_framebuffer_format_map[mode->info->pixel_format];
vesa->red_mask_size = fbinfo->red.size;
#include <video.h>
#include <video_bridge.h>
#include <asm/io.h>
-#include <asm/arch/gpio.h>
#include <dm/device-internal.h>
#include <dm/device_compat.h>
#include <dm/lists.h>
#include <video.h>
#include <video_bridge.h>
#include <asm/io.h>
-#include <asm/arch/gpio.h>
#include <dm/device-internal.h>
#include <dm/device_compat.h>
#include <linux/bitops.h>
config WATCHDOG_AUTOSTART
bool "Automatically start watchdog timer"
depends on WDT
+ default n if ARCH_SUNXI
default y
help
Automatically start watchdog timer and start servicing it during
default 128000 if ARCH_MX31 || ARCH_MX5 || ARCH_MX6
default 128000 if ARCH_MX7 || ARCH_VF610
default 30000 if ARCH_SOCFPGA
+ default 16000 if ARCH_SUNXI
default 60000
help
Watchdog timeout in msec
Enable the STM32 watchdog (IWDG) driver. Enable support to
configure STM32's on-SoC watchdog.
+config WDT_SUNXI
+ bool "Allwinner sunxi watchdog timer support"
+ depends on WDT && ARCH_SUNXI
+ default y
+ help
+ Enable support for the watchdog timer in Allwinner sunxi SoCs.
+
config XILINX_TB_WATCHDOG
bool "Xilinx Axi watchdog timer support"
depends on WDT
obj-$(CONFIG_WDT_K3_RTI) += rti_wdt.o
obj-$(CONFIG_WDT_SP805) += sp805_wdt.o
obj-$(CONFIG_WDT_STM32MP) += stm32mp_wdt.o
+obj-$(CONFIG_WDT_SUNXI) += sunxi_wdt.o
obj-$(CONFIG_WDT_TANGIER) += tangier_wdt.o
obj-$(CONFIG_WDT_XILINX) += xilinx_wwdt.o
static int sandbox_wdt_expire_now(struct udevice *dev, ulong flags)
{
sandbox_wdt_start(dev, 1, flags);
+ sandbox_reset();
return 0;
}
};
static const struct udevice_id sp805_wdt_ids[] = {
- { .compatible = "arm,sp805-wdt" },
+ { .compatible = "arm,sp805" },
{}
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Derived from linux/drivers/watchdog/sunxi_wdt.c:
+ * Copyright (C) 2013 Carlo Caione
+ * Copyright (C) 2012 Henrik Nordstrom
+ */
+
+#include <dm.h>
+#include <wdt.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+
+#define MSEC_PER_SEC 1000
+
+#define WDT_MAX_TIMEOUT 16
+#define WDT_TIMEOUT_MASK 0xf
+
+#define WDT_CTRL_RELOAD ((1 << 0) | (0x0a57 << 1))
+
+#define WDT_MODE_EN BIT(0)
+
+struct sunxi_wdt_reg {
+ u8 wdt_ctrl;
+ u8 wdt_cfg;
+ u8 wdt_mode;
+ u8 wdt_timeout_shift;
+ u8 wdt_reset_mask;
+ u8 wdt_reset_val;
+ u32 wdt_key_val;
+};
+
+struct sunxi_wdt_priv {
+ void __iomem *base;
+ const struct sunxi_wdt_reg *regs;
+};
+
+/* Map of timeout in seconds to register value */
+static const u8 wdt_timeout_map[1 + WDT_MAX_TIMEOUT] = {
+ [0] = 0x0,
+ [1] = 0x1,
+ [2] = 0x2,
+ [3] = 0x3,
+ [4] = 0x4,
+ [5] = 0x5,
+ [6] = 0x6,
+ [7] = 0x7,
+ [8] = 0x7,
+ [9] = 0x8,
+ [10] = 0x8,
+ [11] = 0x9,
+ [12] = 0x9,
+ [13] = 0xa,
+ [14] = 0xa,
+ [15] = 0xb,
+ [16] = 0xb,
+};
+
+static int sunxi_wdt_reset(struct udevice *dev)
+{
+ struct sunxi_wdt_priv *priv = dev_get_priv(dev);
+ const struct sunxi_wdt_reg *regs = priv->regs;
+ void __iomem *base = priv->base;
+
+ writel(WDT_CTRL_RELOAD, base + regs->wdt_ctrl);
+
+ return 0;
+}
+
+static int sunxi_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
+{
+ struct sunxi_wdt_priv *priv = dev_get_priv(dev);
+ const struct sunxi_wdt_reg *regs = priv->regs;
+ void __iomem *base = priv->base;
+ u32 val;
+
+ timeout /= MSEC_PER_SEC;
+ if (timeout > WDT_MAX_TIMEOUT)
+ timeout = WDT_MAX_TIMEOUT;
+
+ /* Set system reset function */
+ val = readl(base + regs->wdt_cfg);
+ val &= ~regs->wdt_reset_mask;
+ val |= regs->wdt_reset_val;
+ val |= regs->wdt_key_val;
+ writel(val, base + regs->wdt_cfg);
+
+ /* Set timeout and enable watchdog */
+ val = readl(base + regs->wdt_mode);
+ val &= ~(WDT_TIMEOUT_MASK << regs->wdt_timeout_shift);
+ val |= wdt_timeout_map[timeout] << regs->wdt_timeout_shift;
+ val |= WDT_MODE_EN;
+ val |= regs->wdt_key_val;
+ writel(val, base + regs->wdt_mode);
+
+ return sunxi_wdt_reset(dev);
+}
+
+static int sunxi_wdt_stop(struct udevice *dev)
+{
+ struct sunxi_wdt_priv *priv = dev_get_priv(dev);
+ const struct sunxi_wdt_reg *regs = priv->regs;
+ void __iomem *base = priv->base;
+
+ writel(regs->wdt_key_val, base + regs->wdt_mode);
+
+ return 0;
+}
+
+static int sunxi_wdt_expire_now(struct udevice *dev, ulong flags)
+{
+ int ret;
+
+ ret = sunxi_wdt_start(dev, 0, flags);
+ if (ret)
+ return ret;
+
+ mdelay(500);
+
+ return 0;
+}
+
+static const struct wdt_ops sunxi_wdt_ops = {
+ .reset = sunxi_wdt_reset,
+ .start = sunxi_wdt_start,
+ .stop = sunxi_wdt_stop,
+ .expire_now = sunxi_wdt_expire_now,
+};
+
+static const struct sunxi_wdt_reg sun4i_wdt_reg = {
+ .wdt_ctrl = 0x00,
+ .wdt_cfg = 0x04,
+ .wdt_mode = 0x04,
+ .wdt_timeout_shift = 3,
+ .wdt_reset_mask = 0x2,
+ .wdt_reset_val = 0x2,
+};
+
+static const struct sunxi_wdt_reg sun6i_wdt_reg = {
+ .wdt_ctrl = 0x10,
+ .wdt_cfg = 0x14,
+ .wdt_mode = 0x18,
+ .wdt_timeout_shift = 4,
+ .wdt_reset_mask = 0x3,
+ .wdt_reset_val = 0x1,
+};
+
+static const struct sunxi_wdt_reg sun20i_wdt_reg = {
+ .wdt_ctrl = 0x10,
+ .wdt_cfg = 0x14,
+ .wdt_mode = 0x18,
+ .wdt_timeout_shift = 4,
+ .wdt_reset_mask = 0x03,
+ .wdt_reset_val = 0x01,
+ .wdt_key_val = 0x16aa0000,
+};
+
+static const struct udevice_id sunxi_wdt_ids[] = {
+ { .compatible = "allwinner,sun4i-a10-wdt", .data = (ulong)&sun4i_wdt_reg },
+ { .compatible = "allwinner,sun6i-a31-wdt", .data = (ulong)&sun6i_wdt_reg },
+ { .compatible = "allwinner,sun20i-d1-wdt", .data = (ulong)&sun20i_wdt_reg },
+ { /* sentinel */ }
+};
+
+static int sunxi_wdt_probe(struct udevice *dev)
+{
+ struct sunxi_wdt_priv *priv = dev_get_priv(dev);
+
+ priv->base = dev_remap_addr(dev);
+ if (!priv->base)
+ return -EINVAL;
+
+ priv->regs = (void *)dev_get_driver_data(dev);
+ if (!priv->regs)
+ return -EINVAL;
+
+ sunxi_wdt_stop(dev);
+
+ return 0;
+}
+
+U_BOOT_DRIVER(sunxi_wdt) = {
+ .name = "sunxi_wdt",
+ .id = UCLASS_WDT,
+ .of_match = sunxi_wdt_ids,
+ .probe = sunxi_wdt_probe,
+ .priv_auto = sizeof(struct sunxi_wdt_priv),
+ .ops = &sunxi_wdt_ops,
+};
#include <errno.h>
#include <hang.h>
#include <log.h>
+#include <sysreset.h>
#include <time.h>
#include <wdt.h>
#include <asm/global_data.h>
priv = dev_get_uclass_priv(dev);
+ if (IS_ENABLED(CONFIG_SYSRESET_WATCHDOG_AUTO)) {
+ ret = sysreset_register_wdt(dev);
+ if (ret)
+ printf("WDT: Failed to register %s for sysreset\n",
+ dev->name);
+ }
+
if (!IS_ENABLED(CONFIG_WATCHDOG_AUTOSTART)) {
printf("WDT: Not starting %s\n", dev->name);
return;
choice
prompt "Provider of DTB for DT control"
depends on OF_CONTROL
+ default OF_BOARD if SANDBOX
config OF_SEPARATE
bool "Separate DTB for DT control"
config OF_BOARD
bool "Provided by the board (e.g a previous loader) at runtime"
- depends on !SANDBOX
help
If this option is enabled, the device tree will be provided by
the board at runtime if the board supports it, instead of being
bundled with the image.
-config OF_HOSTFILE
- bool "Host filed DTB for DT control"
- depends on SANDBOX
- help
- If this option is enabled, DTB will be read from a file on startup.
- This is only useful for Sandbox. Use the -d flag to U-Boot to
- specify the file to read.
-
endchoice
config DEFAULT_DEVICE_TREE
This value may also be positive or negative; this is handled in the
same way as CONFIG_ENV_OFFSET.
+ In case CONFIG_SYS_MMC_ENV_PART is 1 (i.e. environment in eMMC boot
+ partition) then setting CONFIG_ENV_OFFSET_REDUND to the same value
+ as CONFIG_ENV_OFFSET makes use of the second eMMC boot partition for
+ the redundant environment copy.
+
This value is also in units of bytes, but must also be aligned to
an MMC sector boundary.
#include <malloc.h>
#include <u-boot/crc.h>
#include <dm/ofnode.h>
+#include <net.h>
+#include <watchdog.h>
DECLARE_GLOBAL_DATA_PTR;
};
/*
+ * This env_set() function is defined in cmd/nvedit.c, since it calls
+ * _do_env_set(), whis is a static function in that file.
+ *
+ * int env_set(const char *varname, const char *varvalue);
+ */
+
+/**
+ * Set an environment variable to an integer value
+ *
+ * @param varname Environment variable to set
+ * @param value Value to set it to
+ * @return 0 if ok, 1 on error
+ */
+int env_set_ulong(const char *varname, ulong value)
+{
+ /* TODO: this should be unsigned */
+ char *str = simple_itoa(value);
+
+ return env_set(varname, str);
+}
+
+/**
+ * Set an environment variable to an value in hex
+ *
+ * @param varname Environment variable to set
+ * @param value Value to set it to
+ * @return 0 if ok, 1 on error
+ */
+int env_set_hex(const char *varname, ulong value)
+{
+ char str[17];
+
+ sprintf(str, "%lx", value);
+ return env_set(varname, str);
+}
+
+ulong env_get_hex(const char *varname, ulong default_val)
+{
+ const char *s;
+ ulong value;
+ char *endp;
+
+ s = env_get(varname);
+ if (s)
+ value = hextoul(s, &endp);
+ if (!s || endp == s)
+ return default_val;
+
+ return value;
+}
+
+int eth_env_get_enetaddr(const char *name, uint8_t *enetaddr)
+{
+ string_to_enetaddr(env_get(name), enetaddr);
+ return is_valid_ethaddr(enetaddr);
+}
+
+int eth_env_set_enetaddr(const char *name, const uint8_t *enetaddr)
+{
+ char buf[ARP_HLEN_ASCII + 1];
+
+ if (eth_env_get_enetaddr(name, (uint8_t *)buf))
+ return -EEXIST;
+
+ sprintf(buf, "%pM", enetaddr);
+
+ return env_set(name, buf);
+}
+
+/*
+ * Look up variable from environment,
+ * return address of storage for that variable,
+ * or NULL if not found
+ */
+char *env_get(const char *name)
+{
+ if (gd->flags & GD_FLG_ENV_READY) { /* after import into hashtable */
+ struct env_entry e, *ep;
+
+ WATCHDOG_RESET();
+
+ e.key = name;
+ e.data = NULL;
+ hsearch_r(e, ENV_FIND, &ep, &env_htab, 0);
+
+ return ep ? ep->data : NULL;
+ }
+
+ /* restricted capabilities before import */
+ if (env_get_f(name, (char *)(gd->env_buf), sizeof(gd->env_buf)) >= 0)
+ return (char *)(gd->env_buf);
+
+ return NULL;
+}
+
+/*
+ * Like env_get, but prints an error if envvar isn't defined in the
+ * environment. It always returns what env_get does, so it can be used in
+ * place of env_get without changing error handling otherwise.
+ */
+char *from_env(const char *envvar)
+{
+ char *ret;
+
+ ret = env_get(envvar);
+
+ if (!ret)
+ printf("missing environment variable: %s\n", envvar);
+
+ return ret;
+}
+
+static int env_get_from_linear(const char *env, const char *name, char *buf,
+ unsigned len)
+{
+ const char *p, *end;
+ size_t name_len;
+
+ if (name == NULL || *name == '\0')
+ return -1;
+
+ name_len = strlen(name);
+
+ for (p = env; *p != '\0'; p = end + 1) {
+ const char *value;
+ unsigned res;
+
+ for (end = p; *end != '\0'; ++end)
+ if (end - env >= CONFIG_ENV_SIZE)
+ return -1;
+
+ if (strncmp(name, p, name_len) || p[name_len] != '=')
+ continue;
+ value = &p[name_len + 1];
+
+ res = end - value;
+ memcpy(buf, value, min(len, res + 1));
+
+ if (len <= res) {
+ buf[len - 1] = '\0';
+ printf("env_buf [%u bytes] too small for value of \"%s\"\n",
+ len, name);
+ }
+
+ return res;
+ }
+
+ return -1;
+}
+
+/*
+ * Look up variable from environment for restricted C runtime env.
+ */
+int env_get_f(const char *name, char *buf, unsigned len)
+{
+ const char *env;
+
+ if (gd->env_valid == ENV_INVALID)
+ env = default_environment;
+ else
+ env = (const char *)gd->env_addr;
+
+ return env_get_from_linear(env, name, buf, len);
+}
+
+/**
+ * Decode the integer value of an environment variable and return it.
+ *
+ * @param name Name of environment variable
+ * @param base Number base to use (normally 10, or 16 for hex)
+ * @param default_val Default value to return if the variable is not
+ * found
+ * @return the decoded value, or default_val if not found
+ */
+ulong env_get_ulong(const char *name, int base, ulong default_val)
+{
+ /*
+ * We can use env_get() here, even before relocation, since the
+ * environment variable value is an integer and thus short.
+ */
+ const char *str = env_get(name);
+
+ return str ? simple_strtoul(str, NULL, base) : default_val;
+}
+
+/*
* Read an environment variable as a boolean
* Return -1 if variable does not exist (default to true)
*/
*/
char *env_get_default(const char *name)
{
- char *ret_val;
- unsigned long really_valid = gd->env_valid;
- unsigned long real_gd_flags = gd->flags;
-
- /* Pretend that the image is bad. */
- gd->flags &= ~GD_FLG_ENV_READY;
- gd->env_valid = ENV_INVALID;
- ret_val = env_get(name);
- gd->env_valid = really_valid;
- gd->flags = real_gd_flags;
- return ret_val;
+ if (env_get_from_linear(default_environment, name,
+ (char *)(gd->env_buf),
+ sizeof(gd->env_buf)) >= 0)
+ return (char *)(gd->env_buf);
+
+ return NULL;
}
void env_set_default(const char *s, int flags)
{
- if (sizeof(default_environment) > ENV_SIZE) {
- puts("*** Error - default environment is too large\n\n");
- return;
- }
-
if (s) {
if ((flags & H_INTERACTIVE) == 0) {
printf("*** Warning - %s, "
}
flags |= H_DEFAULT;
- if (himport_r(&env_htab, (char *)default_environment,
+ if (himport_r(&env_htab, default_environment,
sizeof(default_environment), '\0', flags, 0,
- 0, NULL) == 0)
+ 0, NULL) == 0) {
pr_err("## Error: Environment import failed: errno = %d\n",
errno);
+ return;
+ }
gd->flags |= GD_FLG_ENV_READY;
gd->flags |= GD_FLG_ENV_DEFAULT;
* (and use \0 as a separator)
*/
flags |= H_NOCLEAR | H_DEFAULT;
- return himport_r(&env_htab, (const char *)default_environment,
+ return himport_r(&env_htab, default_environment,
sizeof(default_environment), '\0',
flags, 0, nvars, vars);
}
return rcode;
}
-/** Call this function from overridden env_get_char_spec() if you need
- * this functionality.
- */
-int env_eeprom_get_char(int index)
-{
- uchar c;
- unsigned int off = CONFIG_ENV_OFFSET;
-
-#ifdef CONFIG_ENV_OFFSET_REDUND
- if (gd->env_valid == ENV_REDUND)
- off = CONFIG_ENV_OFFSET_REDUND;
-#endif
- eeprom_bus_read(CONFIG_SYS_I2C_EEPROM_ADDR,
- off + index + offsetof(env_t, data), &c, 1);
-
- return c;
-}
-
static int env_eeprom_load(void)
{
char buf_env[CONFIG_ENV_SIZE];
return drv;
}
-__weak int env_get_char_spec(int index)
-{
- return *(uchar *)(gd->env_addr + index);
-}
-
-int env_get_char(int index)
-{
- if (gd->env_valid == ENV_INVALID)
- return default_environment[index];
- else
- return env_get_char_spec(index);
-}
-
int env_load(void)
{
struct env_driver *drv;
uchar flag1 = flash_addr->flags;
uchar flag2 = flash_addr_new->flags;
- ulong addr_default = (ulong)&default_environment[0];
ulong addr1 = (ulong)&(flash_addr->data);
ulong addr2 = (ulong)&(flash_addr_new->data);
gd->env_addr = addr2;
gd->env_valid = ENV_VALID;
} else if (!crc1_ok && !crc2_ok) {
- gd->env_addr = addr_default;
gd->env_valid = ENV_INVALID;
} else if (flag1 == ENV_REDUND_ACTIVE &&
flag2 == ENV_REDUND_OBSOLETE) {
perror:
flash_perror(rc);
done:
- if (saved_data)
- free(saved_data);
+ free(saved_data);
/* try to re-protect */
flash_sect_protect(1, (ulong)flash_addr, end_addr);
flash_sect_protect(1, (ulong)flash_addr_new, end_addr_new);
return 0;
}
- gd->env_addr = (ulong)&default_environment[0];
- gd->env_valid = ENV_INVALID;
+ gd->env_valid = ENV_INVALID;
return 0;
}
#endif
perror:
flash_perror(rc);
done:
- if (saved_data)
- free(saved_data);
+ free(saved_data);
/* try to re-protect */
flash_sect_protect(1, (long)flash_addr, end_addr);
return rc;
DECLARE_GLOBAL_DATA_PTR;
+/*
+ * In case the environment is redundant, stored in eMMC hardware boot
+ * partition and the environment and redundant environment offsets are
+ * identical, store the environment and redundant environment in both
+ * eMMC boot partitions, one copy in each.
+ * */
+#if (defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT) && \
+ (CONFIG_SYS_MMC_ENV_PART == 1) && \
+ (CONFIG_ENV_OFFSET == CONFIG_ENV_OFFSET_REDUND))
+#define ENV_MMC_HWPART_REDUND
+#endif
+
#if CONFIG_IS_ENABLED(OF_CONTROL)
static inline int mmc_offset_try_partition(const char *str, int copy, s64 *val)
{
static unsigned char env_mmc_orig_hwpart;
-static int mmc_set_env_part(struct mmc *mmc)
+static int mmc_set_env_part(struct mmc *mmc, uint part)
{
- uint part = mmc_get_env_part(mmc);
int dev = mmc_get_env_dev();
int ret = 0;
- env_mmc_orig_hwpart = mmc_get_blk_desc(mmc)->hwpart;
ret = blk_select_hwpart_devnum(IF_TYPE_MMC, dev, part);
if (ret)
puts("MMC partition switch failed\n");
return ret;
}
#else
-static inline int mmc_set_env_part(struct mmc *mmc) {return 0; };
+static inline int mmc_set_env_part(struct mmc *mmc, uint part) {return 0; };
#endif
static const char *init_mmc_for_env(struct mmc *mmc)
if (mmc_init(mmc))
return "MMC init failed";
#endif
- if (mmc_set_env_part(mmc))
+ env_mmc_orig_hwpart = mmc_get_blk_desc(mmc)->hwpart;
+ if (mmc_set_env_part(mmc, mmc_get_env_part(mmc)))
return "MMC partition switch failed";
return NULL;
#ifdef CONFIG_ENV_OFFSET_REDUND
if (gd->env_valid == ENV_VALID)
copy = 1;
+
+#ifdef ENV_MMC_HWPART_REDUND
+ ret = mmc_set_env_part(mmc, copy + 1);
+ if (ret)
+ goto fini;
+#endif
+
#endif
if (mmc_get_env_addr(mmc, copy, &offset)) {
return 1;
}
- if (mmc_get_env_addr(mmc, copy, &offset))
- return CMD_RET_FAILURE;
+ if (mmc_get_env_addr(mmc, copy, &offset)) {
+ ret = CMD_RET_FAILURE;
+ goto fini;
+ }
ret = erase_env(mmc, CONFIG_ENV_SIZE, offset);
#ifdef CONFIG_ENV_OFFSET_REDUND
copy = 1;
- if (mmc_get_env_addr(mmc, copy, &offset))
- return CMD_RET_FAILURE;
+#ifdef ENV_MMC_HWPART_REDUND
+ ret = mmc_set_env_part(mmc, copy + 1);
+ if (ret)
+ goto fini;
+#endif
+
+ if (mmc_get_env_addr(mmc, copy, &offset)) {
+ ret = CMD_RET_FAILURE;
+ goto fini;
+ }
ret |= erase_env(mmc, CONFIG_ENV_SIZE, offset);
#endif
+fini:
+ fini_mmc_for_env(mmc);
return ret;
}
#endif /* CONFIG_CMD_SAVEENV && !CONFIG_SPL_BUILD */
goto fini;
}
+#ifdef ENV_MMC_HWPART_REDUND
+ ret = mmc_set_env_part(mmc, 1);
+ if (ret)
+ goto fini;
+#endif
+
read1_fail = read_env(mmc, CONFIG_ENV_SIZE, offset1, tmp_env1);
+
+#ifdef ENV_MMC_HWPART_REDUND
+ ret = mmc_set_env_part(mmc, 2);
+ if (ret)
+ goto fini;
+#endif
+
read2_fail = read_env(mmc, CONFIG_ENV_SIZE, offset2, tmp_env2);
ret = env_import_redund((char *)tmp_env1, read1_fail, (char *)tmp_env2,
gd->env_addr = (ulong)env_ptr->data;
#else /* ENV_IS_EMBEDDED || CONFIG_NAND_ENV_DST */
- gd->env_addr = (ulong)&default_environment[0];
- gd->env_valid = ENV_VALID;
+ gd->env_valid = ENV_INVALID;
#endif /* ENV_IS_EMBEDDED || CONFIG_NAND_ENV_DST */
return 0;
*/
static int env_nowhere_init(void)
{
- gd->env_addr = (ulong)&default_environment[0];
- gd->env_valid = ENV_INVALID;
+ gd->env_valid = ENV_INVALID;
return 0;
}
static int env_nowhere_load(void)
{
/*
- * for SPL, set env_valid = ENV_INVALID is enough as env_get_char()
- * return the default env if env_get is used
- * and SPL don't used env_import to reduce its size
+ * For SPL, setting env_valid = ENV_INVALID is enough, as env_get()
+ * searches default_environment array in that case.
* For U-Boot proper, import the default environment to allow reload.
*/
if (!IS_ENABLED(CONFIG_SPL_BUILD))
env_set_default(NULL, 0);
- gd->env_valid = ENV_INVALID;
+ gd->env_valid = ENV_INVALID;
return 0;
}
static env_t *env_ptr = (env_t *)CONFIG_ENV_ADDR;
#endif
-#ifdef CONFIG_SYS_NVRAM_ACCESS_ROUTINE
-/** Call this function from overridden env_get_char_spec() if you need
- * this functionality.
- */
-int env_nvram_get_char(int index)
-{
- uchar c;
-
- nvram_read(&c, CONFIG_ENV_ADDR + index, 1);
-
- return c;
-}
-#endif
-
static int env_nvram_load(void)
{
char buf[CONFIG_ENV_SIZE];
nvram_read(data, CONFIG_ENV_ADDR + sizeof(ulong), ENV_SIZE);
if (crc32(0, data, ENV_SIZE) == crc) {
- gd->env_addr = (ulong)CONFIG_ENV_ADDR + sizeof(long);
+ gd->env_addr = (ulong)CONFIG_ENV_ADDR + sizeof(long);
#else
if (crc32(0, env_ptr->data, ENV_SIZE) == env_ptr->crc) {
- gd->env_addr = (ulong)&env_ptr->data;
+ gd->env_addr = (ulong)&env_ptr->data;
#endif
gd->env_valid = ENV_VALID;
} else {
- gd->env_addr = (ulong)&default_environment[0];
- gd->env_valid = ENV_INVALID;
+ gd->env_valid = ENV_INVALID;
}
return 0;
#endif
loff_t env_addr = CONFIG_ENV_ADDR;
size_t retlen;
- struct erase_info instr = {
- .callback = NULL,
- };
+ struct erase_info instr = {};
ret = env_export(&env_new);
if (ret)
env_t *env_ptr = (env_t *)env_sf_get_env_addr();
if (crc32(0, env_ptr->data, ENV_SIZE) == env_ptr->crc) {
- gd->env_addr = (ulong)&(env_ptr->data);
- gd->env_valid = 1;
+ gd->env_addr = (ulong)&(env_ptr->data);
+ gd->env_valid = ENV_VALID;
} else {
- gd->env_addr = (ulong)&default_environment[0];
- gd->env_valid = 1;
+ gd->env_valid = ENV_INVALID;
}
return 0;
env = NULL;
- /*
- * It's OK to pass only the name piece as last (and not the whole
- * 'name=val' string), since the API_ENUM_ENV call uses env_match()
- * internally, which handles such case
- */
if (!syscall(API_ENV_ENUM, NULL, last, &env))
return NULL;
+config YAFFS_DIRECT
+ bool
+
+config YAFFS_PROVIDE_DEFS
+ bool
+
+config YAFFSFS_PROVIDE_VALUES
+ bool
+
config YAFFS2
bool "YAFFS2 filesystem support"
+ select YAFFS_DIRECT
+ select YAFFS_PROVIDE_DEFS
+ select YAFFSFS_PROVIDE_VALUES
help
This provides access to YAFFS2 filesystems. Yet Another Flash
Filesystem 2 is a filesystem designed specifically for NAND flash.
yaffs_packedtags1.o yaffs_packedtags2.o yaffs_qsort.o \
yaffs_summary.o yaffs_tagscompat.o yaffs_verify.o yaffs_yaffs1.o \
yaffs_yaffs2.o yaffs_mtdif.o yaffs_mtdif2.o
-
-ccflags-y = -DCONFIG_YAFFS_DIRECT -DCONFIG_YAFFS_SHORT_NAMES_IN_RAM \
- -DCONFIG_YAFFS_YAFFS2 -DNO_Y_INLINE \
- -DCONFIG_YAFFS_PROVIDE_DEFS -DCONFIG_YAFFSFS_PROVIDE_VALUES
ei.len = dev->data_bytes_per_chunk * dev->param.chunks_per_block;
ei.time = 1000;
ei.retries = 2;
- ei.callback = NULL;
ei.priv = (u_long) dev;
/* Todo finish off the ei if required */
#define AXP152_POWEROFF (1 << 7)
/* For axp_gpio.c */
+#ifdef CONFIG_AXP152_POWER
#define AXP_GPIO0_CTRL 0x90
#define AXP_GPIO1_CTRL 0x91
#define AXP_GPIO2_CTRL 0x92
#define AXP_GPIO_CTRL_INPUT 0x02 /* Input */
#define AXP_GPIO_STATE 0x97
#define AXP_GPIO_STATE_OFFSET 0
+#endif
#define AXP209_POWEROFF BIT(7)
/* For axp_gpio.c */
+#ifdef CONFIG_AXP209_POWER
#define AXP_POWER_STATUS 0x00
#define AXP_POWER_STATUS_VBUS_PRESENT BIT(5)
#define AXP_GPIO0_CTRL 0x90
#define AXP_GPIO_CTRL_INPUT 0x02 /* Input */
#define AXP_GPIO_STATE 0x94
#define AXP_GPIO_STATE_OFFSET 4
+#endif
#define AXP221_SID 0x20
/* For axp_gpio.c */
+#ifdef CONFIG_AXP221_POWER
#define AXP_POWER_STATUS 0x00
#define AXP_POWER_STATUS_VBUS_PRESENT (1 << 5)
#define AXP_VBUS_IPSOUT 0x30
#define AXP_GPIO_CTRL_INPUT 0x02 /* Input */
#define AXP_GPIO_STATE 0x94
#define AXP_GPIO_STATE_OFFSET 0
+#endif
#define AXP809_SHUTDOWN_POWEROFF (1 << 7)
/* For axp_gpio.c */
+#ifdef CONFIG_AXP809_POWER
#define AXP_POWER_STATUS 0x00
#define AXP_POWER_STATUS_VBUS_PRESENT (1 << 5)
#define AXP_VBUS_IPSOUT 0x30
#define AXP_GPIO_CTRL_INPUT 0x02 /* Input */
#define AXP_GPIO_STATE 0x94
#define AXP_GPIO_STATE_OFFSET 0
+#endif
#define AXP818_SHUTDOWN_POWEROFF (1 << 7)
/* For axp_gpio.c */
+#ifdef CONFIG_AXP818_POWER
#define AXP_POWER_STATUS 0x00
#define AXP_POWER_STATUS_VBUS_PRESENT (1 << 5)
#define AXP_VBUS_IPSOUT 0x30
#define AXP_GPIO_CTRL_INPUT 0x02 /* Input */
#define AXP_GPIO_STATE 0x94
#define AXP_GPIO_STATE_OFFSET 0
+#endif
* X-Powers AX Power Management IC support header
*/
#ifndef _AXP_PMIC_H_
+#define _AXP_PMIC_H_
#include <stdbool.h>
-#ifdef CONFIG_AXP152_POWER
#include <axp152.h>
-#endif
-#ifdef CONFIG_AXP209_POWER
#include <axp209.h>
-#endif
-#ifdef CONFIG_AXP221_POWER
#include <axp221.h>
-#endif
-#ifdef CONFIG_AXP305_POWER
#include <axp305.h>
-#endif
-#ifdef CONFIG_AXP809_POWER
#include <axp809.h>
-#endif
-#ifdef CONFIG_AXP818_POWER
#include <axp818.h>
-#endif
#define AXP_PMIC_MODE_REG 0x3e
#define AXP_PMIC_MODE_I2C 0x00
#define BLK_PRD_SIZE 20
#define BLK_REV_SIZE 8
+#define PART_FORMAT_PCAT 0x1
+#define PART_FORMAT_GPT 0x2
+
/*
* Identifies the partition table type (ie. MBR vs GPT GUID) signature
*/
extern boot_os_fn do_bootm_vxworks;
int do_bootelf(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
-void lynxkdi_boot(image_header_t *hdr);
boot_os_fn *bootm_os_get_boot_func(int os);
*/
ulong timer_get_boot_us(void);
-#if defined(USE_HOSTCC) || !CONFIG_IS_ENABLED(BOOTSTAGE)
+#if defined(USE_HOSTCC) || !CONFIG_IS_ENABLED(SHOW_BOOT_PROGRESS)
#define show_boot_progress(val) do {} while (0)
#else
/**
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#undef CONFIG_WATCHDOG
* (easy to change)
*/
-#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#undef CONFIG_WATCHDOG
*/
#define CONFIG_MCFTMR
-#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#undef CONFIG_WATCHDOG
#define CONFIG_MCFTMR
-#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#undef CONFIG_WATCHDOG /* disable watchdog */
*/
#define CONFIG_MCFTMR
-#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#undef CONFIG_WATCHDOG
#define CONFIG_MCFTMR
-#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
/* Configuration for environment
*/
#define CONFIG_MCFTMR
-#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
* (easy to change)
*/
-#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#undef CONFIG_WATCHDOG
* (easy to change)
*/
-#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#undef CONFIG_WATCHDOG
* (easy to change)
*/
-#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#undef CONFIG_WATCHDOG
/* Miscellaneous configurable options */
-#define CONFIG_SYS_HZ 1000
-
/* Definitions for initial stack pointer and data area (in DPRAM) */
#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x2800)
#define CONFIG_SYS_INIT_RAM_SIZE (0x2e00 - 0x2800)
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2011-2012 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
+ * Copyright 2020-2021 NXP
*/
/*
#define CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_DPAA_PME
-/* Default address of microcode for the Linux Fman driver */
-#if defined(CONFIG_SPIFLASH)
-/*
- * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
- * env, so we got 0x110000.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
-#elif defined(CONFIG_SDCARD)
-/*
- * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 825KB (1650 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
-#elif defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_FMAN_FW_ADDR (8 * (128 * 1024))
-#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
-/*
- * Slave has no ucode locally, it can fetch this from remote. When implementing
- * in two corenet boards, slave's ucode could be stored in master's memory
- * space, the address can be mapped from slave TLB->slave LAW->
- * slave SRIO or PCIE outbound window->master inbound window->
- * master LAW->the ucode address in master's memory space.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
-#else
-#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
-#endif
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#ifdef CONFIG_PCI
/* additions for new ARM relocation support */
#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 */
#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
#define MTDPARTS_DEFAULT "mtdparts=spi0.0:768K(boot)ro,256K(boot-env),14M(user),1M(errlog)"
#define MTDPARTS_MTDOOPS "errlog"
-#define CONFIG_DOS_PARTITION
/*
* Environment variables configurations
#undef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
/*
- * Other required minimal configurations
- */
-#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
-
-/*
* Ethernet Driver configuration
*/
#ifdef CONFIG_CMD_NET
/* additions for new ARM relocation support */
#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 */
#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
#define MTDPARTS_DEFAULT "mtdparts=spi0.0:768K(boot)ro,256K(boot-env),14M(user),1M(errlog)"
#define MTDPARTS_MTDOOPS "errlog"
-#define CONFIG_DOS_PARTITION
/*
* Environment variables configurations
#undef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
/*
- * Other required minimal configurations
- */
-#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
-
-/*
* Ethernet Driver configuration
*/
#ifdef CONFIG_CMD_NET
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
+ * Copyright 2020-2021 NXP
*/
/*
#define CONFIG_SYS_DPAA_FMAN
-/* Default address of microcode for the Linux FMan driver */
-#if defined(CONFIG_SPIFLASH)
-/*
- * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
- * env, so we got 0x110000.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
-#define CONFIG_SYS_QE_FW_ADDR 0x130000
-#elif defined(CONFIG_SDCARD)
-/*
- * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 1MB (2048 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
- */
-#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
-#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
-#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
-/*
- * Slave has no ucode locally, it can fetch this from remote. When implementing
- * in two corenet boards, slave's ucode could be stored in master's memory
- * space, the address can be mapped from slave TLB->slave LAW->
- * slave SRIO or PCIE outbound window->master inbound window->
- * master LAW->the ucode address in master's memory space.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
-#else
-#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
-#define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
-#endif
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif /* CONFIG_NOBQFMAN */
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
+ * Copyright 2020-2021 NXP
*/
#ifndef __CONFIG_H
#define CONFIG_U_QE
-/* Default address of microcode for the Linux Fman driver */
-#if defined(CONFIG_SPIFLASH)
-/*
- * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
- * env, so we got 0x110000.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
-#elif defined(CONFIG_SDCARD)
-/*
- * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 1MB (2048 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
-#else
-#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
-#endif
-
-#if defined(CONFIG_SPIFLASH)
-#define CONFIG_SYS_QE_FW_ADDR 0x130000
-#elif defined(CONFIG_SDCARD)
-#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
-#else
-#define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
-#endif
-
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif /* CONFIG_NOBQFMAN */
#define CONFIG_SYS_DPAA_RMAN /* RMan */
#define CONFIG_SYS_INTERLAKEN
-/* Default address of microcode for the Linux Fman driver */
-#if defined(CONFIG_SPIFLASH)
-/*
- * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
- * env, so we got 0x110000.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
-#elif defined(CONFIG_SDCARD)
-/*
- * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 1MB (2048 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
-#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
-/*
- * Slave has no ucode locally, it can fetch this from remote. When implementing
- * in two corenet boards, slave's ucode could be stored in master's memory
- * space, the address can be mapped from slave TLB->slave LAW->
- * slave SRIO or PCIE outbound window->master inbound window->
- * master LAW->the ucode address in master's memory space.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
-#else
-#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
-#endif
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif /* CONFIG_NOBQFMAN */
#define CONFIG_SYS_DPAA_RMAN /* RMan */
#define CONFIG_SYS_INTERLAKEN
-/* Default address of microcode for the Linux Fman driver */
-#if defined(CONFIG_SPIFLASH)
-/*
- * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
- * env, so we got 0x110000.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
-
-#elif defined(CONFIG_SDCARD)
-/*
- * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 1MB (2048 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
-
-#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
-/*
- * Slave has no ucode locally, it can fetch this from remote. When implementing
- * in two corenet boards, slave's ucode could be stored in master's memory
- * space, the address can be mapped from slave TLB->slave LAW->
- * slave SRIO or PCIE outbound window->master inbound window->
- * master LAW->the ucode address in master's memory space.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
-#else
-#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
-#endif
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif /* CONFIG_NOBQFMAN */
#define CONFIG_SYS_DPAA_RMAN
#define CONFIG_SYS_INTERLAKEN
-/* Default address of microcode for the Linux Fman driver */
-#if defined(CONFIG_SPIFLASH)
-/*
- * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
- * env, so we got 0x110000.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
-#elif defined(CONFIG_SDCARD)
-/*
- * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 1MB (2048 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
-#else
-#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
-#endif
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SKIP_LOWLEVEL_INIT
#ifdef CONFIG_OF_CONTROL
#undef CONFIG_OF_SEPARATE
-#define CONFIG_OF_EMBED
#endif
#endif
#ifdef CONFIG_SKIP_LOWLEVEL_INIT
#ifdef CONFIG_OF_CONTROL
#undef CONFIG_OF_SEPARATE
-#define CONFIG_OF_EMBED
#endif
#endif
#endif /* ! CONFIG_SPL_BUILD */
-#define CONFIG_BMP_16BPP
#define SPLASH_SCREEN_NAND_PART "nand0,10"
#define SPLASH_SCREEN_BMP_FILE_SIZE 0x26000
#define SPLASH_SCREEN_BMP_LOAD_ADDR 0x82000000
#define CONFIG_HOSTNAME "AMCORE"
#define CONFIG_MCFTMR
-#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT 0
#define CONFIG_BOOTCOMMAND "bootm ffc20000"
"erase 0xfff00000 0xffffffff; " \
"cp.b 0x20000 0xfff00000 ${filesize}\0"
-#define CONFIG_SYS_HZ 1000
-
#define CONFIG_SYS_CLK 45000000
#define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 2)
/* Register Base Addrs */
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_MHZ 200
#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_MHZ 325
#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_MHZ 375
#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2019 Toradex
+ * Copyright 2019-2021 Toradex
*/
#ifndef __APALIS_IMX8_H
#define CONFIG_REMAKE_ELF
-#define CONFIG_DISPLAY_BOARDINFO_LATE
-
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5b010000
#define USDHC2_BASE_ADDR 0x5b020000
-#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
/* Networking */
#define CONFIG_IPADDR 192.168.10.2
#define CONFIG_EXTRA_ENV_SETTINGS \
BOOTENV \
MEM_LAYOUT_ENV_SETTINGS \
+ "boot_file=Image\0" \
"console=ttyLP1 earlycon\0" \
"fdt_addr=0x83000000\0" \
"fdt_file=fsl-imx8qm-apalis-eval.dtb\0" \
"fdtfile=fsl-imx8qm-apalis-eval.dtb\0" \
"finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
- "image=Image\0" \
"initrd_addr=0x83800000\0" \
"initrd_high=0xffffffffffffffff\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"netargs=setenv bootargs console=${console},${baudrate} " \
"root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp" \
"\0" \
- "nfsboot=run netargs; dhcp ${loadaddr} ${image}; tftp ${fdt_addr} " \
+ "nfsboot=run netargs; dhcp ${loadaddr} ${boot_file}; tftp ${fdt_addr} " \
"apalis-imx8/${fdt_file}; booti ${loadaddr} - ${fdt_addr}\0" \
"panel=NULL\0" \
"script=boot.scr\0" \
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5b010000
#define USDHC2_BASE_ADDR 0x5b020000
-#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#define CONFIG_IPADDR 192.168.10.2
#define CONFIG_NETMASK 255.255.255.0
#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */
/* Monitor Command Prompt */
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_CBSIZE SZ_2K
#define CONFIG_SYS_MAXARGS 64
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#include "mx6_common.h"
-#undef CONFIG_DISPLAY_BOARDINFO
-
#include <asm/arch/imx-regs.h>
#include <asm/mach-imx/gpio.h>
--- /dev/null
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+
+#define CONFIG_SYS_SDRAM_BASE 0x880000000
+
+#define CONFIG_LNX_KRNL_IMG_TEXT_OFFSET_BASE CONFIG_SYS_TEXT_BASE
+
+/* Environment */
+#define ENV_DEVICE_SETTINGS \
+ "stdin=serial,usbkbd\0" \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
+
+#define ENV_MEM_LAYOUT_SETTINGS \
+ "fdt_addr_r=0x960100000\0" \
+ "kernel_addr_r=0x960200000\0"
+
+#if CONFIG_IS_ENABLED(CMD_USB)
+ #define BOOT_TARGET_USB(func) func(USB, usb, 0)
+#else
+ #define BOOT_TARGET_USB(func)
+#endif
+
+#define BOOT_TARGET_DEVICES(func) \
+ BOOT_TARGET_USB(func)
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ ENV_DEVICE_SETTINGS \
+ ENV_MEM_LAYOUT_SETTINGS \
+ BOOTENV
+
+#endif
* in u-boot command interface
*/
-#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (2)
#define CONFIG_SYS_UART2_ALT3_GPIO
#define CONFIG_SYS_NS16550_COM1 0xf040c000
-#define CONFIG_SYS_TEXT_BASE 0x10100000
#define CONFIG_SYS_INIT_RAM_ADDR 0x10200000
#include "bcmstb.h"
#define CONFIG_SYS_NS16550_COM1 0xf040ab00
-#define CONFIG_SYS_TEXT_BASE 0x80100000
#define CONFIG_SYS_INIT_RAM_ADDR 0x80200000
#include "bcmstb.h"
#define CONFIG_SYS_BOOTM_LEN 0x01800000
/* Access eMMC Boot_1 and Boot_2 partitions */
-#define CONFIG_SUPPORT_EMMC_BOOT
/* enable 64-bit PCI resources */
#define CONFIG_SYS_PCI_64BIT 1
/*
* Filesystem configuration.
*/
-#define CONFIG_DOS_PARTITION
/*
* Environment configuration.
#define CONFIG_MXC_GPT_HCLK
/* MMC */
-#define CONFIG_FSL_USDHC
/* Boot */
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* Ethernet */
-#define CONFIG_MII
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_FEC_FIXED_SPEED _1000BASET
#define CONFIG_ARP_TIMEOUT 1500UL
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_STACK 0x013E000
#define CONFIG_SPL_BSS_START_ADDR 0x00128000
#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */
#include <asm/arch/imx-regs.h>
#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_TEXT_BASE 0x0
#define CONFIG_SPL_MAX_SIZE (124 * 1024)
#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_STACK 0x013E000
#define CONFIG_SPL_BSS_START_ADDR 0x00128000
#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */
#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
-
-#define CONFIG_OF_EMBED
#endif
#define CONFIG_REMAKE_ELF
-#define CONFIG_BOARD_EARLY_INIT_F
-
/* Flat Device Tree Definitions */
#define CONFIG_OF_BOARD_SETUP
#define USDHC1_BASE_ADDR 0x5B010000
#define USDHC2_BASE_ADDR 0x5B020000
#define USDHC3_BASE_ADDR 0x5B030000
-#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
-
-#define CONFIG_ENV_OVERWRITE
/* Boot M4 */
#define M4_BOOT_ENV \
"stdout=vidconsole,serial\0" \
"stderr=vidconsole,serial\0"
-#define CONFIG_ENV_SECT_SIZE 0x1000
-#define CONFIG_ENV_OFFSET 0x003f8000
-
#define CONFIG_TPL_TEXT_BASE 0xffff8000
#define CONFIG_SYS_NS16550_MEM32
#define __CONFIG_CI20_H__
/* Ingenic JZ4780 clock configuration. */
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_MHZ 1200
#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
/* NS16550-ish UARTs */
#define CONFIG_SYS_NS16550_CLK 48000000
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
/* Ethernet: davicom DM9000 */
#define CONFIG_DRIVER_DM9000 1
#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
/* Network */
-#define CONFIG_FEC_MXC
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 0
"echo eMMC boot attempt ...; run emmcbootscript; run emmcboot; " \
"echo USB boot attempt ...; run usbbootscript; "
-#define CONFIG_SYS_HZ 1000
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#endif
/* Ethernet */
-#define CONFIG_FEC_MXC
#define CONFIG_FEC_MXC_PHYADDR 0
#define CONFIG_FEC_XCV_TYPE RGMII
#define IMX_FEC_BASE ENET_BASE_ADDR
* ---
*/
-#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
/* ---
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2018-2019 Toradex AG
+ * Copyright 2018-2021 Toradex AG
*
* Configuration settings for the Colibri iMX6ULL module.
*
#include "mx6_common.h"
#define CONFIG_IOMUX_LPSR
-#define PHYS_SDRAM_SIZE SZ_512M
+#define PHYS_SDRAM_SIZE SZ_1G
/* ENET1 */
#define IMX_FEC_BASE ENET2_BASE_ADDR
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_SERVERIP 192.168.10.1
+#if defined(CONFIG_TARGET_COLIBRI_IMX6ULL_EMMC)
+#define UBOOT_UPDATE \
+ "uboot_hwpart=1\0" \
+ "uboot_blk=2\0" \
+ "set_blkcnt=setexpr blkcnt ${filesize} + 0x1ff && " \
+ "setexpr blkcnt ${blkcnt} / 0x200\0" \
+ "update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} && " \
+ "mmc write ${loadaddr} ${uboot_blk} ${blkcnt}\0"
+#elif defined(CONFIG_TARGET_COLIBRI_IMX6ULL_NAND)
+#define UBOOT_UPDATE \
+ "update_uboot=nand erase.part u-boot1 && " \
+ "nand write ${loadaddr} u-boot1 ${filesize} && " \
+ "nand erase.part u-boot2 && " \
+ "nand write ${loadaddr} u-boot2 ${filesize}\0"
+#endif
+
#define MEM_LAYOUT_ENV_SETTINGS \
"bootm_size=0x10000000\0" \
"fdt_addr_r=0x82100000\0" \
"ramdisk_addr_r=0x82200000\0" \
"scriptaddr=0x87000000\0"
-#define UBOOT_UPDATE \
- "update_uboot=nand erase.part u-boot1 && " \
- "nand write ${loadaddr} u-boot1 ${filesize} && " \
- "nand erase.part u-boot2 && " \
- "nand write ${loadaddr} u-boot2 ${filesize}\0"
-
#define NFS_BOOTCMD \
"nfsargs=ip=:::::eth0: root=/dev/nfs\0" \
"nfsboot=run setup; " \
"ubi read ${fdt_addr_r} dtb && " \
"run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
+#if defined(CONFIG_TARGET_COLIBRI_IMX6ULL_NAND)
/* Run Distro Boot script if ubiboot fails */
#define CONFIG_BOOTCOMMAND "run ubiboot || run distro_bootcmd;"
+#define DFU_ALT_NAND_INFO "imx6ull-bcb part 0,1;u-boot1 part 0,2;u-boot2 part 0,3;u-boot-env part 0,4;ubi partubi 0,5"
+#define MODULE_EXTRA_ENV_SETTINGS \
+ "dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \
+ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+ UBI_BOOTCMD
+#else
+#define MODULE_EXTRA_ENV_SETTINGS ""
+#endif
+#if defined(CONFIG_TARGET_COLIBRI_IMX6ULL_NAND)
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0) \
+ func(USB, usb, 0) \
+ func(DHCP, dhcp, na)
+#elif defined(CONFIG_TARGET_COLIBRI_IMX6ULL_EMMC)
#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 1) \
func(MMC, mmc, 0) \
func(USB, usb, 0) \
func(DHCP, dhcp, na)
+#endif
#include <config_distro_bootcmd.h>
-#define DFU_ALT_NAND_INFO "imx6ull-bcb part 0,1;u-boot1 part 0,2;u-boot2 part 0,3;u-boot-env part 0,4;ubi partubi 0,5"
-
#define CONFIG_EXTRA_ENV_SETTINGS \
BOOTENV \
MEM_LAYOUT_ENV_SETTINGS \
"bootubipart=ubi\0" \
"console=ttymxc0\0" \
"defargs=user_debug=30\0" \
- "dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \
"fdt_board=eval-v3\0" \
"fdt_fixup=;\0" \
"ip_dyn=yes\0" \
"kernel_file=zImage\0" \
- "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
"setethupdate=if env exists ethaddr; then; else setenv ethaddr " \
"00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \
"${board}/flash_eth.img && source ${loadaddr}\0" \
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+/* environment organization */
+
+/* Environment in eMMC, before config block at the end of 1st "boot sector" */
+
+#ifdef CONFIG_TARGET_COLIBRI_IMX6ULL_NAND
/* NAND stuff */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* used to initialize CONFIG_SYS_NAND_BASE_LIST which is unused */
#define CONFIG_SYS_NAND_BASE -1
+#endif
/* USB Configs */
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_REMAKE_ELF
-#define CONFIG_DISPLAY_BOARDINFO_LATE
-
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5b010000
#define USDHC2_BASE_ADDR 0x5b020000
-#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#define CONFIG_IPADDR 192.168.10.2
#define CONFIG_NETMASK 255.255.255.0
#include "mx6_common.h"
-#undef CONFIG_DISPLAY_BOARDINFO
-
#include <asm/arch/imx-regs.h>
#include <asm/mach-imx/gpio.h>
/* Miscellaneous configurable options */
-#define CONFIG_SYS_HZ 1000
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_HZ 1000
-
/* Physical memory map */
#define PHYS_SDRAM (0x80000000)
#define PHYS_SDRAM_SIZE (256 * SZ_1M)
#define CONFIG_SPL_STACK (0x40000000 + ((212 - 16) << 10))
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_I2C
-
#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD
/* SPL related MMC defines */
-#define CONFIG_SPL_MMC
#ifdef CONFIG_SPL_BUILD
#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */
#endif
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2009-2012 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
+ * Copyright 2020-2021 NXP
*/
/*
#define CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_DPAA_PME
-/* Default address of microcode for the Linux Fman driver */
-#if defined(CONFIG_SPIFLASH)
-/*
- * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
- * env, so we got 0x110000.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
-#elif defined(CONFIG_SDCARD)
-/*
- * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 825KB (1650 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
-#elif defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_FMAN_FW_ADDR (8 * (128 * 1024))
-#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
-/*
- * Slave has no ucode locally, it can fetch this from remote. When implementing
- * in two corenet boards, slave's ucode could be stored in master's memory
- * space, the address can be mapped from slave TLB->slave LAW->
- * slave SRIO or PCIE outbound window->master inbound window->
- * master LAW->the ucode address in master's memory space.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
-#else
-#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
-#endif
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#ifdef CONFIG_PCI
#endif
/* Ethernet */
-#define CONFIG_MACB
#define CONFIG_RMII
#define CONFIG_NET_RETRY_COUNT 20
#define CONFIG_AT91_WANTS_COMMON_PHY
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
-#define CONFIG_SUPPORT_EMMC_BOOT
/* I2C configs */
/* Miscellaneous configurable options */
-#define CONFIG_SYS_HZ 1000
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_SIZE SZ_512M
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_STANDALONE_LOAD_ADDR 0x10001000
-#define CONFIG_SYS_HZ 1000
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
* High Level Configuration Options (easy to change) *
*----------------------------------------------------------------------*/
-#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#undef CONFIG_MONITOR_IS_IN_RAM /* starts uboot direct */
* Environment variables configurations
*/
-/*
- * Other required minimal configurations
- */
-
-#define CONFIG_SYS_RESET_ADDRESS 0xffff0000
-
/* Enable command line editing */
/* provide extensive help */
#undef CONFIG_TPM_TIS_BASE_ADDRESS
-#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \
- "stdout=vga,serial\0" \
- "stderr=vga,serial\0"
+#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \
+ "stdout=vidconsole\0" \
+ "stderr=vidconsole\0"
#endif
/* Ethernet */
#define CONFIG_NET_RETRY_COUNT 20
-#define CONFIG_MACB
#define CONFIG_RMII
#define CONFIG_PHY_ID 0
#define CONFIG_MACB_SEARCH_PHY
#define CONFIG_EXYNOS_SPL
-#ifdef FTRACE
-#define CONFIG_TRACE
-#define CONFIG_TRACE_BUFFER_SIZE (16 << 20)
-#define CONFIG_TRACE_EARLY_SIZE (8 << 20)
-#define CONFIG_TRACE_EARLY
-#define CONFIG_TRACE_EARLY_ADDR 0x50000000
-#endif
-
/* Enable ACE acceleration for SHA1 and SHA256 */
#define CONFIG_EXYNOS_ACE_SHA
/* High Level Configuration Options */
#define CONFIG_SAMSUNG /* in a SAMSUNG core */
-#define CONFIG_EXYNOS7420 /* Exynos7 Family */
#define CONFIG_S5P
#include <asm/arch/cpu.h> /* get chip and board defs */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration settings for the EXYNOS 78x0 based boards.
+ *
+ * Copyright (c) 2020 Dzmitry Sankouski (dsankouski@gmail.com)
+ * based on include/exynos7420-common.h
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <thomas.ab@samsung.com>
+ */
+
+#ifndef __CONFIG_EXYNOS78x0_COMMON_H
+#define __CONFIG_EXYNOS78x0_COMMON_H
+
+/* High Level Configuration Options */
+#define CONFIG_SAMSUNG /* in a SAMSUNG core */
+#define CONFIG_S5P
+
+#include <asm/arch/cpu.h> /* get chip and board defs */
+#include <linux/sizes.h>
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/* Timer input clock frequency */
+#define COUNTER_FREQUENCY 26000000
+
+/* Device Tree */
+#define CONFIG_DEVICE_TREE_LIST "EXYNOS78x0-a5y17lte"
+
+#define CPU_RELEASE_ADDR secondary_boot_addr
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600}
+
+#define CONFIG_BOARD_COMMON
+
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_2M - GENERATED_GBL_DATA_SIZE)
+/* DRAM Memory Banks */
+#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
+#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_9 (CONFIG_SYS_SDRAM_BASE + (8 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_9_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_10 (CONFIG_SYS_SDRAM_BASE + (9 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_10_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_11 (CONFIG_SYS_SDRAM_BASE + (10 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_11_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_12 (CONFIG_SYS_SDRAM_BASE + (11 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_12_SIZE SDRAM_BANK_SIZE
+
+#define CONFIG_DEBUG_UART_CLOCK 132710400
+
+#define CONFIG_PREBOOT \
+"echo Read pressed buttons status;" \
+"KEY_VOLUMEUP=gpa20;" \
+"KEY_HOME=gpa17;" \
+"KEY_VOLUMEDOWN=gpa21;" \
+"KEY_POWER=gpa00;" \
+"PRESSED=0;" \
+"RELEASED=1;" \
+"if gpio input $KEY_VOLUMEUP; then setenv VOLUME_UP $PRESSED; " \
+"else setenv VOLUME_UP $RELEASED; fi;" \
+"if gpio input $KEY_VOLUMEDOWN; then setenv VOLUME_DOWN $PRESSED; " \
+"else setenv VOLUME_DOWN $RELEASED; fi;" \
+"if gpio input $KEY_HOME; then setenv HOME $PRESSED; else setenv HOME $RELEASED; fi;" \
+"if gpio input $KEY_POWER; then setenv POWER $PRESSED; else setenv POWER $RELEASED; fi;"
+
+#ifndef MEM_LAYOUT_ENV_SETTINGS
+#define MEM_LAYOUT_ENV_SETTINGS \
+ "bootm_size=0x10000000\0" \
+ "bootm_low=0x40000000\0"
+#endif
+
+#ifndef EXYNOS_DEVICE_SETTINGS
+#define EXYNOS_DEVICE_SETTINGS \
+ "stdin=serial\0" \
+ "stdout=serial\0" \
+ "stderr=serial\0"
+#endif
+
+#ifndef EXYNOS_FDTFILE_SETTING
+#define EXYNOS_FDTFILE_SETTING
+#endif
+
+#define EXTRA_ENV_SETTINGS \
+ EXYNOS_DEVICE_SETTINGS \
+ EXYNOS_FDTFILE_SETTING \
+ MEM_LAYOUT_ENV_SETTINGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ EXTRA_ENV_SETTINGS
+
+#endif /* __CONFIG_EXYNOS78x0_COMMON_H */
#define GICR_BASE 0xF1060000
/* Ethernet RAVB */
-#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
/* I2C Configs */
#define CONFIG_I2C_GSC 0
-#define CONFIG_I2C_EDID
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_EXTRA_ENV_SETTINGS_COMMON \
"splashpos=m,m\0" \
+ "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \
"usb_pgood_delay=2000\0" \
"console=ttymxc1\0" \
"bootdevs=usb mmc sata flash\0" \
/*
* Ethernet
*/
-#define CONFIG_FEC_MXC
#define CONFIG_FEC_MXC_PHYADDR 0x1f
/*
/* Miscellaneous configurable options */
-#define CONFIG_SYS_HZ 1000
-
#ifdef CONFIG_MX6UL
# define DRAM_OFFSET(x) 0x87##x
# define FDT_ADDR __stringify(DRAM_OFFSET(800000))
/* SPL */
#ifdef CONFIG_SPL
-# ifdef CONFIG_ENV_IS_IN_NAND
-# define CONFIG_SPL_NAND_SUPPORT
-# else
-# define CONFIG_SPL_MMC
-# endif
-
# include "imx6_spl.h"
#endif
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00500000
-/* MTD device */
-
-/* DMA stuff, needed for GPMI/MXS NAND support */
-
-/* EEPROM contains serial no, MAC addr and other Logic PD info */
-#define CONFIG_I2C_EEPROM
-
/* USB Configs */
#ifdef CONFIG_CMD_USB
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
/* Miscellaneous configurable options */
-#define CONFIG_SYS_HZ 1000
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_BOOTCOMMAND "run boot${boot-mode}"
-#define CONFIG_SYS_HZ 1000
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
#define CONFIG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
-#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
* - Set the stack at the end of the free area section, at 0x00946BB8.
* - The BOOT ROM loads what they consider the firmware image
* which consists of a 4K header in front of us that contains the IVT, DCD
- * and some padding thus 'our' max size is really 0x00946BB8 - 0x00911000.
- * 64KB is more then enough for the SPL.
+ * and some padding. However, the manual also states that the ROM uses the
+ * OCRAM_EPCD and OCRAM_PXP areas for itself. While the SPL is free to use
+ * this range for stack and malloc, the SPL itself must fit below 0x920000,
+ * or the image will be truncated in at least some boot modes like USB SDP.
+ * Thus our max size is really 0x00920000 - 0x00912000. If necessary,
+ * CONFIG_SPL_TEXT_BASE could be moved to 0x00911000 to gain 4KB of space
+ * for the SPL, but 56KB should be more than enough for the SPL.
*/
-#define CONFIG_SPL_MAX_SIZE 0x10000
+#define CONFIG_SPL_MAX_SIZE 0xE000
#define CONFIG_SPL_STACK 0x00946BB8
/*
- * Pad SPL to 68KB (4KB header + 64KB max size). This allows to write the
- * SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a
- * boot media (given that boot media specific offset is configured properly).
+ * Pad SPL to 68KB (4KB header + 56KB max size + 8KB extra padding)
+ * The extra padding could be removed, but this value was used historically
+ * based on an incorrect CONFIG_SPL_MAX_SIZE definition.
+ * This allows to write the SPL/U-Boot combination generated with
+ * u-boot-with-spl.imx directly to a boot media (given that boot media specific
+ * offset is configured properly).
*/
#define CONFIG_SPL_PAD_TO 0x11000
#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
/* Monitor Command Prompt */
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_CBSIZE 2048
#define CONFIG_SYS_MAXARGS 64
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
sizeof(CONFIG_SYS_PROMPT) + 16)
/* USDHC */
-#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M)
+#define CONFIG_SYS_BOOTM_LEN (64 * SZ_1M)
#define CONFIG_SPL_MAX_SIZE (148 * 1024)
#define CONFIG_SYS_MONITOR_LEN SZ_512K
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
sizeof(CONFIG_SYS_PROMPT) + 16)
/* USDHC */
-#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
/* Monitor Command Prompt */
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_CBSIZE SZ_2K
#define CONFIG_SYS_MAXARGS 64
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-#define CONFIG_ENV_OVERWRITE
-
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#if CONFIG_IS_ENABLED(IMX8MN_BEACON_2GB_LPDDR)
#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
/* Monitor Command Prompt */
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_CBSIZE 2048
#define CONFIG_SYS_MAXARGS 64
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
sizeof(CONFIG_SYS_PROMPT) + 16)
/* USDHC */
-#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#ifdef CONFIG_SPL_BUILD
/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_STACK 0x960000
#define CONFIG_SPL_BSS_START_ADDR 0x0098FC00
#define CONFIG_SPL_BSS_MAX_SIZE 0x400 /* 1 KB */
#define FEC_QUIRK_ENET_MAC
#define DWC_NET_PHYADDR 1
-#ifdef CONFIG_DWC_ETH_QOS
-#define CONFIG_SYS_NONCACHED_MEMORY (1 * SZ_1M) /* 1M */
-#endif
#define PHY_ANEG_TIMEOUT 20000
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_FSL_USDHC
-
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_IMX_BOOTAUX
-
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M)
+#define CONFIG_SYS_BOOTM_LEN (64 * SZ_1M)
#define CONFIG_SPL_MAX_SIZE (124 * 1024)
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#ifdef CONFIG_SPL_BUILD
/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
-#define CONFIG_SPL_WATCHDOG
-#define CONFIG_SPL_DRIVERS_MISC
-#define CONFIG_SPL_POWER
-#define CONFIG_SPL_I2C
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_STACK 0x187FF0
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_GPIO
-#define CONFIG_SPL_MMC
#define CONFIG_SPL_BSS_START_ADDR 0x00180000
#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
/* ENET Config */
/* ENET1 */
#if defined(CONFIG_CMD_NET)
-#define CONFIG_MII
#define CONFIG_ETHPRIME "FEC"
-#define CONFIG_FEC_MXC
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_FEC_MXC_PHYADDR 0
#define FEC_QUIRK_ENET_MAC
-#define CONFIG_PHY_GIGE
#define IMX_FEC_BASE 0x30BE0000
#endif
#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
/* Monitor Command Prompt */
-#undef CONFIG_SYS_PROMPT
-#define CONFIG_SYS_PROMPT "u-boot=> "
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SYS_MAXARGS 64
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_IMX_BOOTAUX
-
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#ifdef CONFIG_SPL_BUILD
/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
-#define CONFIG_SPL_WATCHDOG
-#define CONFIG_SPL_DRIVERS_MISC
-#define CONFIG_SPL_POWER
-#define CONFIG_SPL_I2C
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_STACK 0x187FF0
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_GPIO
-#define CONFIG_SPL_MMC
#define CONFIG_SPL_BSS_START_ADDR 0x00180000
#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
/* ENET Config */
/* ENET1 */
#if defined(CONFIG_CMD_NET)
-#define CONFIG_MII
#define CONFIG_ETHPRIME "FEC"
-#define CONFIG_FEC_MXC
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_FEC_MXC_PHYADDR 0
#define FEC_QUIRK_ENET_MAC
-#define CONFIG_PHY_GIGE
#define IMX_FEC_BASE 0x30BE0000
-
-#define CONFIG_PHYLIB
#endif
#define CONFIG_MFG_ENV_SETTINGS \
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_IMX_BOOTAUX
-
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
+#define CONFIG_SYS_BOOTM_LEN (64 * SZ_1M)
+
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_MAX_SIZE (124 * 1024)
#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_STACK 0x013E000
#define CONFIG_SPL_BSS_START_ADDR 0x00128000
#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */
#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
-
-#define CONFIG_OF_EMBED
#endif
#define CONFIG_REMAKE_ELF
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5B010000
#define USDHC2_BASE_ADDR 0x5B020000
-#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#ifdef CONFIG_AHAB_BOOT
#define AHAB_ENV "sec_boot=yes\0"
#define CONFIG_SPL_BSS_START_ADDR 0x00128000
#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */
-#define CONFIG_FSL_USDHC
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5B010000
#define USDHC2_BASE_ADDR 0x5B020000
#define USDHC3_BASE_ADDR 0x5B030000
-#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
-
/* FUSE command */
/* Boot M4 */
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_STACK 0x013E000
#define CONFIG_SPL_BSS_START_ADDR 0x00128000
#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */
#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
-
-#define CONFIG_OF_EMBED
#endif
#define CONFIG_REMAKE_ELF
#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_STACK 0x22050000
#define CONFIG_SPL_BSS_START_ADDR 0x22048000
#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
#define CONFIG_MALLOC_F_ADDR 0x22040000
-#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x95000000 /* SPL_RAM needed */
-
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */
#endif
#define CONFIG_REMAKE_ELF
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_BOARD_LATE_INIT
-
/* ENET Config */
#if defined(CONFIG_FEC_MXC)
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-#define CONFIG_ENV_OVERWRITE
#define CONFIG_MMCROOT "/dev/mmcblk2p2"
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
/* Monitor Command Prompt */
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_CBSIZE 2048
#define CONFIG_SYS_MAXARGS 64
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* QE microcode/firmware address */
/* between the u-boot partition and env */
-#ifndef CONFIG_SYS_QE_FW_ADDR
-#define CONFIG_SYS_QE_FW_ADDR 0xF00C0000
-#endif
/*
* System IO Config
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#define CONFIG_SYS_MONITOR_LEN 0x100000 /* 1Mbyte */
-#define CONFIG_SYS_QE_FW_ADDR 0x60020000
#define CONFIG_SYS_BOOTCOUNT_BE
#define CONFIG_SYS_CS2_FTIM2 SYS_QRIO_FTIM2
#define CONFIG_SYS_CS2_FTIM3 SYS_QRIO_FTIM3
-#define CONFIG_MISC_INIT_F
#define CONFIG_HWCONFIG
/* define to use L1 as initial stack */
#define CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_DPAA_PME
-/* Default address of microcode for the Linux Fman driver */
-#define CONFIG_SYS_FMAN_FW_ADDR 0xE8020000
-#define CONFIG_SYS_QE_FW_ADDR 0xE8040000
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
/* Qman / Bman */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ *
+ * Configuration settings for the Kontron i.MX6UL boards/SoMs.
+ */
+#ifndef __KONTRON_MX6UL_CONFIG_H
+#define __KONTRON_MX6UL_CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include <linux/sizes.h>
+
+#include "mx6_common.h"
+#ifdef CONFIG_SPL_BUILD
+#include "imx6_spl.h"
+#endif
+
+/* RAM */
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE
+
+/* Board and environment settings */
+#define CONFIG_MXC_UART_BASE UART4_BASE
+#define CONFIG_HOSTNAME "kontron-mx6ul"
+#define CONFIG_ETHPRIME "eth0"
+
+#ifdef CONFIG_USB_EHCI_HCD
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#endif
+
+/* Boot order for distro boot */
+#ifndef CONFIG_SPL_BUILD
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 1) \
+ func(MMC, mmc, 0) \
+ func(UBIFS, ubifs, 0) \
+ func(USB, usb, 0) \
+ func(PXE, pxe, na) \
+ func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+#else
+#define BOOTENV
+#endif
+
+/* MMC Configs */
+#ifdef CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "kernel_addr_r=0x82000000\0" \
+ "ramdisk_addr_r=0x88080000\0" \
+ "pxefile_addr_r=0x80100000\0" \
+ "scriptaddr=0x80100000\0" \
+ "bootdelay=3\0" \
+ "ethact=" CONFIG_ETHPRIME "\0" \
+ "hostname=" CONFIG_HOSTNAME "\0" \
+ BOOTENV
+
+#endif /* __KONTRON_MX6UL_CONFIG_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 Kontron Electronics GmbH
+ *
+ * Configuration settings for the Kontron SL/BL i.MX8M-Mini boards and modules (N81xx).
+ */
+#ifndef __KONTRON_MX8MM_CONFIG_H
+#define __KONTRON_MX8MM_CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include <linux/sizes.h>
+
+#ifdef CONFIG_SPL_BUILD
+#include <config.h>
+#endif
+
+/* RAM */
+#define PHYS_SDRAM DDR_CSD1_BASE_ADDR
+#define PHYS_SDRAM_SIZE (SZ_4G)
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+
+#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Board and environment settings */
+#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
+#define CONFIG_HOSTNAME "kontron-mx8mm"
+
+#ifdef CONFIG_USB_EHCI_HCD
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#endif
+
+#ifndef CONFIG_SPL_BUILD
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 1) \
+ func(MMC, mmc, 0) \
+ func(USB, usb, 0) \
+ func(PXE, pxe, na)
+#include <config_distro_bootcmd.h>
+/* Do not try to probe USB net adapters for net boot */
+#undef BOOTENV_RUN_NET_USB_START
+#define BOOTENV_RUN_NET_USB_START
+#else
+#define BOOTENV
+#endif
+
+#define CONFIG_SYS_BOOTM_LEN SZ_64M
+#define CONFIG_SPL_MAX_SIZE (148 * SZ_1K)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_STACK 0x91fff0
+#define CONFIG_SPL_BSS_START_ADDR 0x910000
+#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K
+#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K
+/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
+#define CONFIG_MALLOC_F_ADDR 0x930000
+#endif
+
+#define FEC_QUIRK_ENET_MAC
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "kernel_addr_r=0x42000000\0" \
+ "fdt_addr_r=0x44000000\0" \
+ "ramdisk_addr_r=0x46400000\0" \
+ "pxefile_addr_r=0x46000000\0" \
+ "scriptaddr=0x46000000\0" \
+ "dfu_alt_info=sf 0:0=flash-bin raw 0x400 0x1f0000\0" \
+ "bootdelay=3\0" \
+ "hostname=" CONFIG_HOSTNAME "\0" \
+ BOOTENV
+
+#endif /* __KONTRON_MX8MM_CONFIG_H */
"envload=env import -d -b ${env_addr}\0" \
"install_rcw=source 20200000\0" \
"fdtfile=freescale/fsl-ls1028a-kontron-sl28.dtb\0" \
+ "dfu_alt_info=sf 0:0=u-boot-bin raw 0x210000 0x1d0000;" \
+ "u-boot-env raw 0x3e0000 0x20000\0" \
ENV_MEM_LAYOUT_SETTINGS \
BOOTENV
"else run netboot; fi"
/* Miscellaneous configurable options */
-#define CONFIG_SYS_HZ 1000
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#endif
#ifdef CONFIG_CMD_NET
-#define CONFIG_FEC_MXC
#define CONFIG_FEC_ENET_DEV 0
#define IMX_FEC_BASE ENET_BASE_ADDR
/* CSU */
#define CONFIG_LAYERSCAPE_NS_ACCESS
-/* PFE */
-#define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x300000
-
/*SPI device */
#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
-#define CONFIG_SYS_HZ 1000
-
#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE 128
#define SDRAM_CFG_BI 0x00000001
#ifdef CONFIG_SD_BOOT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_ENV_SUPPORT
-#define CONFIG_SPL_I2C
-#define CONFIG_SPL_WATCHDOG
-#define CONFIG_SPL_MMC
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
#define CONFIG_SPL_MAX_SIZE 0x1a000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#endif
-#define CONFIG_SYS_QE_FW_ADDR 0x67f40000
-
#define CONFIG_OF_BOARD_SETUP
#define CONFIG_OF_STDOUT_VIA_ALIAS
#define CONFIG_FSL_DEVICE_DISABLE
-
-#define CONFIG_SYS_QE_FW_ADDR 0x60940000
-
#ifdef CONFIG_LPUART
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#endif
-#define CONFIG_SYS_QE_FW_ADDR 0x60940000
-
/*
* Environment
*/
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
-#ifdef CONFIG_TFABOOT
-#define CONFIG_SYS_FMAN_FW_ADDR 0x900000
-#define CONFIG_SYS_QE_FW_ADDR 0x940000
-
-
-#else
-#if defined(CONFIG_SD_BOOT)
-/*
- * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 1MB (2040 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 18432(0x4800).
- */
-#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800)
-#define CONFIG_SYS_QE_FW_ADDR (512 * 0x4A00)
-#elif defined(CONFIG_QSPI_BOOT)
-#define CONFIG_SYS_FMAN_FW_ADDR 0x40900000
-#else
-/* FMan fireware Pre-load address */
-#define CONFIG_SYS_FMAN_FW_ADDR 0x60900000
-#define CONFIG_SYS_QE_FW_ADDR 0x60940000
-#endif
-#endif
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif
#endif
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_HZ 1000
-
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* NAND SPL */
#ifdef CONFIG_NAND_BOOT
#define CONFIG_SPL_PBL_PAD
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_ENV_SUPPORT
-#define CONFIG_SPL_WATCHDOG
-#define CONFIG_SPL_I2C
-
-#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_DRIVERS_MISC
+
#define CONFIG_SPL_MAX_SIZE 0x17000 /* 90 KiB */
#define CONFIG_SPL_STACK 0x1001f000
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
#endif
-
-#ifdef CONFIG_TFABOOT
-#define CONFIG_SYS_FMAN_FW_ADDR 0x900000
-#else
-#ifdef CONFIG_SD_BOOT
-/*
- * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 1MB (2048 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 18432(0x4800).
- */
-#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800)
-#elif defined(CONFIG_QSPI_BOOT)
-#define CONFIG_SYS_FMAN_FW_ADDR 0x40900000
-#elif defined(CONFIG_NAND_BOOT)
-#define CONFIG_SYS_FMAN_FW_ADDR (36 * (256 * 1024))
-#else
-#define CONFIG_SYS_FMAN_FW_ADDR 0x60900000
-#endif
-#endif
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
-/* DSPI */
-#ifdef CONFIG_FSL_DSPI
-#define CONFIG_SPI_FLASH_STMICRO /* cs0 */
-#define CONFIG_SPI_FLASH_SST /* cs1 */
-#define CONFIG_SPI_FLASH_EON /* cs2 */
-#endif
-
#ifdef CONFIG_SYS_DPAA_FMAN
#define RGMII_PHY1_ADDR 0x1
#define RGMII_PHY2_ADDR 0x2
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_HZ 1000
-
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#ifdef CONFIG_SPL
#define CONFIG_SPL_BSS_START_ADDR 0x80100000
#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_MAX_SIZE 0x16000
#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
unsigned long get_board_sys_clk(void);
#endif
-#ifdef CONFIG_TFABOOT
-#define CONFIG_MISC_INIT_R
-#endif
-
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_QIXIS_I2C_ACCESS
#define SYS_NO_FLASH
#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
#define CONFIG_ETHPRIME "DPMAC1@xgmii"
-#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
#endif
#define QSGMII2_PORT4_PHY_ADDR 0x1f
#define CONFIG_ETHPRIME "DPMAC1@xgmii"
-#define CONFIG_PHY_GIGE
#endif
#endif
#include <asm/arch/soc.h>
#define CONFIG_REMAKE_ELF
-#define CONFIG_FSL_LAYERSCAPE
#define CONFIG_FSL_TZPC_BP147
#define CONFIG_FSL_MEMAC
#define COUNTER_FREQUENCY 25000000 /* 25MHz */
/* Serial Port */
-#define CONFIG_PL01X_SERIAL
#define CONFIG_PL011_CLOCK (get_bus_freq(0) / 4)
#define CONFIG_SYS_SERIAL0 0x21c0000
#define CONFIG_SYS_SERIAL1 0x21d0000
/* MAC/PHY configuration */
#if defined(CONFIG_FSL_MC_ENET)
-#define CONFIG_MII
#define CONFIG_ETHPRIME "DPMAC17@rgmii-id"
#endif
/* MAC/PHY configuration */
#if defined(CONFIG_FSL_MC_ENET)
-#define CONFIG_MII
#define CONFIG_ETHPRIME "DPMAC1@xgmii"
#endif
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2020 NXP
+ * Copyright 2020-2021 NXP
*/
#ifndef __LX2162_QDS_H
/* MAC/PHY configuration */
#if defined(CONFIG_FSL_MC_ENET)
-#define CONFIG_MII
#define CONFIG_ETHPRIME "DPMAC17@rgmii-id"
#endif
"$kernelhdr_addr_sd $kernelhdr_size_sd " \
" && esbc_validate ${kernelheader_addr_r};" \
"bootm $load_addr#$BOARD\0" \
- "emmc_bootcmd=echo Trying load from emmc card..;" \
+ "sd2_bootcmd=echo Trying load from emmc card..;" \
"mmc dev 1; mmcinfo; mmc read $load_addr " \
"$kernel_addr_sd $kernel_size_sd ;" \
"env exists secureboot && mmc read $kernelheader_addr_r "\
* Ethernet on SOC (FEC)
*/
#ifdef CONFIG_CMD_NET
-#define CONFIG_FEC_MXC
#define IMX_FEC_BASE FEC_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x0
-#define CONFIG_MII
#define CONFIG_DISCOVER_PHY
#define CONFIG_FEC_XCV_TYPE RMII
#define CONFIG_ETHPRIME "FEC0"
"splashfile=boot/usplash.bmp.gz\0" \
"splashimage=0x88000000\0" \
"splashpos=m,m\0" \
+ "altbootcmd=" \
+ "if test ${mmcpart} -eq 1 ; then " \
+ "setenv mmcpart 2 ; " \
+ "else " \
+ "setenv mmcpart 1 ; " \
+ "fi ; " \
+ "boot\0" \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0" \
"addcons=" \
"setenv bootargs ${bootargs} ${miscargs}\0" \
"addargs=run addcons addmisc addmtd\0" \
"mmcload=" \
- "mmc rescan ; load mmc ${mmcdev}:${mmcpart} " \
- "${kernel_addr_r} ${bootfile}\0" \
+ "mmc rescan || reset ; load mmc ${mmcdev}:${mmcpart} " \
+ "${kernel_addr_r} ${bootfile} || reset\0" \
"miscargs=nohlt panic=1\0" \
"mmcargs=setenv bootargs root=/dev/mmcblk0p${mmcpart} rw " \
"rootwait\0" \
"mmc_mmc=" \
- "run mmcload mmcargs addargs ; " \
- "bootm ${kernel_addr_r}\0" \
+ "run mmcload mmcargs addargs || reset ; " \
+ "bootm ${kernel_addr_r} ; reset\0" \
"netload=tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \
"net_nfs=" \
"run netload nfsargs addip addargs ; " \
#include "mx6_common.h"
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
#include "imx6_spl.h"
#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + 0x80000)
#define PHYS_SDRAM_SIZE SZ_512M
-#define CONFIG_SYS_HZ 1000
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#endif
/* Ethernet */
-#define CONFIG_MACB
#define CONFIG_RMII
#define CONFIG_NET_RETRY_COUNT 20
#undef CONFIG_RESET_PHY_R
#ifndef __CONFIG_MT7620_H
#define __CONFIG_MT7620_H
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_MIPS_TIMER_FREQ 290000000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#ifndef __CONFIG_MT7628_H
#define __CONFIG_MT7628_H
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_MIPS_TIMER_FREQ 290000000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
/*
* Other required minimal configurations
*/
-#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
/* ====> Include platform Common Definitions */
/*
* Other required minimal configurations
*/
-#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
/* End of 16M scrubbed by training in bootrom */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0xFF0000)
/*
- * I2C
- */
-#define CONFIG_I2C_MV
-
-/*
* Environment
*/
#define DEFAULT_ENV_IS_RW /* required for configuring default fdtfile= */
/*
* Other required minimal configurations
*/
-#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
/* End of 16M scrubbed by training in bootrom */
/*
* PCI configuration
*/
-#ifdef CONFIG_PCIE_DW_MVEBU
-#define CONFIG_E1000
-#endif
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 1) \
#include <asm/arch/imx-regs.h>
#include <asm/mach-imx/gpio.h>
-#ifndef CONFIG_MX6
-#define CONFIG_MX6
-#endif
-
#define CONFIG_SYS_FSL_CLK
/* Miscellaneous configurable options */
/* MMC */
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_DRIVERS_MISC
-#endif
-
#endif
/* Network */
-#define CONFIG_FEC_MXC
-
#define IMX_FEC_BASE ENET2_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x0
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
/* Network */
-#define CONFIG_FEC_MXC
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x1
/* Miscellaneous configurable options */
-#define CONFIG_SYS_HZ 1000
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
/* Miscellaneous configurable options */
-#define CONFIG_SYS_HZ 1000
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#include <asm/arch/imx-regs.h>
#include <asm/mach-imx/gpio.h>
-#ifndef CONFIG_MX7
-#define CONFIG_MX7
-#endif
-
/* Timer settings */
#define CONFIG_MXC_GPT_HCLK
#define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */
#define CONFIG_ARMV7_SECURE_BASE 0x00900000
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_DRIVERS_MISC
-#endif
-
/*
* If we have defined the OPTEE ram size and not OPTEE it means that we were
* launched by OPTEE, because of that we shall skip all the low level
#include <config_distro_bootcmd.h>
-#define CONFIG_SYS_HZ 1000
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
"bootz ${loadaddr} - ${fdt_addr}; " \
"fi;\0" \
-#define CONFIG_BOOTCOMMAND \
- "if run loadimage; then " \
- "run mmcboot; " \
- "fi; " \
-
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE SZ_256K
#define LPUART_BASE LPUART4_RBASE
/* Miscellaneous configurable options */
-#define CONFIG_SYS_PROMPT "=> "
#define CONFIG_SYS_CBSIZE 512
#define CONFIG_SYS_MAXARGS 256
"fi; " \
"fi"
-#define CONFIG_SYS_HZ 1000
-
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE SZ_256K
/* SPL */
#ifndef CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_NO_CPU_SUPPORT
#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs"
#endif
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
-#define CONFIG_SYS_HZ 1000
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_SIZE SZ_256M
#define CONFIG_MXC_UART_BASE UART2_BASE
-/* I2C Configs */
-#define CONFIG_I2C_EDID
-
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_LBA48
#endif
-#define CONFIG_FEC_MXC
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_SYS_HZ 1000
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-/* environment settings */
-#if defined(CONFIG_ENV_IS_IN_MMC)
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#elif defined(CONFIG_ENV_IS_IN_NAND)
-#undef CONFIG_ENV_SIZE
-#define CONFIG_ENV_SECT_SIZE (128 << 10)
-#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-#endif
-
/* NAND */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_ETHPRIME "eth0"
#endif
-#define CONFIG_IMX_THERMAL
-
#define CONFIG_FEC_ENET_DEV 1
#define CONFIG_EXTRA_ENV_SETTINGS \
/** Stack starting address */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xffff0)
-#define CONFIG_LAST_STAGE_INIT
-
-/* Allow environment variable to be overwritten */
-#define CONFIG_ENV_OVERWRITE
-
/* Autoboot options */
#define CONFIG_RESET_TO_RETRY
#define CONFIG_BOOT_RETRY_TIME -1
"ethrotate=yes\0" \
"autoload=0\0"
-/** Environment defines */
-#if defined(CONFIG_ENV_IS_IN_MMC)
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#endif
-
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 1024 /** Console I/O Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 8192
-#undef CONFIG_SYS_PROMPT
-#define CONFIG_SYS_PROMPT env_get("prompt")
-
#if defined(CONFIG_MMC_OCTEONTX)
#define MMC_SUPPORTS_TUNING
/** EMMC specific defines */
-#define CONFIG_SUPPORT_EMMC_BOOT
#define CONFIG_SUPPORT_EMMC_RPMB
#endif
/** Heap size for U-Boot */
-/* Allow environment variable to be overwritten */
-#define CONFIG_ENV_OVERWRITE
-
/* Autoboot options */
#define CONFIG_RESET_TO_RETRY
#define CONFIG_BOOT_RETRY_TIME -1
# define CONFIG_SF_DEFAULT_CS 0
#endif
-/** Environment defines */
-#if defined(CONFIG_ENV_IS_IN_MMC)
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#endif
-
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 1024 /** Console I/O Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 8192
-#undef CONFIG_SYS_PROMPT
-#define CONFIG_SYS_PROMPT env_get("prompt")
-
/** EMMC specific defines */
#if defined(CONFIG_MMC_OCTEONTX)
-#define CONFIG_SUPPORT_EMMC_BOOT
#define CONFIG_SUPPORT_EMMC_RPMB
#endif
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
-#define CONFIG_SYS_HZ 1000
/*
* Memory Info
#define CONFIG_SPL_GD_ADDR 0x85000000
#endif
-/* -------------------------------------------------
- * Environment
- */
-//Disable persistent environment variable storage
-#define CONFIG_ENV_IS_NOWHERE 1
-
/* ---------------------------------------------------------------------
* Board boot configuration
*/
#define CONFIG_HAS_ETH2
#endif /* CONFIG_TSEC_ENET */
-#ifdef CONFIG_QE
-/* QE microcode/firmware address */
-#define CONFIG_SYS_QE_FW_ADDR 0xefec0000
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
-#endif /* CONFIG_QE */
-
/*
* Environment
*/
#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2571"
/* Board-specific serial config */
-#define CONFIG_SERIAL_MULTI
#define CONFIG_TEGRA_ENABLE_UARTA
/* Environment in eMMC, at the end of 2nd "boot sector" */
/* Miscellaneous configurable options */
-#define CONFIG_SYS_HZ 1000
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_SIZE SZ_256M
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
-#define CONFIG_SUPPORT_EMMC_BOOT
/* I2C configs */
/* Miscellaneous configurable options */
-#define CONFIG_SYS_HZ 1000
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_SIZE SZ_256M
"console=ttymxc2,115200\0" \
"fdt_addr=0x48000000\0" \
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
- "ipaddr=192.168.3.11\0" \
- "serverip=192.168.3.10\0" \
- "netmask=255.225.255.0\0" \
- "ip_dyn=no\0" \
+ "ip_dyn=yes\0" \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
"mmcroot=2\0" \
#define CONFIG_SYS_SDRAM_BASE 0x40000000
-#define PHYS_SDRAM SZ_1G
+#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */
/* UART */
#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
/* Monitor Command Prompt */
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_CBSIZE SZ_2K
#define CONFIG_SYS_MAXARGS 64
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
+
/* USDHC */
-#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
-/* ENET1 */
-#define CONFIG_ETHPRIME "FEC"
-#define CONFIG_FEC_XCV_TYPE RGMII
-#define CONFIG_FEC_MXC_PHYADDR 0
-#define FEC_QUIRK_ENET_MAC
-#define IMX_FEC_BASE 0x30BE0000
-
#endif /* __PHYCORE_IMX8MM_H */
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_STACK 0x960000
#define CONFIG_SPL_BSS_START_ADDR 0x98FC00
#define CONFIG_SPL_BSS_MAX_SIZE SZ_1K
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* USDHC */
-#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
/* MMC Configuration */
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
-#define CONFIG_SUPPORT_EMMC_BOOT
#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
/* USB Configs */
#define CONFIG_BOARD_SIZE_LIMIT 715776
/* Ethernet Configuration */
-#define CONFIG_FEC_MXC
-#define CONFIG_MII
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_ETHPRIME "FEC"
/* Network support */
-#define CONFIG_FEC_MXC
#define IMX_FEC_BASE ENET2_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x1
#define CONFIG_FEC_XCV_TYPE RMII
#include <config_distro_bootcmd.h>
#include <linux/stringify.h>
-#define CONFIG_SYS_HZ 1000
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#include <config_distro_bootcmd.h>
#include <linux/stringify.h>
-#define CONFIG_SYS_HZ 1000
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#ifdef CONFIG_SPL_BUILD
/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
-#define CONFIG_SPL_WATCHDOG
-#define CONFIG_SPL_DRIVERS_MISC
-#define CONFIG_SPL_POWER
-#define CONFIG_SPL_I2C
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_STACK 0x187FF0
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_GPIO
-#define CONFIG_SPL_MMC
#define CONFIG_SPL_BSS_START_ADDR 0x00180000
#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
/* ENET Config */
/* ENET1 */
#if defined(CONFIG_CMD_NET)
-#define CONFIG_MII
#define CONFIG_ETHPRIME "FEC"
-#define CONFIG_FEC_MXC
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_FEC_MXC_PHYADDR 1
#define FEC_QUIRK_ENET_MAC
-#define CONFIG_PHY_GIGE
#define IMX_FEC_BASE 0x30BE0000
-
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_ATHEROS
#endif
/* Initial environment variables */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_IMX_BOOTAUX
-
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
/* BOOTP options */
#define CONFIG_BOOTP_BOOTFILESIZE
-/* Miscellaneous configurable options */
-#define CONFIG_LAST_STAGE_INIT
-
/* SDRAM Bank #1 */
#define DDR_BASE 0x00000000
#define PHYS_SDRAM_1 DDR_BASE
#define CONFIG_SYS_BOOTM_LEN SZ_64M
/* For timer, QEMU emulates an ARMv7/ARMv8 architected timer */
-#define CONFIG_SYS_HZ 1000
/* Environment options */
#define CONFIG_CPU_SH7751 1
#define __LITTLE_ENDIAN__ 1
-#define CONFIG_DISPLAY_BOARDINFO
-
/* SCIF */
#define CONFIG_CONS_SCIF1 1
/* Not used: not need IRQ/FIQ stuff */
#undef CONFIG_USE_IRQ
/* decrementer freq: 1ms ticks */
-#define CONFIG_SYS_HZ 1000
/*-----------------------------------------------------------------------
* System initialize options (board_init_f)
*/
/* board_init_f->init_sequence, call arch_cpu_init */
-#define CONFIG_ARCH_CPU_INIT
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configurable options
- */
-#ifdef CONFIG_SYS_PROMPT
-#undef CONFIG_SYS_PROMPT
-/* Monitor Command Prompt */
-#define CONFIG_SYS_PROMPT "nanopi2# "
-#endif
/* Console I/O Buffer Size */
#define CONFIG_SYS_CBSIZE 1024
#endif
/* SPL */
-#define CONFIG_SPL_TEXT_BASE 0x200000
#define CONFIG_SPL_MAX_SIZE 0x10000
#define CONFIG_SPL_BSS_START_ADDR 0x20000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
#undef CONFIG_SYS_AT91_MAIN_CLOCK
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
-#define CONFIG_MISC_INIT_R
-
/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE 0x20000000
#ifndef __CONFIG_H
#define __CONFIG_H
-#ifdef FTRACE
-#define CONFIG_TRACE
-#define CONFIG_TRACE_BUFFER_SIZE (16 << 20)
-#define CONFIG_TRACE_EARLY_SIZE (16 << 20)
-#define CONFIG_TRACE_EARLY
-#define CONFIG_TRACE_EARLY_ADDR 0x00100000
-#endif
-
#ifndef CONFIG_SPL_BUILD
#define CONFIG_IO_TRACE
#endif
/* SPI - enable all SPI flash types for testing purposes */
-#define CONFIG_I2C_EDID
-
#define CONFIG_SYS_FDT_LOAD_ADDR 0x100
#define CONFIG_PHYSMEM
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration file for boards, based on Qualcomm SDM845 chip
+ *
+ * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
+ */
+
+#ifndef __CONFIGS_SDM845_H
+#define __CONFIGS_SDM845_H
+
+#include <linux/sizes.h>
+#include <asm/arch/sysmap-sdm845.h>
+
+#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 }
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY 19000000
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_BOOTM_LEN SZ_64M
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 512
+#define CONFIG_SYS_MAXARGS 64
+
+#endif
* Ethernet configuration
*
*/
-#define CONFIG_MACB
#define CONFIG_RMII /* use reduced MII inteface */
#define CONFIG_NET_RETRY_COUNT 20 /* # of DHCP/BOOTP retries */
#define CONFIG_AT91_WANTS_COMMON_PHY
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_INIT_SP_ADDR 0x301000
-#define CONFIG_SPL_STACK_R
-#define CONFIG_SPL_STACK_R_ADDR CONFIG_SYS_TEXT_BASE
#else
/*
* Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
"bootm_size=0x10000000\0" \
"mmcdev=0\0" \
"mmcpart=1\0" \
- "mmcroot=/dev/mmcblk0p1 rootwait rw\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
- "root=${mmcroot}\0" \
+ "root=/dev/mmcblk0p${mmcpart} rootwait rw\0" \
"loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${image}\0" \
"loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} boot/${fdtfile}\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcboot; " \
"fi; " \
-#define CONFIG_SYS_HZ 1000
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
/* Ethernet */
-#define CONFIG_MACB
#define CONFIG_RMII
#define CONFIG_NET_RETRY_COUNT 20
#define CONFIG_RESET_PHY_R
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8
/* Ethernet */
-#define CONFIG_MACB
#define CONFIG_RMII
#define CONFIG_NET_RETRY_COUNT 20
#define CONFIG_RESET_PHY_R
#include <asm/arch/base_addr_ac5.h>
#include <linux/stringify.h>
-/* Call misc_init_r */
-#define CONFIG_MISC_INIT_R
-
#define CONFIG_HUSH_INIT_VAR
/* Eternal oscillator */
#define CONFIG_SYS_TIMER_RATE 40000000
/* Flash device info */
-/*#define CONFIG_ENV_IS_IN_SPI_FLASH*/
-
#ifndef CONFIG_SPL_BUILD
#define CONFIG_MTD_PARTITIONS
#define MTDIDS_DEFAULT "nor0=ff705000.spi.0"
/* Miscellaneous configurable options */
-#define CONFIG_SYS_HZ 1000
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#endif
#ifdef CONFIG_CMD_NET
-#define CONFIG_FEC_MXC
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x1
#define CONFIG_FEC_XCV_TYPE RMII
"ramdisk_addr_r=0xC0438000\0" \
BOOTENV
-#define CONFIG_DISPLAY_BOARDINFO
-
/* For SPL */
#ifdef CONFIG_SUPPORT_SPL
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
* Configuration settings for the STM32MP15x CPU
*/
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __CONFIG_STM32MP15_COMMMON_H
+#define __CONFIG_STM32MP15_COMMMON_H
#include <linux/sizes.h>
#include <asm/arch/stm32.h>
-#ifndef CONFIG_TFABOOT
+#ifdef CONFIG_ARMV7_PSCI
/* PSCI support */
#define CONFIG_ARMV7_SECURE_BASE STM32_SYSRAM_BASE
#define CONFIG_ARMV7_SECURE_MAX_SIZE STM32_SYSRAM_SIZE
BOOT_TARGET_PXE(func)
/*
- * bootcmd for stm32mp1:
+ * default bootcmd for stm32mp1:
* for serial/usb: execute the stm32prog command
- * for mmc boot (eMMC, SD card), boot only on the same device
- * for nand or spi-nand boot, boot with on ubifs partition on UBI partition
- * for nor boot, use the default order
+ * for mmc boot (eMMC, SD card), distro boot on the same mmc device
+ * for nand or spi-nand boot, distro boot with ubifs on UBI partition
+ * for nor boot, use the default distro order in ${boot_targets}
*/
#define STM32MP_BOOTCMD "bootcmd_stm32mp=" \
"echo \"Boot over ${boot_device}${boot_instance}!\";" \
#ifdef CONFIG_FASTBOOT_CMD_OEM_FORMAT
/* eMMC default partitions for fastboot command: oem format */
-#define PARTS_DEFAULT \
+#define STM32MP_PARTS_DEFAULT \
"partitions=" \
"name=ssbl,size=2M;" \
"name=bootfs,size=64MB,bootable;" \
"name=rootfs,size=746M;" \
"name=userfs,size=-\0"
#else
-#define PARTS_DEFAULT
+#define STM32MP_PARTS_DEFAULT
#endif
+#define STM32MP_EXTRA \
+ "altbootcmd=run bootcmd\0" \
+ "env_check=if env info -p -d -q; then env save; fi\0" \
+ "boot_net_usb_start=true\0"
+
#include <config_distro_bootcmd.h>
/*
* 1M fdt, 1M script, 1M pxe and 1M for overlay
* and the ramdisk at the end.
*/
+#define __KERNEL_ADDR_R __stringify(0xc2000000)
+#define __FDT_ADDR_R __stringify(0xc4000000)
+#define __SCRIPT_ADDR_R __stringify(0xc4100000)
+#define __PXEFILE_ADDR_R __stringify(0xc4200000)
+#define __FDTOVERLAY_ADDR_R __stringify(0xc4300000)
+#define __RAMDISK_ADDR_R __stringify(0xc4400000)
+
+#define STM32MP_MEM_LAYOUT \
+ "kernel_addr_r=" __KERNEL_ADDR_R "\0" \
+ "fdt_addr_r=" __FDT_ADDR_R "\0" \
+ "scriptaddr=" __SCRIPT_ADDR_R "\0" \
+ "pxefile_addr_r=" __PXEFILE_ADDR_R "\0" \
+ "fdtoverlay_addr_r=" __FDTOVERLAY_ADDR_R "\0" \
+ "ramdisk_addr_r=" __RAMDISK_ADDR_R "\0"
+
#define CONFIG_EXTRA_ENV_SETTINGS \
- "kernel_addr_r=0xc2000000\0" \
- "fdt_addr_r=0xc4000000\0" \
- "scriptaddr=0xc4100000\0" \
- "pxefile_addr_r=0xc4200000\0" \
- "fdtoverlay_addr_r=0xc4300000\0" \
- "ramdisk_addr_r=0xc4400000\0" \
- "altbootcmd=run bootcmd\0" \
- "env_check=if env info -p -d -q; then env save; fi\0" \
+ STM32MP_MEM_LAYOUT \
STM32MP_BOOTCMD \
- PARTS_DEFAULT \
+ STM32MP_PARTS_DEFAULT \
BOOTENV \
- "boot_net_usb_start=true\0"
+ STM32MP_EXTRA
#endif /* ifndef CONFIG_SPL_BUILD */
#endif /* ifdef CONFIG_DISTRO_DEFAULTS*/
-#endif /* __CONFIG_H */
+#endif /* __CONFIG_STM32MP15_COMMMON_H */
* Configuration settings for the DH STM32MP15x SoMs
*/
-#ifndef __CONFIG_DH_STM32MP1_H__
-#define __CONFIG_DH_STM32MP1_H__
+#ifndef __CONFIG_STM32MP15_DH_DHSOM_H__
+#define __CONFIG_STM32MP15_DH_DHSOM_H__
-#include <configs/stm32mp1.h>
+#include <configs/stm32mp15_common.h>
#define CONFIG_SPL_TARGET "u-boot.itb"
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
+/*
+ * Copyright (C) 2021, STMicroelectronics - All Rights Reserved
+ *
+ * Configuration settings for the STMicroelectonics STM32MP15x boards
+ */
+
+#ifndef __CONFIG_STM32MP15_ST_COMMON_H__
+#define __CONFIG_STM32MP15_ST_COMMON_H__
+
+#include <configs/stm32mp15_common.h>
+
+#ifdef CONFIG_EXTRA_ENV_SETTINGS
+/*
+ * default bootcmd for stm32mp1 STMicroelectronics boards:
+ * for serial/usb: execute the stm32prog command
+ * for mmc boot (eMMC, SD card), distro boot on the same mmc device
+ * for nand or spi-nand boot, distro boot with ubifs on UBI partition
+ * for nor boot, distro boot on SD card = mmc0 ONLY !
+ */
+#define ST_STM32MP1_BOOTCMD "bootcmd_stm32mp=" \
+ "echo \"Boot over ${boot_device}${boot_instance}!\";" \
+ "if test ${boot_device} = serial || test ${boot_device} = usb;" \
+ "then stm32prog ${boot_device} ${boot_instance}; " \
+ "else " \
+ "run env_check;" \
+ "if test ${boot_device} = mmc;" \
+ "then env set boot_targets \"mmc${boot_instance}\"; fi;" \
+ "if test ${boot_device} = nand ||" \
+ " test ${boot_device} = spi-nand ;" \
+ "then env set boot_targets ubifs0; fi;" \
+ "if test ${boot_device} = nor;" \
+ "then env set boot_targets mmc0; fi;" \
+ "run distro_bootcmd;" \
+ "fi;\0"
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ STM32MP_MEM_LAYOUT \
+ ST_STM32MP1_BOOTCMD \
+ STM32MP_PARTS_DEFAULT \
+ BOOTENV \
+ STM32MP_EXTRA
+
+#endif
+#endif
#define CONFIG_HOSTNAME "stmark2"
-#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT 0
#define LDS_BOARD_TEXT \
* Environment is embedded in u-boot in the second sector of the flash
*/
-#if defined(CONFIG_CF_SBF)
-#define CONFIG_ENV_IS_IN_SPI_FLASH 1
-#endif
-
/* Cache Configuration */
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
* A23 specific configuration
*/
+#include <asm/arch/cpu.h>
+
#ifdef SUNXI_SRAM_A2_SIZE
/*
* If the SoC has enough SRAM A2, use that for the secure monitor.
/* Note SPL_STACK_R_ADDR is set through Kconfig, we include it here
* since it needs to fit in with the other values. By also #defining it
* we get warnings if the Kconfig value mismatches. */
-#define CONFIG_SPL_STACK_R_ADDR 0x2fe00000
#define CONFIG_SPL_BSS_START_ADDR 0x2ff80000
#else
#define SDRAM_OFFSET(x) 0x4##x
/* Note SPL_STACK_R_ADDR is set through Kconfig, we include it here
* since it needs to fit in with the other values. By also #defining it
* we get warnings if the Kconfig value mismatches. */
-#define CONFIG_SPL_STACK_R_ADDR 0x4fe00000
#define CONFIG_SPL_BSS_START_ADDR 0x4ff80000
#endif
#define __CONFIG_H
/* Timers for fasp(TIMCLK) */
-#define CONFIG_SYS_HZ 1000 /* 1 msec */
#define CONFIG_SYS_TIMERBASE 0x31080000 /* AP Timer 1 (ARM-SP804) */
/*
/* Serial (pl011) */
#define UART_CLK (62500000)
-#define CONFIG_SERIAL_MULTI
-#define CONFIG_PL011_SERIAL
#define CONFIG_PL011_CLOCK UART_CLK
#define CONFIG_PL01x_PORTS {(void *)(0x2a400000)}
-#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
-
/* Support MTD */
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_FLASH_BASE (0x08000000)
#endif
/* Ethernet */
-#define CONFIG_MACB
#define CONFIG_RMII
#define CONFIG_AT91_WANTS_COMMON_PHY
/* General configuration */
-#define CONFIG_SYS_HZ 1000
-
/* Physical Memory Map */
#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR
#define CONFIG_SPL_MAX_FOOTPRINT CONFIG_SYS_SPI_U_BOOT_OFFS
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-/* No falcon support */
-#undef CONFIG_SPL_OS_BOOT
-
/* FPGA commands that we don't use */
/* Extras */
#define CONFIG_BOOTCOMMAND "if mmcinfo; then " \
"if fatload mmc 0 0x1900000 ${bootscript}; then source 0x1900000; " \
"fi; fi; run $modeboot"
-#undef CONFIG_DISPLAY_BOARDINFO
#endif /* __CONFIG_TOPIC_MIAMI_H */
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_MHZ 280
#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
-#define CONFIG_FEC_MXC
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_ARP_TIMEOUT 200UL
#ifndef _CONFIG_TURRIS_MOX_H
#define _CONFIG_TURRIS_MOX_H
-#define CONFIG_SYS_BOOTM_LEN (64 << 20)
-
-#define CONFIG_LAST_STAGE_INIT
-
-/*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_DISPLAY_BOARDINFO_LATE
-
-/* additions for new ARM relocation support */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-
-/* auto boot */
-
+#define CONFIG_SYS_BOOTM_LEN (64 << 20)
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0xFF0000)
+#define CONFIG_SYS_CBSIZE 1024
+#define CONFIG_SYS_MAXARGS 32
#define CONFIG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \
9600, 19200, 38400, 57600, 115200, \
230400, 460800, 500000, 576000, \
4000000, 4500000, 5000000, 5500000, \
6000000 }
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */
-
-/*
- * Other required minimal configurations
- */
-#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
-#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
-
-/* End of 16M scrubbed by training in bootrom */
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0xFF0000)
-
-/*
- * I2C
- */
-#define CONFIG_I2C_MV
-
-/* Environment in SPI NOR flash */
-
-/*
- * Ethernet Driver configuration
- */
-#define CONFIG_ARP_TIMEOUT 200
-#define CONFIG_NET_RETRY_COUNT 50
+#define CONFIG_ARP_TIMEOUT 200
+#define CONFIG_NET_RETRY_COUNT 50
-#define CONFIG_USB_MAX_CONTROLLER_COUNT (3 + 3)
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 6
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
#include <config_distro_bootcmd.h>
-#define TURRIS_MOX_BOOTCMD_RESCUE \
- "setenv bootargs \"console=ttyMV0,115200 " \
- "earlycon=ar3700_uart,0xd0012000\" && " \
- "sf probe && " \
- "sf read 0x5000000 0x190000 && " \
- "lzmadec 0x5000000 0x5800000 && " \
+#define TURRIS_MOX_BOOTCMD_RESCUE \
+ "setenv bootargs \"console=ttyMV0,115200 " \
+ "earlycon=ar3700_uart,0xd0012000\" && " \
+ "sf probe && " \
+ "sf read 0x5000000 0x190000 && " \
+ "lzmadec 0x5000000 0x5800000 && " \
"bootm 0x5800000"
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "scriptaddr=0x4d00000\0" \
- "pxefile_addr_r=0x4e00000\0" \
- "fdt_addr_r=0x4f00000\0" \
- "kernel_addr_r=0x5000000\0" \
- "ramdisk_addr_r=0x8000000\0" \
- "fdtfile=marvell/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
- "bootcmd_rescue=" TURRIS_MOX_BOOTCMD_RESCUE "\0" \
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "scriptaddr=0x4d00000\0" \
+ "pxefile_addr_r=0x4e00000\0" \
+ "fdt_addr_r=0x4f00000\0" \
+ "kernel_addr_r=0x5000000\0" \
+ "ramdisk_addr_r=0x8000000\0" \
+ "fdtfile=marvell/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
+ "bootcmd_rescue=" TURRIS_MOX_BOOTCMD_RESCUE "\0" \
BOOTENV
#endif /* _CONFIG_TURRIS_MOX_H */
#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE)
#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MALLOC_SIMPLE
-#endif
-
#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
-#define CONFIG_SPL_DRIVERS_MISC
#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC
/* SPL related MMC defines */
#endif
/* Ethernet */
-#define CONFIG_MACB
#define CONFIG_RMII
#define CONFIG_NET_RETRY_COUNT 20
#define CONFIG_AT91_WANTS_COMMON_PHY
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2020 Toradex
+ * Copyright 2020-2021 Toradex
*/
#ifndef __VERDIN_IMX8MM_H
BOOTENV \
MEM_LAYOUT_ENV_SETTINGS \
"bootcmd_mfg=fastboot 0\0" \
+ "boot_file=Image\0" \
"console=ttymxc0\0" \
"fdt_addr=0x43000000\0" \
- "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ "fdt_board=dev\0" \
"initrd_addr=0x43800000\0" \
"initrd_high=0xffffffffffffffff\0" \
- "kernel_image=Image\0" \
"netargs=setenv bootargs console=${console},${baudrate} " \
"root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp" \
"\0" \
- "nfsboot=run netargs; dhcp ${loadaddr} ${kernel_image}; " \
+ "nfsboot=run netargs; dhcp ${loadaddr} ${boot_file}; " \
"tftp ${fdt_addr} verdin/${fdtfile}; " \
"booti ${loadaddr} - ${fdt_addr}\0" \
"setup=setenv setupargs console=${console},${baudrate} " \
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
/* USDHC */
-#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#endif /*_VERDIN_IMX8MM_H */
+#endif /* __VERDIN_IMX8MM_H */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 1
-#define CONFIG_FEC_MXC
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE RMII
#define CONFIG_FEC_MXC_PHYADDR 0
/* USB device */
/* Ethernet Hardware */
-#define CONFIG_MACB
#define CONFIG_RMII
#define CONFIG_NET_RETRY_COUNT 20
#define CONFIG_MACB_SEARCH_PHY
func(MMC, mmc, 1) \
#ifndef CONFIG_TPL_BUILD
-
-#define CONFIG_SPL_OS_BOOT
-
/* Falcon Mode */
#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args"
#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
"fi; " \
"fi"
-#define CONFIG_SYS_HZ 1000
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
* High Level Configuration Options (easy to change)
*/
-#define CONFIG_DISPLAY_BOARDINFO_LATE
-
/*
* NS16550 Configuration
*/
#include <asm/arch/config.h>
-/*
- * Other required minimal configurations
- */
-#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
-
/* Keep device tree and initrd in low memory so the kernel can access them */
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0x10000000\0" \
#endif
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_DFU)
-# define CONFIG_SPL_ENV_SUPPORT
# define CONFIG_SPL_HASH
# define CONFIG_ENV_MAX_ENTRIES 10
#endif
/* Miscellaneous configurable options */
-#define CONFIG_SYS_HZ 1000
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_SIZE (128 << 20)
#define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_FEC_MXC
#define CONFIG_FEC_ENET_DEV 0
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x0
fdt_addr_t devfdt_get_addr_index(const struct udevice *dev, int index);
/**
+ * devfdt_get_addr_index_ptr() - Return indexed pointer to the address of the
+ * reg property of a device
+ *
+ * @dev: Pointer to a device
+ * @index: the 'reg' property can hold a list of <addr, size> pairs
+ * and @index is used to select which one is required
+ *
+ * @return Pointer to addr, or NULL if there is no such property
+ */
+void *devfdt_get_addr_index_ptr(const struct udevice *dev, int index);
+
+/**
* devfdt_get_addr_size_index() - Get the indexed reg property of a device
*
* Returns the address and size specified in the 'reg' property of a device.
node = ofnode_next_subnode(node))
/**
+ * ofnode_for_each_compatible_node() - iterate over all nodes with a given
+ * compatible string
+ *
+ * @node: child node (ofnode, lvalue)
+ * @compat: compatible string to match
+ *
+ * This is a wrapper around a for loop and is used like so:
+ *
+ * ofnode node;
+ *
+ * ofnode_for_each_compatible_node(node, parent, compatible) {
+ * Use node
+ * ...
+ * }
+ *
+ * Note that this is implemented as a macro and @node is used as
+ * iterator in the loop.
+ */
+#define ofnode_for_each_compatible_node(node, compat) \
+ for (node = ofnode_by_compatible(ofnode_null(), compat); \
+ ofnode_valid(node); \
+ node = ofnode_by_compatible(node, compat))
+
+/**
* ofnode_get_child_count() - get the child count of a ofnode
*
* @node: valid node to get its child count
fdt_addr_t dev_read_addr_index(const struct udevice *dev, int index);
/**
+ * dev_read_addr_index_ptr() - Get the indexed reg property of a device
+ * as a pointer
+ *
+ * @dev: Device to read from
+ * @index: the 'reg' property can hold a list of <addr, size> pairs
+ * and @index is used to select which one is required
+ *
+ * @return pointer or NULL if not found
+ */
+void *dev_read_addr_index_ptr(const struct udevice *dev, int index);
+
+/**
* dev_read_addr_size_index() - Get the indexed reg property of a device
*
* @dev: Device to read from
return devfdt_get_addr_index(dev, index);
}
+static inline void *dev_read_addr_index_ptr(const struct udevice *dev,
+ int index)
+{
+ return devfdt_get_addr_index_ptr(dev, index);
+}
+
static inline fdt_addr_t dev_read_addr_size_index(const struct udevice *dev,
int index,
fdt_size_t *size)
UCLASS_I2C_MUX, /* I2C multiplexer */
UCLASS_I2S, /* I2S bus */
UCLASS_IDE, /* IDE device */
+ UCLASS_IOMMU, /* IOMMU */
UCLASS_IRQ, /* Interrupt controller */
UCLASS_KEYBOARD, /* Keyboard input device */
UCLASS_LED, /* Light-emitting diode (LED) */
/* Dump out a list of drivers with static platform data */
void dm_dump_static_driver_info(void);
-#endif
-
#if CONFIG_IS_ENABLED(OF_PLATDATA_INST) && CONFIG_IS_ENABLED(READ_ONLY)
void *dm_priv_to_rw(void *priv);
#else
return priv;
}
#endif
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef DT_CLOCK_FSL_QORIQ_CLOCKGEN_H
+#define DT_CLOCK_FSL_QORIQ_CLOCKGEN_H
+
+#define QORIQ_CLK_SYSCLK 0
+#define QORIQ_CLK_CMUX 1
+#define QORIQ_CLK_HWACCEL 2
+#define QORIQ_CLK_FMAN 3
+#define QORIQ_CLK_PLATFORM_PLL 4
+#define QORIQ_CLK_CORECLK 5
+
+#define QORIQ_CLK_PLL_DIV(x) ((x) - 1)
+
+#endif /* DT_CLOCK_FSL_QORIQ_CLOCKGEN_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_APPLE_AIC_H
+#define _DT_BINDINGS_INTERRUPT_CONTROLLER_APPLE_AIC_H
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#define AIC_IRQ 0
+#define AIC_FIQ 1
+
+#define AIC_TMR_HV_PHYS 0
+#define AIC_TMR_HV_VIRT 1
+#define AIC_TMR_GUEST_PHYS 2
+#define AIC_TMR_GUEST_VIRT 3
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ OR MIT */
+/*
+ * This header provides constants for Apple pinctrl bindings.
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_APPLE_H
+#define _DT_BINDINGS_PINCTRL_APPLE_H
+
+#define APPLE_PINMUX(pin, func) ((pin) | ((func) << 16))
+#define APPLE_PIN(pinmux) ((pinmux) & 0xffff)
+#define APPLE_FUNC(pinmux) ((pinmux) >> 16)
+
+#endif /* _DT_BINDINGS_PINCTRL_APPLE_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ */
+#ifndef __DT_BINDINGS_SPMI_H
+#define __DT_BINDINGS_SPMI_H
+
+#define SPMI_USID 0
+#define SPMI_GSID 1
+
+#endif
*
* @return pointer to EFI system table
*/
-
struct efi_system_table *efi_get_sys_table(void);
/**
+ * efi_get_boot() - Get access to the EFI boot services table
+ *
+ * @return pointer to EFI boot services table
+ */
+struct efi_boot_services *efi_get_boot(void);
+
+/**
* efi_get_ram_base() - Find the base of RAM
*
* This is used when U-Boot is built as an EFI application.
struct efi_device_path **device_path,
efi_handle_t *device);
efi_status_t (EFIAPI *install_configuration_table)(
- efi_guid_t *guid, void *table);
+ const efi_guid_t *guid, void *table);
efi_status_t (EFIAPI *load_image)(bool boot_policiy,
efi_handle_t parent_image,
#define EFI_INITRD_MEDIA_GUID \
EFI_GUID(0x5568e427, 0x68fc, 0x4f3d, \
0xac, 0x74, 0xca, 0x55, 0x52, 0x31, 0xcc, 0x68)
+extern const efi_guid_t efi_lf2_initrd_guid;
struct efi_initrd_dp {
struct efi_device_path_vendor vendor;
extern const efi_guid_t efi_guid_firmware_management_protocol;
/* GUID for the ESRT */
extern const efi_guid_t efi_esrt_guid;
+/* GUID of the SMBIOS table */
+extern const efi_guid_t smbios_guid;
extern char __efi_runtime_start[], __efi_runtime_stop[];
extern char __efi_runtime_rel_start[], __efi_runtime_rel_stop[];
void efi_variables_boot_exit_notify(void);
efi_status_t efi_tcg2_notify_exit_boot_services_failed(void);
/* Measure efi application invocation */
-efi_status_t efi_tcg2_measure_efi_app_invocation(void);
+efi_status_t efi_tcg2_measure_efi_app_invocation(struct efi_loaded_image_obj *handle);
/* Measure efi application exit */
efi_status_t efi_tcg2_measure_efi_app_exit(void);
/* Called by bootefi to initialize root node */
#define efi_size_in_pages(size) (((size) + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT)
/* Generic EFI memory allocator, call this to get memory */
void *efi_alloc(uint64_t len, int memory_type);
+/* Allocate pages on the specified alignment */
+void *efi_alloc_aligned_pages(u64 len, int memory_type, size_t align);
/* More specific EFI memory allocator, called by EFI payloads */
efi_status_t efi_allocate_pages(enum efi_allocate_type type,
enum efi_memory_type memory_type,
u64 *remaining_variable_storage_size,
u64 *maximum_variable_size);
-void *efi_get_var(u16 *name, const efi_guid_t *vendor, efi_uintn_t *size);
+void *efi_get_var(const u16 *name, const efi_guid_t *vendor, efi_uintn_t *size);
/*
* See section 3.1.3 in the v2.7 UEFI spec for more details on
};
struct efi_device_path *efi_dp_from_lo(struct efi_load_option *lo,
- efi_uintn_t *size, efi_guid_t guid);
+ const efi_guid_t *guid);
struct efi_device_path *efi_dp_concat(const struct efi_device_path *dp1,
const struct efi_device_path *dp2);
+struct efi_device_path *search_gpt_dp_node(struct efi_device_path *device_path);
efi_status_t efi_deserialize_load_option(struct efi_load_option *lo, u8 *data,
efi_uintn_t *size);
unsigned long efi_serialize_load_option(struct efi_load_option *lo, u8 **data);
u8 variable_data[1];
};
+/**
+ * struct tdUEFI_HANDOFF_TABLE_POINTERS2 - event log structure of SMBOIS tables
+ * @table_description_size: size of table description
+ * @table_description: table description
+ * @number_of_tables: number of uefi configuration table
+ * @table_entry: uefi configuration table entry
+ */
+#define SMBIOS_HANDOFF_TABLE_DESC "SmbiosTable"
+struct smbios_handoff_table_pointers2 {
+ u8 table_description_size;
+ u8 table_description[sizeof(SMBIOS_HANDOFF_TABLE_DESC)];
+ u64 number_of_tables;
+ struct efi_configuration_table table_entry[];
+} __packed;
+
+/**
+ * struct tdUEFI_GPT_DATA - event log structure of industry standard tables
+ * @uefi_partition_header: gpt partition header
+ * @number_of_partitions: the number of partition
+ * @partitions: partition entries
+ */
+struct efi_gpt_data {
+ gpt_header uefi_partition_header;
+ u64 number_of_partitions;
+ gpt_entry partitions[];
+} __packed;
+
struct efi_tcg2_protocol {
efi_status_t (EFIAPI * get_capability)(struct efi_tcg2_protocol *this,
struct efi_tcg2_boot_service_capability *capability);
* @timep: authentication time (seconds since start of epoch)
* Return: status code
*/
-efi_status_t efi_get_variable_int(u16 *variable_name, const efi_guid_t *vendor,
+efi_status_t efi_get_variable_int(const u16 *variable_name,
+ const efi_guid_t *vendor,
u32 *attributes, efi_uintn_t *data_size,
void *data, u64 *timep);
* @ro_check: check the read only read only bit in attributes
* Return: status code
*/
-efi_status_t efi_set_variable_int(u16 *variable_name, const efi_guid_t *vendor,
+efi_status_t efi_set_variable_int(const u16 *variable_name,
+ const efi_guid_t *vendor,
u32 attributes, efi_uintn_t data_size,
const void *data, bool ro_check);
* @time: time of authentication (as seconds since start of epoch)
* Result: status code
*/
-efi_status_t efi_var_mem_ins(u16 *variable_name,
+efi_status_t efi_var_mem_ins(const u16 *variable_name,
const efi_guid_t *vendor, u32 attributes,
const efi_uintn_t size1, const void *data1,
const efi_uintn_t size2, const void *data2,
* @guid: guid of UEFI variable
* Return: identifier for authentication related variables
*/
-enum efi_auth_var_type efi_auth_var_get_type(u16 *name, const efi_guid_t *guid);
+enum efi_auth_var_type efi_auth_var_get_type(const u16 *name,
+ const efi_guid_t *guid);
+
+/**
+ * efi_auth_var_get_guid() - get the predefined GUID for a variable name
+ *
+ * @name: name of UEFI variable
+ * Return: guid of UEFI variable
+ */
+const efi_guid_t *efi_auth_var_get_guid(const u16 *name);
/**
* efi_get_next_variable_name_mem() - Runtime common code across efi variable
* Return: status code
*/
efi_status_t __efi_runtime
-efi_get_variable_mem(u16 *variable_name, const efi_guid_t *vendor, u32 *attributes,
- efi_uintn_t *data_size, void *data, u64 *timep);
+efi_get_variable_mem(const u16 *variable_name, const efi_guid_t *vendor,
+ u32 *attributes, efi_uintn_t *data_size, void *data,
+ u64 *timep);
/**
* efi_get_variable_runtime() - runtime implementation of GetVariable()
void env_relocate(void);
/**
- * env_match() - Match a name / name=value pair
- *
- * This is used prior to relocation for finding envrionment variables
- *
- * @name: A simple 'name', or a 'name=value' pair.
- * @index: The environment index for a 'name2=value2' pair.
- * @return index for the value if the names match, else -1.
- */
-int env_match(unsigned char *name, int index);
-
-/**
* env_get() - Look up the value of an environment variable
*
* In U-Boot proper this can be called before relocation (which is when the
* support reading the value (slowly) and some will not.
*
* @varname: Variable to look up
- * @return value of variable, or NULL if not found
+ * @return actual length of the variable value excluding the terminating
+ * NULL-byte, or -1 if the variable is not found
*/
int env_get_f(const char *name, char *buf, unsigned int len);
void env_set_default(const char *s, int flags);
/**
- * env_get_char() - Get a character from the early environment
- *
- * This reads from the pre-relocation environment
- *
- * @index: Index of character to read (0 = first)
- * @return character read, or -ve on error
- */
-int env_get_char(int index);
-
-/**
* env_reloc() - Relocate the 'env' sub-commands
*
* This is used for those unfortunate archs with crappy toolchains
#elif defined(DEFAULT_ENV_INSTANCE_STATIC)
static char default_environment[] = {
#elif defined(DEFAULT_ENV_IS_RW)
-uchar default_environment[] = {
+char default_environment[] = {
#else
-const uchar default_environment[] = {
+const char default_environment[] = {
#endif
#ifndef CONFIG_USE_DEFAULT_ENV_FILE
#ifdef CONFIG_ENV_CALLBACK_LIST_DEFAULT
}
#endif
};
+
+#if !defined(USE_HOSTCC) && !defined(DEFAULT_ENV_INSTANCE_EMBEDDED)
+#include <env_internal.h>
+static_assert(sizeof(default_environment) <= ENV_SIZE,
+ "Default environment is too large");
+#endif
# error "is set"
# endif
extern unsigned long nand_env_oob_offset;
-# define CONFIG_ENV_OFFSET nand_env_oob_offset
# endif /* CONFIG_ENV_OFFSET_OOB */
#endif /* CONFIG_ENV_IS_IN_NAND */
#endif /* ENV_IS_EMBEDDED */
#ifdef DEFAULT_ENV_IS_RW
-extern unsigned char default_environment[];
+extern char default_environment[];
#else
-extern const unsigned char default_environment[];
+extern const char default_environment[];
#endif
#ifndef DO_DEPS_ONLY
* Board-specific FDT initialization. Returns the address to a device tree blob.
* Called when CONFIG_OF_BOARD is defined, or if CONFIG_OF_SEPARATE is defined
* and the board implements it.
+ *
+ * @err internal error code if we fail to setup a DTB
*/
-void *board_fdt_blob_setup(void);
+void *board_fdt_blob_setup(int *err);
/*
* Decode the size of memory
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2014 Freescale Semiconductor
+ * Copyright 2021 NXP
*/
#ifndef __FSL_MC_H__
u32 reg_error[];
};
+struct log_header {
+ u32 magic_word;
+ char reserved[4];
+ u32 buf_start;
+ u32 buf_length;
+ u32 last_byte;
+};
+
void fdt_fsl_mc_fixup_iommu_map_entry(void *blob);
int get_mc_boot_status(void);
int get_dpl_apply_status(void);
#define ESDHC_STROBE_DLL_CTRL_RESET BIT(1)
#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT 0x7
#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3
+#define ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT (4 << 20)
#define ESDHC_STROBE_DLL_STATUS 0x74
#define ESDHC_STROBE_DLL_STS_REF_LOCK BIT(1)
const char *keydir; /* Directory conaining keys */
const char *keyname; /* Name of key to use */
const char *keyfile; /* Filename of private or public key */
- void *fit; /* Pointer to FIT blob */
+ const void *fit; /* Pointer to FIT blob */
int node_offset; /* Offset of signature node */
const char *name; /* Algorithm name */
struct checksum_algo *checksum; /* Checksum algorithm information */
--- /dev/null
+#ifndef _IOMMU_H
+#define _IOMMU_H
+
+struct udevice;
+
+#if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) && \
+ CONFIG_IS_ENABLED(IOMMU)
+int dev_iommu_enable(struct udevice *dev);
+#else
+static inline int dev_iommu_enable(struct udevice *dev)
+{
+ return 0;
+}
+#endif
+
+#endif
u_long retries;
unsigned dev;
unsigned cell;
- void (*callback) (struct erase_info *self);
u_long priv;
u_char state;
struct erase_info *next;
#endif
void *mtd_kmalloc_up_to(const struct mtd_info *mtd, size_t *size);
-#ifdef CONFIG_MTD_PARTITIONS
-void mtd_erase_callback(struct erase_info *instr);
-#else
-static inline void mtd_erase_callback(struct erase_info *instr)
-{
- if (instr->callback)
- instr->callback(instr);
-}
-#endif
-
static inline int mtd_is_bitflip(int err) {
return err == -EUCLEAN;
}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2003
- * Orbacom Systems, Inc.
- */
-
-#ifndef __LYNXKDI_H__
-#define __LYNXKDI_H__
-
-
-/* Boot parameter struct passed to kernel
- */
-typedef struct lynxos_bootparms_t {
- uint8_t rsvd1[2]; /* Reserved */
- uint8_t ethaddr[6]; /* Ethernet address */
- uint16_t flags; /* Boot flags */
- uint32_t rate; /* System frequency */
- uint32_t clock_ref; /* Time reference */
- uint32_t dramsz; /* DRAM size */
- uint32_t rsvd2; /* Reserved */
-} lynxos_bootparms_t;
-
-
-#endif /* __LYNXKDI_H__ */
instr.mtd = info;
instr.addr = off;
instr.len = size;
- instr.callback = 0;
return mtd_erase(info, &instr);
}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __PXE_UTILS_H
+#define __PXE_UTILS_H
+
+#include <linux/list.h>
+
+/*
+ * A note on the pxe file parser.
+ *
+ * We're parsing files that use syslinux grammar, which has a few quirks.
+ * String literals must be recognized based on context - there is no
+ * quoting or escaping support. There's also nothing to explicitly indicate
+ * when a label section completes. We deal with that by ending a label
+ * section whenever we see a line that doesn't include.
+ *
+ * As with the syslinux family, this same file format could be reused in the
+ * future for non pxe purposes. The only action it takes during parsing that
+ * would throw this off is handling of include files. It assumes we're using
+ * pxe, and does a tftp download of a file listed as an include file in the
+ * middle of the parsing operation. That could be handled by refactoring it to
+ * take a 'include file getter' function.
+ */
+
+/*
+ * Describes a single label given in a pxe file.
+ *
+ * Create these with the 'label_create' function given below.
+ *
+ * name - the name of the menu as given on the 'menu label' line.
+ * kernel - the path to the kernel file to use for this label.
+ * append - kernel command line to use when booting this label
+ * initrd - path to the initrd to use for this label.
+ * attempted - 0 if we haven't tried to boot this label, 1 if we have.
+ * localboot - 1 if this label specified 'localboot', 0 otherwise.
+ * list - lets these form a list, which a pxe_menu struct will hold.
+ */
+struct pxe_label {
+ char num[4];
+ char *name;
+ char *menu;
+ char *kernel;
+ char *config;
+ char *append;
+ char *initrd;
+ char *fdt;
+ char *fdtdir;
+ char *fdtoverlays;
+ int ipappend;
+ int attempted;
+ int localboot;
+ int localboot_val;
+ struct list_head list;
+};
+
+/*
+ * Describes a pxe menu as given via pxe files.
+ *
+ * title - the name of the menu as given by a 'menu title' line.
+ * default_label - the name of the default label, if any.
+ * bmp - the bmp file name which is displayed in background
+ * timeout - time in tenths of a second to wait for a user key-press before
+ * booting the default label.
+ * prompt - if 0, don't prompt for a choice unless the timeout period is
+ * interrupted. If 1, always prompt for a choice regardless of
+ * timeout.
+ * labels - a list of labels defined for the menu.
+ */
+struct pxe_menu {
+ char *title;
+ char *default_label;
+ char *bmp;
+ int timeout;
+ int prompt;
+ struct list_head labels;
+};
+
+struct pxe_context;
+typedef int (*pxe_getfile_func)(struct pxe_context *ctx, const char *file_path,
+ char *file_addr, ulong *filesizep);
+
+/**
+ * struct pxe_context - context information for PXE parsing
+ *
+ * @cmdtp: Pointer to command table to use when calling other commands
+ * @getfile: Function called by PXE to read a file
+ * @userdata: Data the caller requires for @getfile
+ * @allow_abs_path: true to allow absolute paths
+ * @bootdir: Directory that files are loaded from ("" if no directory). This is
+ * allocated
+ * @pxe_file_size: Size of the PXE file
+ */
+struct pxe_context {
+ struct cmd_tbl *cmdtp;
+ /**
+ * getfile() - read a file
+ *
+ * @ctx: PXE context
+ * @file_path: Path to the file
+ * @file_addr: String containing the hex address to put the file in
+ * memory
+ * @filesizep: Returns the file size in bytes
+ * Return 0 if OK, -ve on error
+ */
+ pxe_getfile_func getfile;
+
+ void *userdata;
+ bool allow_abs_path;
+ char *bootdir;
+ ulong pxe_file_size;
+};
+
+/**
+ * destroy_pxe_menu() - Destroy an allocated pxe structure
+ *
+ * Free the memory used by a pxe_menu and its labels
+ *
+ * @cfg: Config to destroy, previous returned from parse_pxefile()
+ */
+void destroy_pxe_menu(struct pxe_menu *cfg);
+
+/**
+ * get_pxe_file() - Read a file
+ *
+ * Retrieve the file at 'file_path' to the locate given by 'file_addr'. If
+ * 'bootfile' was specified in the environment, the path to bootfile will be
+ * prepended to 'file_path' and the resulting path will be used.
+ *
+ * @ctx: PXE context
+ * @file_path: Path to file
+ * @file_addr: Address to place file
+ * Returns 1 on success, or < 0 for error
+ */
+int get_pxe_file(struct pxe_context *ctx, const char *file_path,
+ ulong file_addr);
+
+/**
+ * get_pxelinux_path() - Read a file from the same place as pxelinux.cfg
+ *
+ * Retrieves a file in the 'pxelinux.cfg' folder. Since this uses get_pxe_file()
+ * to do the hard work, the location of the 'pxelinux.cfg' folder is generated
+ * from the bootfile path, as described in get_pxe_file().
+ *
+ * @ctx: PXE context
+ * @file: Relative path to file
+ * @pxefile_addr_r: Address to load file
+ * Returns 1 on success or < 0 on error.
+ */
+int get_pxelinux_path(struct pxe_context *ctx, const char *file,
+ ulong pxefile_addr_r);
+
+/**
+ * handle_pxe_menu() - Boot the system as prescribed by a pxe_menu.
+ *
+ * Use the menu system to either get the user's choice or the default, based
+ * on config or user input. If there is no default or user's choice,
+ * attempted to boot labels in the order they were given in pxe files.
+ * If the default or user's choice fails to boot, attempt to boot other
+ * labels in the order they were given in pxe files.
+ *
+ * If this function returns, there weren't any labels that successfully
+ * booted, or the user interrupted the menu selection via ctrl+c.
+ *
+ * @ctx: PXE context
+ * @cfg: PXE menu
+ */
+void handle_pxe_menu(struct pxe_context *ctx, struct pxe_menu *cfg);
+
+/**
+ * parse_pxefile() - Parsing a pxe file
+ *
+ * This is only used for the top-level file.
+ *
+ * @ctx: PXE context (provided by the caller)
+ * Returns NULL if there is an error, otherwise, returns a pointer to a
+ * pxe_menu struct populated with the results of parsing the pxe file (and any
+ * files it includes). The resulting pxe_menu struct can be free()'d by using
+ * the destroy_pxe_menu() function.
+ */
+struct pxe_menu *parse_pxefile(struct pxe_context *ctx, ulong menucfg);
+
+/**
+ * format_mac_pxe() - Convert a MAC address to PXE format
+ *
+ * Convert an ethaddr from the environment to the format used by pxelinux
+ * filenames based on mac addresses. Convert's ':' to '-', and adds "01-" to
+ * the beginning of the ethernet address to indicate a hardware type of
+ * Ethernet. Also converts uppercase hex characters into lowercase, to match
+ * pxelinux's behavior.
+ *
+ * @outbuf: Buffer to hold the output (must hold 22 bytes)
+ * @outbuf_len: Length of buffer
+ * Returns 1 for success, -ENOENT if 'ethaddr' is undefined in the
+ * environment, or some other value < 0 on error.
+ */
+int format_mac_pxe(char *outbuf, size_t outbuf_len);
+
+/**
+ * pxe_setup_ctx() - Setup a new PXE context
+ *
+ * @ctx: Context to set up
+ * @cmdtp: Command table entry which started this action
+ * @getfile: Function to call to read a file
+ * @userdata: Data the caller requires for @getfile - stored in ctx->userdata
+ * @allow_abs_path: true to allow absolute paths
+ * @bootfile: Bootfile whose directory loaded files are relative to, NULL if
+ * none
+ * @return 0 if OK, -ENOMEM if out of memory, -E2BIG if bootfile is larger than
+ * MAX_TFTP_PATH_LEN bytes
+ */
+int pxe_setup_ctx(struct pxe_context *ctx, struct cmd_tbl *cmdtp,
+ pxe_getfile_func getfile, void *userdata,
+ bool allow_abs_path, const char *bootfile);
+
+/**
+ * pxe_destroy_ctx() - Destroy a PXE context
+ *
+ * @ctx: Context to destroy
+ */
+void pxe_destroy_ctx(struct pxe_context *ctx);
+
+/**
+ * pxe_process() - Process a PXE file through to boot
+ *
+ * @ctx: PXE context created with pxe_setup_ctx()
+ * @pxefile_addr_r: Address to load file
+ * @prompt: Force a prompt for the user
+ */
+int pxe_process(struct pxe_context *ctx, ulong pxefile_addr_r, bool prompt);
+
+/**
+ * pxe_get_file_size() - Read the value of the 'filesize' environment variable
+ *
+ * @sizep: Place to put the value
+ * @return 0 if OK, -ENOENT if no such variable, -EINVAL if format is invalid
+ */
+int pxe_get_file_size(ulong *sizep);
+
+/**
+ * pxe_get() - Get the PXE file from the server
+ *
+ * This tries various filenames to obtain a PXE file
+ *
+ * @pxefile_addr_r: Address to put file
+ * @bootdirp: Returns the boot filename, or NULL if none. This is the 'bootfile'
+ * option provided by the DHCP server. If none, returns NULL. For example,
+ * "rpi/info", which indicates that all files should be fetched from the
+ * "rpi/" subdirectory
+ * @sizep: Size of the PXE file (not bootfile)
+ */
+int pxe_get(ulong pxefile_addr_r, char **bootdirp, ulong *sizep);
+
+#endif /* __PXE_UTILS_H */
/**
* struct scmi_clk_state_in - Message payload for CLOCK_RATE_SET command
- * @clock_id: SCMI clock ID
* @flags: Flags for the clock rate set request
+ * @clock_id: SCMI clock ID
* @rate_lsb: 32bit LSB of the clock rate in Hertz
* @rate_msb: 32bit MSB of the clock rate in Hertz
*/
struct scmi_clk_rate_set_in {
- u32 clock_id;
u32 flags;
+ u32 clock_id;
u32 rate_lsb;
u32 rate_msb;
};
#define SDHCI_CARD_STATE_STABLE BIT(17)
#define SDHCI_CARD_DETECT_PIN_LEVEL BIT(18)
#define SDHCI_WRITE_PROTECT BIT(19)
+#define SDHCI_DATA_LVL_MASK 0x00F00000
+#define SDHCI_DATA_0_LVL_MASK BIT(20)
#define SDHCI_HOST_CONTROL 0x28
#define SDHCI_CTRL_LED BIT(0)
*
* @header: pointer to struct smbios_header
* @index: string index
- * @return: NULL or a valid const char pointer
+ * @return: NULL or a valid char pointer
*/
-const char *smbios_string(const struct smbios_header *header, int index);
+char *smbios_string(const struct smbios_header *header, int index);
/**
* smbios_update_version() - Update the version string
*/
int smbios_update_version_full(void *smbios_tab, const char *version);
+/**
+ * smbios_prepare_measurement() - Update smbios table for the measurement
+ *
+ * TCG specification requires to measure static configuration information.
+ * This function clear the device dependent parameters such as
+ * serial number for the measurement.
+ *
+ * @entry: pointer to a struct smbios_entry
+ * @header: pointer to a struct smbios_header
+ */
+void smbios_prepare_measurement(const struct smbios_entry *entry,
+ struct smbios_header *header);
+
#endif /* _SMBIOS_H_ */
struct mtd_info *mtd = &flash->mtd;
size_t retlen;
+ if (!len)
+ return 0;
+
return mtd->_read(mtd, offset, len, &retlen, buf);
}
struct mtd_info *mtd = &flash->mtd;
size_t retlen;
+ if (!len)
+ return 0;
+
return mtd->_write(mtd, offset, len, &retlen, buf);
}
return -EINVAL;
}
+ if (!len)
+ return 0;
+
memset(&instr, 0, sizeof(instr));
instr.addr = offset;
instr.len = len;
bool spl_load_simple_fit_skip_processing(void);
/**
+ * spl_load_simple_fit_fix_load() - Hook to make fixes
+ * after fit image header is loaded
+ *
+ * Returns pointer to fit
+ */
+void *spl_load_simple_fit_fix_load(const void *fit);
+
+/**
* spl_load_simple_fit() - Loads a fit image from a device.
* @spl_image: Image description to set up
* @info: Structure containing the information required to load data.
void __noreturn jump_to_image_linux(struct spl_image_info *spl_image);
/**
+ * jump_to_image_linux() - Jump to OP-TEE OS from SPL
+ *
+ * This jumps into OP-TEE OS using the information in @spl_image.
+ *
+ * @spl_image: Image description to set up
+ */
+void __noreturn jump_to_image_optee(struct spl_image_info *spl_image);
+
+/**
* spl_start_uboot() - Check if SPL should start the kernel or U-Boot
*
* This is called by the various SPL loaders to determine whether the board
* @arg2: device tree address, (ARMv7 standard bootarg #2)
* @arg3: non-secure entry address (ARMv7 bootarg #0)
*/
-void spl_optee_entry(void *arg0, void *arg1, void *arg2, void *arg3);
+void __noreturn spl_optee_entry(void *arg0, void *arg1, void *arg2, void *arg3);
/**
* spl_invoke_opensbi - boot using a RISC-V OpenSBI image
struct udevice;
+/**
+ * enum sysreset_t - system reset types
+ */
enum sysreset_t {
- SYSRESET_WARM, /* Reset CPU, keep GPIOs active */
- SYSRESET_COLD, /* Reset CPU and GPIOs */
- SYSRESET_POWER, /* Reset PMIC (remove and restore power) */
- SYSRESET_POWER_OFF, /* Turn off power */
-
+ /** @SYSRESET_WARM: reset CPU, keep GPIOs active */
+ SYSRESET_WARM,
+ /** @SYSRESET_COLD: reset CPU and GPIOs */
+ SYSRESET_COLD,
+ /** @SYSRESET_POWER: reset PMIC (remove and restore power) */
+ SYSRESET_POWER,
+ /** @SYSRESET_POWER_OFF: turn off power */
+ SYSRESET_POWER_OFF,
+ /** @SYSRESET_COUNT: number of available reset types */
SYSRESET_COUNT,
};
+/**
+ * struct sysreset_ops - operations of system reset drivers
+ */
struct sysreset_ops {
/**
- * request() - request a sysreset of the given type
+ * @request: request a sysreset of the given type
*
* Note that this function may return before the reset takes effect.
*
+ * @dev: Device to be used for system reset
* @type: Reset type to request
- * @return -EINPROGRESS if the reset has been started and
- * will complete soon, -EPROTONOSUPPORT if not supported
- * by this device, 0 if the reset has already happened
- * (in which case this method will not actually return)
+ * Return:
+ * -EINPROGRESS if the reset has been started and
+ * will complete soon, -EPROTONOSUPPORT if not supported
+ * by this device, 0 if the reset has already happened
+ * (in which case this method will not actually return)
*/
int (*request)(struct udevice *dev, enum sysreset_t type);
/**
- * get_status() - get printable reset status information
+ * @get_status: get printable reset status information
*
* @dev: Device to check
* @buf: Buffer to receive the textual reset information
* @size: Size of the passed buffer
- * @return 0 if OK, -ve on error
+ * Return: 0 if OK, -ve on error
*/
int (*get_status)(struct udevice *dev, char *buf, int size);
/**
- * get_last() - get information on the last reset
+ * @get_last: get information on the last reset
*
* @dev: Device to check
- * @return last reset state (enum sysreset_t) or -ve error
+ * Return: last reset state (enum :enum:`sysreset_t`) or -ve error
*/
int (*get_last)(struct udevice *dev);
};
/**
* sysreset_request() - request a sysreset
*
+ * @dev: Device to be used for system reset
* @type: Reset type to request
- * @return 0 if OK, -EPROTONOSUPPORT if not supported by this device
+ * Return: 0 if OK, -EPROTONOSUPPORT if not supported by this device
*/
int sysreset_request(struct udevice *dev, enum sysreset_t type);
* @dev: Device to check
* @buf: Buffer to receive the textual reset information
* @size: Size of the passed buffer
- * @return 0 if OK, -ve on error
+ * Return: 0 if OK, -ve on error
*/
int sysreset_get_status(struct udevice *dev, char *buf, int size);
* sysreset_get_last() - get information on the last reset
*
* @dev: Device to check
- * @return last reset state (enum sysreset_t) or -ve error
+ * Return: last reset state (enum sysreset_t) or -ve error
*/
int sysreset_get_last(struct udevice *dev);
* If this function fails to reset, it will display a message and halt
*
* @type: Reset type to request
- * @return -EINPROGRESS if a reset is in progress, -ENOSYS if not available
+ * Return: -EINPROGRESS if a reset is in progress, -ENOSYS if not available
*/
int sysreset_walk(enum sysreset_t type);
*
* If no device prives the information, this function returns -ENOENT
*
- * @return last reset state (enum sysreset_t) or -ve error
+ * Return: last reset state (enum sysreset_t) or -ve error
*/
int sysreset_get_last_walk(void);
*
* This calls sysreset_walk(). If it returns, indicating that reset is not
* supported, it prints a message and halts.
+ *
+ * @type: Reset type to request
*/
void sysreset_walk_halt(enum sysreset_t type);
*/
void reset_cpu(void);
+/**
+ * sysreset_register_wdt() - register a watchdog for use with sysreset
+ *
+ * This registers the given watchdog timer to be used to reset the system.
+ *
+ * @dev: WDT device
+ * @return: 0 if OK, -errno if error
+ */
+int sysreset_register_wdt(struct udevice *dev);
+
#endif
TPM_STS_DATA_EXPECT = 1 << 3,
TPM_STS_SELF_TEST_DONE = 1 << 2,
TPM_STS_RESPONSE_RETRY = 1 << 1,
+ TPM_STS_READ_ZERO = 0x23
};
enum {
*/
u32 tpm2_disable_platform_hierarchy(struct udevice *dev);
+/**
+ * submit user specified data to the TPM and get response
+ *
+ * @dev TPM device
+ * @sendbuf: Buffer of the data to send
+ * @recvbuf: Buffer to save the response to
+ * @recv_size: Pointer to the size of the response buffer
+ *
+ * @return code of the operation
+ */
+u32 tpm2_submit_command(struct udevice *dev, const u8 *sendbuf,
+ u8 *recvbuf, size_t *recv_size);
+
#endif /* __TPM_V2_H */
* See the vsprintf() documentation for format string extensions over C99.
*/
int vsprintf(char *buf, const char *fmt, va_list args);
-char *simple_itoa(ulong i);
+
+/**
+ * simple_itoa() - convert an unsigned integer to a string
+ *
+ * This returns a static string containing the decimal representation of the
+ * given value. The returned value may be overwritten by other calls to other
+ * simple_... functions, so should be used immediately
+ *
+ * @val: Value to convert
+ * @return string containing the decimal representation of @val
+ */
+char *simple_itoa(ulong val);
+
+/**
+ * simple_xtoa() - convert an unsigned integer to a hex string
+ *
+ * This returns a static string containing the hexadecimal representation of the
+ * given value. The returned value may be overwritten by other calls to other
+ * simple_... functions, so should be used immediately
+ *
+ * @val: Value to convert
+ * @return string containing the hexecimal representation of @val
+ */
+char *simple_xtoa(ulong num);
/**
* Format a string and place it in a buffer
endchoice
-config EFI_RAM_SIZE
- hex "Amount of EFI RAM for U-Boot"
+choice
+ prompt "EFI app 32/64-bit selection"
depends on EFI_APP
- default 0x2000000
help
- Set the amount of EFI RAM which is claimed by U-Boot for its own
- use. U-Boot allocates this from EFI on start-up (along with a few
- other smaller amounts) and it can never be increased after that.
- It is used as the RAM size in with U-Boot.
+ EFI does not support mixing 32-bit and 64-bit modes. This is a
+ significant problem because it means that you must build a stub with
+ the correct type for EFI to load it correctly. If you are using
+ 32-bit EFI, select 32-bit here, else select 64-bit. Failure to do
+ this may produce no error message - it just won't start!
+
+config EFI_APP_32BIT
+ bool "Produce an app for running with 32-bit EFI"
+
+config EFI_APP_64BIT
+ bool "Produce an app for running with 64-bit EFI"
+
+endchoice
choice
- prompt "EFI 32/64-bit selection"
+ prompt "EFI stub 32/64-bit selection"
depends on EFI_STUB
help
EFI does not support mixing 32-bit and 64-bit modes. This is a
bool "Produce a stub for running with 64-bit EFI"
endchoice
+
+config EFI_RAM_SIZE
+ hex "Amount of EFI RAM for U-Boot"
+ depends on EFI_APP
+ default 0x10000000
+ help
+ Set the amount of EFI RAM which is claimed by U-Boot for its own
+ use. U-Boot allocates this from EFI on start-up (along with a few
+ other smaller amounts) and it can never be increased after that.
+ It is used as the RAM size in with U-Boot.
#include <efi_api.h>
/*
+ * Global declaration of gd.
+ *
+ * As we write to it before relocation we have to make sure it is not put into
+ * a .bss section which may overlap a .rela section. Initialization forces it
+ * into a .data section which cannot overlap any .rela section.
+ */
+struct global_data *global_data_ptr = (struct global_data *)~0;
+
+/*
* Unfortunately we cannot access any code outside what is built especially
* for the stub. lib/string.c is already being built for the U-Boot payload
* so it uses the wrong compiler flags. Add our own memset() here.
return global_priv->sys_table;
}
+struct efi_boot_services *efi_get_boot(void)
+{
+ return global_priv->boot;
+}
+
unsigned long efi_get_ram_base(void)
{
return global_priv->ram_base;
}
+int efi_info_get(enum efi_entry_t type, void **datap, int *sizep)
+{
+ return -ENOSYS;
+}
+
static efi_status_t setup_memory(struct efi_priv *priv)
{
struct efi_boot_services *boot = priv->boot;
# object inclusion implicitly depends on it
obj-y += efi_uclass.o
-ifeq ($(CONFIG_BLK)$(CONFIG_PARTITIONS),yy)
+ifeq ($(CONFIG_PARTITIONS),y)
obj-y += efi_block_device.o
endif
# We need EFI_STUB_32BIT to be set on x86_32 with EFI_STUB
depends on !EFI_STUB || !X86 || X86_64 || EFI_STUB_32BIT
depends on BLK
+ depends on DM_ETH || !NET
+ depends on !EFI_APP
default y if !ARM || SYS_CPU = armv7 || SYS_CPU = armv8
select LIB_UUID
select PARTITION_UUIDS
select SHA384
select SHA512
select HASH
+ select SMBIOS_PARSER
help
Provide a EFI_TCG2_PROTOCOL implementation using the TPM hardware
of the platform.
/* GUIDs of the Load File and Load File2 protocols */
const efi_guid_t efi_guid_load_file_protocol = EFI_LOAD_FILE_PROTOCOL_GUID;
const efi_guid_t efi_guid_load_file2_protocol = EFI_LOAD_FILE2_PROTOCOL_GUID;
+/* GUID of the SMBIOS table */
+const efi_guid_t smbios_guid = SMBIOS_TABLE_GUID;
static efi_status_t EFIAPI efi_disconnect_controller(
efi_handle_t controller_handle,
*
* Return: status code
*/
-static efi_status_t EFIAPI efi_install_configuration_table_ext(efi_guid_t *guid,
- void *table)
+static efi_status_t
+EFIAPI efi_install_configuration_table_ext(const efi_guid_t *guid,
+ void *table)
{
EFI_ENTRY("%pUl, %p", guid, table);
return EFI_EXIT(efi_install_configuration_table(guid, table));
if (IS_ENABLED(CONFIG_EFI_TCG2_PROTOCOL)) {
if (image_obj->image_type == IMAGE_SUBSYSTEM_EFI_APPLICATION) {
- ret = efi_tcg2_measure_efi_app_invocation();
+ ret = efi_tcg2_measure_efi_app_invocation(image_obj);
if (ret != EFI_SUCCESS) {
log_warning("tcg2 measurement fails(0x%lx)\n",
ret);
#include <common.h>
#include <efi_loader.h>
#include <efi_variable.h>
+#include <env.h>
+#include <fdtdec.h>
#include <fs.h>
#include <malloc.h>
#include <mapmem.h>
#include <sort.h>
+#include <asm/global_data.h>
#include <crypto/pkcs7.h>
#include <crypto/pkcs7_parser.h>
#include <linux/err.h>
+DECLARE_GLOBAL_DATA_PTR;
+
const efi_guid_t efi_guid_capsule_report = EFI_CAPSULE_REPORT_GUID;
static const efi_guid_t efi_guid_firmware_management_capsule_id =
EFI_FIRMWARE_MANAGEMENT_CAPSULE_ID_GUID;
}
#if defined(CONFIG_EFI_CAPSULE_AUTHENTICATE)
+int efi_get_public_key_data(void **pkey, efi_uintn_t *pkey_len)
+{
+ const void *fdt_blob = gd->fdt_blob;
+ const void *blob;
+ const char *cnode_name = "capsule-key";
+ const char *snode_name = "signature";
+ int sig_node;
+ int len;
+
+ sig_node = fdt_subnode_offset(fdt_blob, 0, snode_name);
+ if (sig_node < 0) {
+ log_err("Unable to get signature node offset\n");
+
+ return -FDT_ERR_NOTFOUND;
+ }
+
+ blob = fdt_getprop(fdt_blob, sig_node, cnode_name, &len);
+
+ if (!blob || len < 0) {
+ log_err("Unable to get capsule-key value\n");
+ *pkey = NULL;
+ *pkey_len = 0;
+
+ return -FDT_ERR_NOTFOUND;
+ }
+
+ *pkey = (void *)blob;
+ *pkey_len = len;
+
+ return 0;
+}
efi_status_t efi_capsule_authenticate(const void *capsule, efi_uintn_t capsule_size,
void **image, efi_uintn_t *image_size)
.guid = U_BOOT_GUID,
};
-#if defined(CONFIG_DM_MMC) && defined(CONFIG_MMC)
+#if defined(CONFIG_MMC)
/*
* Determine if an MMC device is an SD card.
*
return p->sub_type == DEVICE_PATH_SUB_TYPE_INSTANCE_END;
}
-#ifdef CONFIG_DM
/* size of device-path not including END node for device and all parents
* up to the root device.
*/
case UCLASS_ETH:
return dp_size(dev->parent) +
sizeof(struct efi_device_path_mac_addr);
-#ifdef CONFIG_BLK
case UCLASS_BLK:
switch (dev->parent->uclass->uc_drv->id) {
#ifdef CONFIG_IDE
return dp_size(dev->parent) +
sizeof(struct efi_device_path_atapi);
#endif
-#if defined(CONFIG_SCSI) && defined(CONFIG_DM_SCSI)
+#if defined(CONFIG_SCSI)
case UCLASS_SCSI:
return dp_size(dev->parent) +
sizeof(struct efi_device_path_scsi);
#endif
-#if defined(CONFIG_DM_MMC) && defined(CONFIG_MMC)
+#if defined(CONFIG_MMC)
case UCLASS_MMC:
return dp_size(dev->parent) +
sizeof(struct efi_device_path_sd_mmc_path);
default:
return dp_size(dev->parent);
}
-#endif
-#if defined(CONFIG_DM_MMC) && defined(CONFIG_MMC)
+#if defined(CONFIG_MMC)
case UCLASS_MMC:
return dp_size(dev->parent) +
sizeof(struct efi_device_path_sd_mmc_path);
*vdp = ROOT;
return &vdp[1];
}
-#ifdef CONFIG_DM_ETH
+#ifdef CONFIG_NET
case UCLASS_ETH: {
struct efi_device_path_mac_addr *dp =
dp_fill(buf, dev->parent);
return &dp[1];
}
#endif
-#ifdef CONFIG_BLK
case UCLASS_BLK:
switch (dev->parent->uclass->uc_drv->id) {
#ifdef CONFIG_SANDBOX
return &dp[1];
}
#endif
-#if defined(CONFIG_SCSI) && defined(CONFIG_DM_SCSI)
+#if defined(CONFIG_SCSI)
case UCLASS_SCSI: {
struct efi_device_path_scsi *dp =
dp_fill(buf, dev->parent);
return &dp[1];
}
#endif
-#if defined(CONFIG_DM_MMC) && defined(CONFIG_MMC)
+#if defined(CONFIG_MMC)
case UCLASS_MMC: {
struct efi_device_path_sd_mmc_path *sddp =
dp_fill(buf, dev->parent);
dev->name, dev->parent->uclass->uc_drv->id);
return dp_fill(buf, dev->parent);
}
-#endif
-#if defined(CONFIG_DM_MMC) && defined(CONFIG_MMC)
+#if defined(CONFIG_MMC)
case UCLASS_MMC: {
struct efi_device_path_sd_mmc_path *sddp =
dp_fill(buf, dev->parent);
return dp_fill(buf, dev->parent);
}
}
-#endif
static unsigned dp_part_size(struct blk_desc *desc, int part)
{
unsigned dpsize;
+ struct udevice *dev;
+ int ret;
-#ifdef CONFIG_BLK
- {
- struct udevice *dev;
- int ret = blk_find_device(desc->if_type, desc->devnum, &dev);
+ ret = blk_find_device(desc->if_type, desc->devnum, &dev);
- if (ret)
- dev = desc->bdev->parent;
- dpsize = dp_size(dev);
- }
-#else
- dpsize = sizeof(ROOT) + sizeof(struct efi_device_path_usb);
-#endif
+ if (ret)
+ dev = desc->bdev->parent;
+ dpsize = dp_size(dev);
if (part == 0) /* the actual disk, not a partition */
return dpsize;
*/
static void *dp_part_fill(void *buf, struct blk_desc *desc, int part)
{
-#ifdef CONFIG_BLK
- {
- struct udevice *dev;
- int ret = blk_find_device(desc->if_type, desc->devnum, &dev);
+ struct udevice *dev;
+ int ret;
- if (ret)
- dev = desc->bdev->parent;
- buf = dp_fill(buf, dev);
- }
-#else
- /*
- * We *could* make a more accurate path, by looking at if_type
- * and handling all the different cases like we do for non-
- * legacy (i.e. CONFIG_BLK=y) case. But most important thing
- * is just to have a unique device-path for if_type+devnum.
- * So map things to a fictitious USB device.
- */
- struct efi_device_path_usb *udp;
-
- memcpy(buf, &ROOT, sizeof(ROOT));
- buf += sizeof(ROOT);
-
- udp = buf;
- udp->dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE;
- udp->dp.sub_type = DEVICE_PATH_SUB_TYPE_MSG_USB;
- udp->dp.length = sizeof(*udp);
- udp->parent_port_number = desc->if_type;
- udp->usb_interface = desc->devnum;
- buf = &udp[1];
-#endif
+ ret = blk_find_device(desc->if_type, desc->devnum, &dev);
+
+ if (ret)
+ dev = desc->bdev->parent;
+ buf = dp_fill(buf, dev);
if (part == 0) /* the actual disk, not a partition */
return buf;
#ifdef CONFIG_NET
struct efi_device_path *efi_dp_from_eth(void)
{
-#ifndef CONFIG_DM_ETH
- struct efi_device_path_mac_addr *ndp;
-#endif
void *buf, *start;
unsigned dpsize = 0;
assert(eth_get_dev());
-#ifdef CONFIG_DM_ETH
dpsize += dp_size(eth_get_dev());
-#else
- dpsize += sizeof(ROOT);
- dpsize += sizeof(*ndp);
-#endif
start = buf = dp_alloc(dpsize + sizeof(END));
if (!buf)
return NULL;
-#ifdef CONFIG_DM_ETH
buf = dp_fill(buf, eth_get_dev());
-#else
- memcpy(buf, &ROOT, sizeof(ROOT));
- buf += sizeof(ROOT);
-
- ndp = buf;
- ndp->dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE;
- ndp->dp.sub_type = DEVICE_PATH_SUB_TYPE_MSG_MAC_ADDR;
- ndp->dp.length = sizeof(*ndp);
- ndp->if_type = 1; /* Ethernet */
- memcpy(ndp->mac.addr, eth_get_ethaddr(), ARP_HLEN);
- buf = &ndp[1];
-#endif
*((struct efi_device_path *)buf) = END;
* initrd location
*
* @lo: EFI_LOAD_OPTION containing a valid device path
- * @size: size of the discovered device path
* @guid: guid to search for
*
* Return:
*/
struct
efi_device_path *efi_dp_from_lo(struct efi_load_option *lo,
- efi_uintn_t *size, efi_guid_t guid)
+ const efi_guid_t *guid)
{
struct efi_device_path *fp = lo->file_path;
struct efi_device_path_vendor *vendor;
continue;
vendor = (struct efi_device_path_vendor *)fp;
- if (!guidcmp(&vendor->guid, &guid))
- return efi_dp_dup(fp);
+ if (!guidcmp(&vendor->guid, guid))
+ return efi_dp_dup(efi_dp_next(fp));
}
log_debug("VenMedia(%pUl) not found in %ls\n", &guid, lo->label);
return NULL;
}
+
+/**
+ * search_gpt_dp_node() - search gpt device path node
+ *
+ * @device_path: device path
+ *
+ * Return: pointer to the gpt device path node
+ */
+struct efi_device_path *search_gpt_dp_node(struct efi_device_path *device_path)
+{
+ struct efi_device_path *dp = device_path;
+
+ while (dp) {
+ if (dp->type == DEVICE_PATH_TYPE_MEDIA_DEVICE &&
+ dp->sub_type == DEVICE_PATH_SUB_TYPE_HARD_DRIVE_PATH) {
+ struct efi_device_path_hard_drive_path *hd_dp =
+ (struct efi_device_path_hard_drive_path *)dp;
+
+ if (hd_dp->partmap_type == PART_FORMAT_GPT &&
+ hd_dp->signature_type == SIG_TYPE_GUID)
+ return dp;
+ }
+ dp = efi_dp_next(dp);
+ }
+
+ return NULL;
+}
struct efi_disk_obj *disk;
int disks = 0;
efi_status_t ret;
-#ifdef CONFIG_BLK
struct udevice *dev;
for (uclass_first_device_check(UCLASS_BLK, &dev); dev;
&disk->header, desc, if_typename,
desc->devnum, dev->name);
}
-#else
- int i, if_type;
- /* Search for all available disk devices */
- for (if_type = 0; if_type < IF_TYPE_COUNT; if_type++) {
- const struct blk_driver *cur_drvr;
- const char *if_typename;
-
- cur_drvr = blk_driver_lookup_type(if_type);
- if (!cur_drvr)
- continue;
-
- if_typename = cur_drvr->if_typename;
- log_info("Scanning disks on %s...\n", if_typename);
- for (i = 0; i < 4; i++) {
- struct blk_desc *desc;
- char devname[32] = { 0 }; /* dp->str is u16[32] long */
-
- desc = blk_get_devnum_by_type(if_type, i);
- if (!desc)
- continue;
- if (desc->type == DEV_TYPE_UNKNOWN)
- continue;
-
- snprintf(devname, sizeof(devname), "%s%d",
- if_typename, i);
-
- /* Add block device for the full device */
- ret = efi_disk_add_dev(NULL, NULL, if_typename, desc,
- i, NULL, 0, &disk);
- if (ret == EFI_NOT_READY) {
- log_notice("Disk %s not ready\n", devname);
- continue;
- }
- if (ret) {
- log_err("ERROR: failure to add disk device %s, r = %lu\n",
- devname, ret & ~EFI_ERROR_MASK);
- return ret;
- }
- disks++;
-
- /* Partitions show up as block devices in EFI */
- disks += efi_disk_create_partitions
- (&disk->header, desc,
- if_typename, i, devname);
- }
- }
-#endif
log_info("Found %d disks\n", disks);
return EFI_SUCCESS;
#include <efi_loader.h>
#include <efi_variable.h>
+#if defined(CONFIG_CMD_EFIDEBUG) || defined(CONFIG_EFI_LOAD_FILE2_INITRD)
+/* GUID used by Linux to identify the LoadFile2 protocol with the initrd */
+const efi_guid_t efi_lf2_initrd_guid = EFI_INITRD_MEDIA_GUID;
+#endif
+
/**
* efi_create_current_boot_var() - Return Boot#### name were #### is replaced by
* the value of BootCurrent
*/
struct efi_device_path *efi_get_dp_from_boot(const efi_guid_t guid)
{
- struct efi_device_path *file_path = NULL;
- struct efi_device_path *tmp = NULL;
struct efi_load_option lo;
- void *var_value = NULL;
+ void *var_value;
efi_uintn_t size;
efi_status_t ret;
u16 var_name[16];
ret = efi_deserialize_load_option(&lo, var_value, &size);
if (ret != EFI_SUCCESS)
- goto out;
-
- tmp = efi_dp_from_lo(&lo, &size, guid);
- if (!tmp)
- goto out;
+ goto err;
- /* efi_dp_dup will just return NULL if efi_dp_next is NULL */
- file_path = efi_dp_dup(efi_dp_next(tmp));
+ return efi_dp_from_lo(&lo, &guid);
-out:
- efi_free_pool(tmp);
+err:
free(var_value);
-
- return file_path;
+ return NULL;
}
image_base = opt->ImageBase;
efi_set_code_and_data_type(loaded_image_info, opt->Subsystem);
handle->image_type = opt->Subsystem;
- virt_size = ALIGN(virt_size, opt->SectionAlignment);
- efi_reloc = efi_alloc(virt_size,
- loaded_image_info->image_code_type);
+ efi_reloc = efi_alloc_aligned_pages(virt_size,
+ loaded_image_info->image_code_type,
+ opt->SectionAlignment);
if (!efi_reloc) {
log_err("Out of memory\n");
ret = EFI_OUT_OF_RESOURCES;
image_base = opt->ImageBase;
efi_set_code_and_data_type(loaded_image_info, opt->Subsystem);
handle->image_type = opt->Subsystem;
- virt_size = ALIGN(virt_size, opt->SectionAlignment);
- efi_reloc = efi_alloc(virt_size,
- loaded_image_info->image_code_type);
+ efi_reloc = efi_alloc_aligned_pages(virt_size,
+ loaded_image_info->image_code_type,
+ opt->SectionAlignment);
if (!efi_reloc) {
log_err("Out of memory\n");
ret = EFI_OUT_OF_RESOURCES;
*/
static efi_status_t get_initrd_fp(struct efi_device_path **initrd_fp)
{
- const efi_guid_t lf2_initrd_guid = EFI_INITRD_MEDIA_GUID;
struct efi_device_path *dp = NULL;
/*
* We can then use this specific return value and not install the
* protocol, while allowing the boot to continue
*/
- dp = efi_get_dp_from_boot(lf2_initrd_guid);
+ dp = efi_get_dp_from_boot(efi_lf2_initrd_guid);
if (!dp)
return EFI_INVALID_PARAMETER;
}
/**
+ * efi_alloc_aligned_pages - allocate
+ *
+ * @len: len in bytes
+ * @memory_type: usage type of the allocated memory
+ * @align: alignment in bytes
+ * Return: aligned memory or NULL
+ */
+void *efi_alloc_aligned_pages(u64 len, int memory_type, size_t align)
+{
+ u64 req_pages = efi_size_in_pages(len);
+ u64 true_pages = req_pages + efi_size_in_pages(align) - 1;
+ u64 free_pages;
+ u64 aligned_mem;
+ efi_status_t r;
+ u64 mem;
+
+ /* align must be zero or a power of two */
+ if (align & (align - 1))
+ return NULL;
+
+ /* Check for overflow */
+ if (true_pages < req_pages)
+ return NULL;
+
+ if (align < EFI_PAGE_SIZE) {
+ r = efi_allocate_pages(EFI_ALLOCATE_ANY_PAGES, memory_type,
+ req_pages, &mem);
+ return (r == EFI_SUCCESS) ? (void *)(uintptr_t)mem : NULL;
+ }
+
+ r = efi_allocate_pages(EFI_ALLOCATE_ANY_PAGES, memory_type,
+ true_pages, &mem);
+ if (r != EFI_SUCCESS)
+ return NULL;
+
+ aligned_mem = ALIGN(mem, align);
+ /* Free pages before alignment */
+ free_pages = efi_size_in_pages(aligned_mem - mem);
+ if (free_pages)
+ efi_free_pages(mem, free_pages);
+
+ /* Free trailing pages */
+ free_pages = true_pages - (req_pages + free_pages);
+ if (free_pages) {
+ mem = aligned_mem + req_pages * EFI_PAGE_SIZE;
+ efi_free_pages(mem, free_pages);
+ }
+
+ return (void *)(uintptr_t)aligned_mem;
+}
+
+/**
* efi_allocate_pool - allocate memory from pool
*
* @pool_type: type of the pool from which memory is to be allocated
#include <common.h>
#include <charset.h>
#include <efi_loader.h>
+#include <efi_variable.h>
#include <image.h>
#include <hexdump.h>
#include <malloc.h>
*/
struct efi_signature_store *efi_sigstore_parse_sigdb(u16 *name)
{
- struct efi_signature_store *sigstore = NULL;
const efi_guid_t *vendor;
void *db;
efi_uintn_t db_size;
- efi_status_t ret;
-
- if (!u16_strcmp(name, L"PK") || !u16_strcmp(name, L"KEK")) {
- vendor = &efi_global_variable_guid;
- } else if (!u16_strcmp(name, L"db") || !u16_strcmp(name, L"dbx")) {
- vendor = &efi_guid_image_security_database;
- } else {
- EFI_PRINT("unknown signature database, %ls\n", name);
- return NULL;
- }
-
- /* retrieve variable data */
- db_size = 0;
- ret = EFI_CALL(efi_get_variable(name, vendor, NULL, &db_size, NULL));
- if (ret == EFI_NOT_FOUND) {
- EFI_PRINT("variable, %ls, not found\n", name);
- sigstore = calloc(sizeof(*sigstore), 1);
- return sigstore;
- } else if (ret != EFI_BUFFER_TOO_SMALL) {
- EFI_PRINT("Getting variable, %ls, failed\n", name);
- return NULL;
- }
- db = malloc(db_size);
+ vendor = efi_auth_var_get_guid(name);
+ db = efi_get_var(name, vendor, &db_size);
if (!db) {
- EFI_PRINT("Out of memory\n");
- return NULL;
- }
-
- ret = EFI_CALL(efi_get_variable(name, vendor, NULL, &db_size, db));
- if (ret != EFI_SUCCESS) {
- EFI_PRINT("Getting variable, %ls, failed\n", name);
- free(db);
- return NULL;
+ EFI_PRINT("variable, %ls, not found\n", name);
+ return calloc(sizeof(struct efi_signature_store), 1);
}
return efi_build_signature_store(db, db_size);
#include <mapmem.h>
#include <smbios.h>
-static const efi_guid_t smbios_guid = SMBIOS_TABLE_GUID;
-
/*
* Install the SMBIOS table as a configuration table.
*
#include <common.h>
#include <dm.h>
#include <efi_loader.h>
+#include <efi_variable.h>
#include <efi_tcg2.h>
#include <log.h>
#include <malloc.h>
+#include <smbios.h>
#include <version_string.h>
#include <tpm-v2.h>
#include <u-boot/hash-checksum.h>
#include <u-boot/sha1.h>
#include <u-boot/sha256.h>
#include <u-boot/sha512.h>
-#include <linux/unaligned/access_ok.h>
+#include <linux/unaligned/be_byteshift.h>
+#include <linux/unaligned/le_byteshift.h>
#include <linux/unaligned/generic.h>
#include <hexdump.h>
};
struct variable_info {
- u16 *name;
- const efi_guid_t *guid;
+ const u16 *name;
+ bool accept_empty;
+ u32 pcr_index;
};
static struct variable_info secure_variables[] = {
- {L"SecureBoot", &efi_global_variable_guid},
- {L"PK", &efi_global_variable_guid},
- {L"KEK", &efi_global_variable_guid},
- {L"db", &efi_guid_image_security_database},
- {L"dbx", &efi_guid_image_security_database},
+ {u"SecureBoot", true, 7},
+ {u"PK", true, 7},
+ {u"KEK", true, 7},
+ {u"db", true, 7},
+ {u"dbx", true, 7},
+ {u"dbt", false, 7},
+ {u"dbr", false, 7},
+ {u"DeployedMode", false, 1},
+ {u"AuditMode", false, 1},
};
#define MAX_HASH_COUNT ARRAY_SIZE(hash_algo_list)
* Return: status code
*/
static efi_status_t EFIAPI
-efi_tcg2_submit_command(__maybe_unused struct efi_tcg2_protocol *this,
- u32 __maybe_unused input_param_block_size,
- u8 __maybe_unused *input_param_block,
- u32 __maybe_unused output_param_block_size,
- u8 __maybe_unused *output_param_block)
+efi_tcg2_submit_command(struct efi_tcg2_protocol *this,
+ u32 input_param_block_size,
+ u8 *input_param_block,
+ u32 output_param_block_size,
+ u8 *output_param_block)
{
- return EFI_UNSUPPORTED;
+ struct udevice *dev;
+ efi_status_t ret;
+ u32 rc;
+ size_t resp_buf_size = output_param_block_size;
+
+ EFI_ENTRY("%p, %u, %p, %u, %p", this, input_param_block_size,
+ input_param_block, output_param_block_size, output_param_block);
+
+ if (!this || !input_param_block || !input_param_block_size) {
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+
+ ret = platform_get_tpm2_device(&dev);
+ if (ret != EFI_SUCCESS)
+ goto out;
+
+ rc = tpm2_submit_command(dev, input_param_block,
+ output_param_block, &resp_buf_size);
+ if (rc) {
+ ret = (rc == -ENOSPC) ? EFI_OUT_OF_RESOURCES : EFI_DEVICE_ERROR;
+
+ goto out;
+ }
+
+out:
+ return EFI_EXIT(ret);
}
/**
* Return: status code
*/
static efi_status_t tcg2_measure_variable(struct udevice *dev, u32 pcr_index,
- u32 event_type, u16 *var_name,
+ u32 event_type, const u16 *var_name,
const efi_guid_t *guid,
efi_uintn_t data_size, u8 *data)
{
boot_order = efi_get_var(var_name, &efi_global_variable_guid,
&var_data_size);
if (!boot_order) {
- ret = EFI_NOT_FOUND;
- goto error;
+ /* If "BootOrder" is not defined, skip the boot variable measurement */
+ return EFI_SUCCESS;
}
ret = tcg2_measure_variable(dev, 1, EV_EFI_VARIABLE_BOOT2, var_name,
}
/**
+ * tcg2_measure_smbios() - measure smbios table
+ *
+ * @dev: TPM device
+ * @entry: pointer to the smbios_entry structure
+ *
+ * Return: status code
+ */
+static efi_status_t
+tcg2_measure_smbios(struct udevice *dev,
+ const struct smbios_entry *entry)
+{
+ efi_status_t ret;
+ struct smbios_header *smbios_copy;
+ struct smbios_handoff_table_pointers2 *event = NULL;
+ u32 event_size;
+
+ /*
+ * TCG PC Client PFP Spec says
+ * "SMBIOS structures that contain static configuration information
+ * (e.g. Platform Manufacturer Enterprise Number assigned by IANA,
+ * platform model number, Vendor and Device IDs for each SMBIOS table)
+ * that is relevant to the security of the platform MUST be measured".
+ * Device dependent parameters such as serial number are cleared to
+ * zero or spaces for the measurement.
+ */
+ event_size = sizeof(struct smbios_handoff_table_pointers2) +
+ FIELD_SIZEOF(struct efi_configuration_table, guid) +
+ entry->struct_table_length;
+ event = calloc(1, event_size);
+ if (!event) {
+ ret = EFI_OUT_OF_RESOURCES;
+ goto out;
+ }
+
+ event->table_description_size = sizeof(SMBIOS_HANDOFF_TABLE_DESC);
+ memcpy(event->table_description, SMBIOS_HANDOFF_TABLE_DESC,
+ sizeof(SMBIOS_HANDOFF_TABLE_DESC));
+ put_unaligned_le64(1, &event->number_of_tables);
+ guidcpy(&event->table_entry[0].guid, &smbios_guid);
+ smbios_copy = (struct smbios_header *)((uintptr_t)&event->table_entry[0].table);
+ memcpy(&event->table_entry[0].table,
+ (void *)((uintptr_t)entry->struct_table_address),
+ entry->struct_table_length);
+
+ smbios_prepare_measurement(entry, smbios_copy);
+
+ ret = tcg2_measure_event(dev, 1, EV_EFI_HANDOFF_TABLES2, event_size,
+ (u8 *)event);
+ if (ret != EFI_SUCCESS)
+ goto out;
+
+out:
+ free(event);
+
+ return ret;
+}
+
+/**
+ * find_smbios_table() - find smbios table
+ *
+ * Return: pointer to the smbios table
+ */
+static void *find_smbios_table(void)
+{
+ u32 i;
+
+ for (i = 0; i < systab.nr_tables; i++) {
+ if (!guidcmp(&smbios_guid, &systab.tables[i].guid))
+ return systab.tables[i].table;
+ }
+
+ return NULL;
+}
+
+/**
+ * tcg2_measure_gpt_table() - measure gpt table
+ *
+ * @dev: TPM device
+ * @loaded_image: handle to the loaded image
+ *
+ * Return: status code
+ */
+static efi_status_t
+tcg2_measure_gpt_data(struct udevice *dev,
+ struct efi_loaded_image_obj *loaded_image)
+{
+ efi_status_t ret;
+ efi_handle_t handle;
+ struct efi_handler *dp_handler;
+ struct efi_device_path *orig_device_path;
+ struct efi_device_path *device_path;
+ struct efi_device_path *dp;
+ struct efi_block_io *block_io;
+ struct efi_gpt_data *event = NULL;
+ efi_guid_t null_guid = NULL_GUID;
+ gpt_header *gpt_h;
+ gpt_entry *entry = NULL;
+ gpt_entry *gpt_e;
+ u32 num_of_valid_entry = 0;
+ u32 event_size;
+ u32 i;
+ u32 total_gpt_entry_size;
+
+ ret = efi_search_protocol(&loaded_image->header,
+ &efi_guid_loaded_image_device_path,
+ &dp_handler);
+ if (ret != EFI_SUCCESS)
+ return ret;
+
+ orig_device_path = dp_handler->protocol_interface;
+ if (!orig_device_path) /* no device path, skip GPT measurement */
+ return EFI_SUCCESS;
+
+ device_path = efi_dp_dup(orig_device_path);
+ if (!device_path)
+ return EFI_OUT_OF_RESOURCES;
+
+ dp = search_gpt_dp_node(device_path);
+ if (!dp) {
+ /* no GPT device path node found, skip GPT measurement */
+ ret = EFI_SUCCESS;
+ goto out1;
+ }
+
+ /* read GPT header */
+ dp->type = DEVICE_PATH_TYPE_END;
+ dp->sub_type = DEVICE_PATH_SUB_TYPE_END;
+ dp = device_path;
+ ret = EFI_CALL(systab.boottime->locate_device_path(&efi_block_io_guid,
+ &dp, &handle));
+ if (ret != EFI_SUCCESS)
+ goto out1;
+
+ ret = EFI_CALL(efi_handle_protocol(handle,
+ &efi_block_io_guid, (void **)&block_io));
+ if (ret != EFI_SUCCESS)
+ goto out1;
+
+ gpt_h = memalign(block_io->media->io_align, block_io->media->block_size);
+ if (!gpt_h) {
+ ret = EFI_OUT_OF_RESOURCES;
+ goto out2;
+ }
+
+ ret = block_io->read_blocks(block_io, block_io->media->media_id, 1,
+ block_io->media->block_size, gpt_h);
+ if (ret != EFI_SUCCESS)
+ goto out2;
+
+ /* read GPT entry */
+ total_gpt_entry_size = gpt_h->num_partition_entries *
+ gpt_h->sizeof_partition_entry;
+ entry = memalign(block_io->media->io_align, total_gpt_entry_size);
+ if (!entry) {
+ ret = EFI_OUT_OF_RESOURCES;
+ goto out2;
+ }
+
+ ret = block_io->read_blocks(block_io, block_io->media->media_id,
+ gpt_h->partition_entry_lba,
+ total_gpt_entry_size, entry);
+ if (ret != EFI_SUCCESS)
+ goto out2;
+
+ /* count valid GPT entry */
+ gpt_e = entry;
+ for (i = 0; i < gpt_h->num_partition_entries; i++) {
+ if (guidcmp(&null_guid, &gpt_e->partition_type_guid))
+ num_of_valid_entry++;
+
+ gpt_e = (gpt_entry *)((u8 *)gpt_e + gpt_h->sizeof_partition_entry);
+ }
+
+ /* prepare event data for measurement */
+ event_size = sizeof(struct efi_gpt_data) +
+ (num_of_valid_entry * gpt_h->sizeof_partition_entry);
+ event = calloc(1, event_size);
+ if (!event) {
+ ret = EFI_OUT_OF_RESOURCES;
+ goto out2;
+ }
+ memcpy(event, gpt_h, sizeof(gpt_header));
+ put_unaligned_le64(num_of_valid_entry, &event->number_of_partitions);
+
+ /* copy valid GPT entry */
+ gpt_e = entry;
+ num_of_valid_entry = 0;
+ for (i = 0; i < gpt_h->num_partition_entries; i++) {
+ if (guidcmp(&null_guid, &gpt_e->partition_type_guid)) {
+ memcpy((u8 *)event->partitions +
+ (num_of_valid_entry * gpt_h->sizeof_partition_entry),
+ gpt_e, gpt_h->sizeof_partition_entry);
+ num_of_valid_entry++;
+ }
+
+ gpt_e = (gpt_entry *)((u8 *)gpt_e + gpt_h->sizeof_partition_entry);
+ }
+
+ ret = tcg2_measure_event(dev, 5, EV_EFI_GPT_EVENT, event_size, (u8 *)event);
+ if (ret != EFI_SUCCESS)
+ goto out2;
+
+out2:
+ EFI_CALL(efi_close_protocol((efi_handle_t)block_io, &efi_block_io_guid,
+ NULL, NULL));
+ free(gpt_h);
+ free(entry);
+ free(event);
+out1:
+ efi_free_pool(device_path);
+
+ return ret;
+}
+
+/**
* efi_tcg2_measure_efi_app_invocation() - measure efi app invocation
*
* Return: status code
*/
-efi_status_t efi_tcg2_measure_efi_app_invocation(void)
+efi_status_t efi_tcg2_measure_efi_app_invocation(struct efi_loaded_image_obj *handle)
{
efi_status_t ret;
u32 pcr_index;
struct udevice *dev;
u32 event = 0;
+ struct smbios_entry *entry;
if (tcg2_efi_app_invoked)
return EFI_SUCCESS;
if (ret != EFI_SUCCESS)
goto out;
+ entry = (struct smbios_entry *)find_smbios_table();
+ if (entry) {
+ ret = tcg2_measure_smbios(dev, entry);
+ if (ret != EFI_SUCCESS)
+ goto out;
+ }
+
+ ret = tcg2_measure_gpt_data(dev, handle);
+ if (ret != EFI_SUCCESS)
+ goto out;
+
for (pcr_index = 0; pcr_index <= 7; pcr_index++) {
ret = tcg2_measure_event(dev, pcr_index, EV_SEPARATOR,
sizeof(event), (u8 *)&event);
efi_uintn_t data_size;
u32 count, i;
efi_status_t ret;
+ u8 deployed_mode;
+ efi_uintn_t size;
+ u32 deployed_audit_pcr_index = 1;
+
+ size = sizeof(deployed_mode);
+ ret = efi_get_variable_int(u"DeployedMode", &efi_global_variable_guid,
+ NULL, &size, &deployed_mode, NULL);
+ if (ret != EFI_SUCCESS || !deployed_mode)
+ deployed_audit_pcr_index = 7;
count = ARRAY_SIZE(secure_variables);
for (i = 0; i < count; i++) {
- /*
- * According to the TCG2 PC Client PFP spec, "SecureBoot",
- * "PK", "KEK", "db" and "dbx" variables must be measured
- * even if they are empty.
- */
- data = efi_get_var(secure_variables[i].name,
- secure_variables[i].guid,
- &data_size);
+ const efi_guid_t *guid;
- ret = tcg2_measure_variable(dev, 7,
- EV_EFI_VARIABLE_DRIVER_CONFIG,
- secure_variables[i].name,
- secure_variables[i].guid,
- data_size, data);
- free(data);
- if (ret != EFI_SUCCESS)
- goto error;
- }
+ guid = efi_auth_var_get_guid(secure_variables[i].name);
- /*
- * TCG2 PC Client PFP spec says "dbt" and "dbr" are
- * measured if present and not empty.
- */
- data = efi_get_var(L"dbt",
- &efi_guid_image_security_database,
- &data_size);
- if (data) {
- ret = tcg2_measure_variable(dev, 7,
- EV_EFI_VARIABLE_DRIVER_CONFIG,
- L"dbt",
- &efi_guid_image_security_database,
- data_size, data);
- free(data);
- }
+ data = efi_get_var(secure_variables[i].name, guid, &data_size);
+ if (!data && !secure_variables[i].accept_empty)
+ continue;
- data = efi_get_var(L"dbr",
- &efi_guid_image_security_database,
- &data_size);
- if (data) {
- ret = tcg2_measure_variable(dev, 7,
+ if (u16_strcmp(u"DeployedMode", secure_variables[i].name))
+ secure_variables[i].pcr_index = deployed_audit_pcr_index;
+ if (u16_strcmp(u"AuditMode", secure_variables[i].name))
+ secure_variables[i].pcr_index = deployed_audit_pcr_index;
+
+ ret = tcg2_measure_variable(dev, secure_variables[i].pcr_index,
EV_EFI_VARIABLE_DRIVER_CONFIG,
- L"dbr",
- &efi_guid_image_security_database,
+ secure_variables[i].name, guid,
data_size, data);
free(data);
+ if (ret != EFI_SUCCESS)
+ goto error;
}
error:
return efi_secure_boot;
}
-enum efi_auth_var_type efi_auth_var_get_type(u16 *name, const efi_guid_t *guid)
+enum efi_auth_var_type efi_auth_var_get_type(const u16 *name,
+ const efi_guid_t *guid)
{
for (size_t i = 0; i < ARRAY_SIZE(name_type); ++i) {
if (!u16_strcmp(name, name_type[i].name) &&
return EFI_AUTH_VAR_NONE;
}
+const efi_guid_t *efi_auth_var_get_guid(const u16 *name)
+{
+ for (size_t i = 0; i < ARRAY_SIZE(name_type); ++i) {
+ if (!u16_strcmp(name, name_type[i].name))
+ return name_type[i].guid;
+ }
+ return &efi_global_variable_guid;
+}
+
/**
* efi_get_var() - read value of an EFI variable
*
*
* Return: buffer with variable data or NULL
*/
-void *efi_get_var(u16 *name, const efi_guid_t *vendor, efi_uintn_t *size)
+void *efi_get_var(const u16 *name, const efi_guid_t *vendor, efi_uintn_t *size)
{
efi_status_t ret;
void *buf = NULL;
#define PART_STR_LEN 10
+/* GUID used by Shim to store the MOK database */
+#define SHIM_LOCK_GUID \
+ EFI_GUID(0x605dab50, 0xe046, 0x4300, \
+ 0xab, 0xb6, 0x3d, 0xd8, 0x10, 0xdd, 0x8b, 0x23)
+
+static const efi_guid_t shim_lock_guid = SHIM_LOCK_GUID;
+
/**
* efi_set_blk_dev_to_system_partition() - select EFI system partition
*
if (!safe &&
(efi_auth_var_get_type(var->name, &var->guid) !=
EFI_AUTH_VAR_NONE ||
+ !guidcmp(&var->guid, &shim_lock_guid) ||
!(var->attr & EFI_VARIABLE_NON_VOLATILE)))
continue;
if (!var->length)
}
efi_status_t __efi_runtime efi_var_mem_ins(
- u16 *variable_name,
+ const u16 *variable_name,
const efi_guid_t *vendor, u32 attributes,
const efi_uintn_t size1, const void *data1,
const efi_uintn_t size2, const void *data2,
}
efi_status_t __efi_runtime
-efi_get_variable_mem(u16 *variable_name, const efi_guid_t *vendor, u32 *attributes,
- efi_uintn_t *data_size, void *data, u64 *timep)
+efi_get_variable_mem(const u16 *variable_name, const efi_guid_t *vendor,
+ u32 *attributes, efi_uintn_t *data_size, void *data,
+ u64 *timep)
{
efi_uintn_t old_size;
struct efi_var_entry *var;
*
* Return: status code
*/
-static efi_status_t efi_variable_authenticate(u16 *variable,
+static efi_status_t efi_variable_authenticate(const u16 *variable,
const efi_guid_t *vendor,
efi_uintn_t *data_size,
const void **data, u32 given_attr,
return ret;
}
#else
-static efi_status_t efi_variable_authenticate(u16 *variable,
+static efi_status_t efi_variable_authenticate(const u16 *variable,
const efi_guid_t *vendor,
efi_uintn_t *data_size,
const void **data, u32 given_attr,
#endif /* CONFIG_EFI_SECURE_BOOT */
efi_status_t __efi_runtime
-efi_get_variable_int(u16 *variable_name, const efi_guid_t *vendor,
+efi_get_variable_int(const u16 *variable_name, const efi_guid_t *vendor,
u32 *attributes, efi_uintn_t *data_size, void *data,
u64 *timep)
{
return efi_get_next_variable_name_mem(variable_name_size, variable_name, vendor);
}
-efi_status_t efi_set_variable_int(u16 *variable_name, const efi_guid_t *vendor,
+efi_status_t efi_set_variable_int(const u16 *variable_name,
+ const efi_guid_t *vendor,
u32 attributes, efi_uintn_t data_size,
const void *data, bool ro_check)
{
* StMM can store internal attributes and properties for variables, i.e enabling
* R/O variables
*/
-static efi_status_t set_property_int(u16 *variable_name, efi_uintn_t name_size,
+static efi_status_t set_property_int(const u16 *variable_name,
+ efi_uintn_t name_size,
const efi_guid_t *vendor,
struct var_check_property *var_property)
{
return ret;
}
-static efi_status_t get_property_int(u16 *variable_name, efi_uintn_t name_size,
+static efi_status_t get_property_int(const u16 *variable_name,
+ efi_uintn_t name_size,
const efi_guid_t *vendor,
struct var_check_property *var_property)
{
return ret;
}
-efi_status_t efi_get_variable_int(u16 *variable_name, const efi_guid_t *vendor,
+efi_status_t efi_get_variable_int(const u16 *variable_name,
+ const efi_guid_t *vendor,
u32 *attributes, efi_uintn_t *data_size,
void *data, u64 *timep)
{
return ret;
}
-efi_status_t efi_set_variable_int(u16 *variable_name, const efi_guid_t *vendor,
- u32 attributes, efi_uintn_t data_size,
- const void *data, bool ro_check)
+efi_status_t efi_set_variable_int(const u16 *variable_name,
+ const efi_guid_t *vendor, u32 attributes,
+ efi_uintn_t data_size, const void *data,
+ bool ro_check)
{
efi_status_t ret, alt_ret = EFI_SUCCESS;
struct var_check_property var_property;
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * This file contains a precompiled EFI binary built from
+ * lib/efi_selftest/efi_miniapp_file_image_exit.c and converted to an include
+ * using tools/file2include. It is used to testing the EFI_TCG2_PROTOCOL.
+ * The precompiled form is needed to avoid the problem of reproducible builds.
+ */
+
+#define EFI_ST_DISK_IMG { 0x00000570, { \
+ {0x00000000, "\x4d\x5a\x00\x00\x00\x00\x00\x00"}, /* MZ...... */ \
+ {0x00000038, "\x00\x00\x00\x00\x40\x00\x00\x00"}, /* ....@... */ \
+ {0x00000040, "\x50\x45\x00\x00\xc2\x01\x02\x00"}, /* PE...... */ \
+ {0x00000050, "\x00\x00\x00\x00\x90\x00\x0e\x03"}, /* ........ */ \
+ {0x00000058, "\x0b\x01\x02\x14\x38\x04\x00\x00"}, /* ....8... */ \
+ {0x00000068, "\x38\x01\x00\x00\x38\x01\x00\x00"}, /* 8...8... */ \
+ {0x00000078, "\x20\x00\x00\x00\x08\x00\x00\x00"}, /* ....... */ \
+ {0x00000090, "\x70\x05\x00\x00\x38\x01\x00\x00"}, /* p...8... */ \
+ {0x00000098, "\x00\x00\x00\x00\x0a\x00\x00\x00"}, /* ........ */ \
+ {0x000000b0, "\x00\x00\x00\x00\x06\x00\x00\x00"}, /* ........ */ \
+ {0x000000e8, "\x2e\x72\x65\x6c\x6f\x63\x00\x00"}, /* .reloc.. */ \
+ {0x00000108, "\x00\x00\x00\x00\x40\x00\x10\x42"}, /* ....@..B */ \
+ {0x00000110, "\x2e\x74\x65\x78\x74\x00\x00\x00"}, /* .text... */ \
+ {0x00000118, "\x38\x04\x00\x00\x38\x01\x00\x00"}, /* 8...8... */ \
+ {0x00000120, "\x38\x04\x00\x00\x38\x01\x00\x00"}, /* 8...8... */ \
+ {0x00000130, "\x00\x00\x00\x00\x20\x00\x50\xe0"}, /* .... .P. */ \
+ {0x00000138, "\x07\x40\x2d\xe9\x24\x10\x8f\xe2"}, /* .@-.$... */ \
+ {0x00000140, "\x00\x00\x91\xe5\x01\x10\x80\xe0"}, /* ........ */ \
+ {0x00000148, "\x15\x0e\x4f\xe2\x5a\x00\x00\xeb"}, /* ..O.Z... */ \
+ {0x00000150, "\x00\x00\x30\xe3\x01\x00\x00\x1a"}, /* ..0..... */ \
+ {0x00000158, "\x03\x00\x9d\xe8\x2e\x00\x00\xeb"}, /* ........ */ \
+ {0x00000160, "\x0c\xd0\x8d\xe2\x04\xf0\x9d\xe4"}, /* ........ */ \
+ {0x00000168, "\xa8\x03\x00\x00\x02\x30\xa0\xe3"}, /* .....0.. */ \
+ {0x00000170, "\x30\x40\x2d\xe9\x14\xd0\x4d\xe2"}, /* 0@-...M. */ \
+ {0x00000178, "\x3c\x20\x91\xe5\x2c\x50\x91\xe5"}, /* < ..,P.. */ \
+ {0x00000180, "\x04\x30\x8d\xe5\x00\x30\xa0\xe3"}, /* .0...0.. */ \
+ {0x00000188, "\x7c\x10\x9f\xe5\x00\x30\x8d\xe5"}, /* |....0.. */ \
+ {0x00000190, "\x98\x40\x92\xe5\x01\x10\x8f\xe0"}, /* .@...... */ \
+ {0x00000198, "\x0c\x20\x8d\xe2\x34\xff\x2f\xe1"}, /* . ..4./. */ \
+ {0x000001a0, "\x00\x40\x50\xe2\x07\x00\x00\x0a"}, /* .@P..... */ \
+ {0x000001a8, "\x60\x10\x9f\xe5\x05\x00\xa0\xe1"}, /* `....... */ \
+ {0x000001b0, "\x04\x30\x95\xe5\x01\x10\x8f\xe0"}, /* .0...... */ \
+ {0x000001b8, "\x33\xff\x2f\xe1\x04\x00\xa0\xe1"}, /* 3./..... */ \
+ {0x000001c0, "\x14\xd0\x8d\xe2\x30\x80\xbd\xe8"}, /* ....0... */ \
+ {0x000001c8, "\x0c\x10\x9d\xe5\x40\x20\x9f\xe5"}, /* ....@ .. */ \
+ {0x000001d0, "\x20\x30\x91\xe5\x02\x20\x8f\xe0"}, /* 0... .. */ \
+ {0x000001d8, "\x02\x00\x53\xe1\x03\x00\x00\x8a"}, /* ..S..... */ \
+ {0x000001e0, "\x28\x10\x91\xe5\x01\x30\x83\xe0"}, /* (....0.. */ \
+ {0x000001e8, "\x02\x00\x53\xe1\xf2\xff\xff\x8a"}, /* ..S..... */ \
+ {0x000001f0, "\x20\x10\x9f\xe5\x05\x00\xa0\xe1"}, /* ....... */ \
+ {0x000001f8, "\x04\x30\x95\xe5\x01\x10\x8f\xe0"}, /* .0...... */ \
+ {0x00000200, "\x33\xff\x2f\xe1\x3a\x41\xa0\xe3"}, /* 3./.:A.. */ \
+ {0x00000208, "\xeb\xff\xff\xea\xac\x03\x00\x00"}, /* ........ */ \
+ {0x00000210, "\x34\x02\x00\x00\x90\xff\xff\xff"}, /* 4....... */ \
+ {0x00000218, "\x36\x02\x00\x00\xf0\x40\x2d\xe9"}, /* 6....@-. */ \
+ {0x00000220, "\x14\xd0\x4d\xe2\x0d\x70\xa0\xe1"}, /* ..M..p.. */ \
+ {0x00000228, "\x00\x50\xa0\xe1\x01\x40\xa0\xe1"}, /* .P...@.. */ \
+ {0x00000230, "\x2c\x60\x91\xe5\x74\x10\x9f\xe5"}, /* ,`..t... */ \
+ {0x00000238, "\x10\x20\xa0\xe3\x01\x10\x8f\xe0"}, /* . ...... */ \
+ {0x00000240, "\x07\x00\xa0\xe1\x60\x00\x00\xeb"}, /* ....`... */ \
+ {0x00000248, "\x64\x10\x9f\xe5\x04\x30\x96\xe5"}, /* d....0.. */ \
+ {0x00000250, "\x01\x10\x8f\xe0\x06\x00\xa0\xe1"}, /* ........ */ \
+ {0x00000258, "\x33\xff\x2f\xe1\x04\x10\xa0\xe1"}, /* 3./..... */ \
+ {0x00000260, "\x05\x00\xa0\xe1\xc0\xff\xff\xeb"}, /* ........ */ \
+ {0x00000268, "\x00\x00\x50\xe3\x0e\x11\xa0\x03"}, /* ..P..... */ \
+ {0x00000270, "\x05\x00\x00\x0a\x3c\x10\x9f\xe5"}, /* ....<... */ \
+ {0x00000278, "\x06\x00\xa0\xe1\x01\x10\x8f\xe0"}, /* ........ */ \
+ {0x00000280, "\x04\x30\x96\xe5\x33\xff\x2f\xe1"}, /* .0..3./. */ \
+ {0x00000288, "\x3a\x11\xa0\xe3\x3c\x30\x94\xe5"}, /* :...<0.. */ \
+ {0x00000290, "\x10\x20\xa0\xe3\x78\x40\x93\xe5"}, /* . ..x@.. */ \
+ {0x00000298, "\x05\x00\xa0\xe1\x07\x30\xa0\xe1"}, /* .....0.. */ \
+ {0x000002a0, "\x34\xff\x2f\xe1\x00\x00\xa0\xe3"}, /* 4./..... */ \
+ {0x000002a8, "\x14\xd0\x8d\xe2\xf0\x80\xbd\xe8"}, /* ........ */ \
+ {0x000002b0, "\xb8\x02\x00\x00\x2a\x02\x00\x00"}, /* ........ */ \
+ {0x000002b8, "\x3a\x02\x00\x00\x00\x30\xa0\xe3"}, /* :....0.. */ \
+ {0x000002c0, "\x03\x20\xa0\xe1\x03\xc0\xa0\xe1"}, /* . ...... */ \
+ {0x000002c8, "\x04\xe0\x2d\xe5\x00\xe0\x91\xe5"}, /* ..-..... */ \
+ {0x000002d0, "\x00\x00\x5e\xe3\x03\x00\x00\x1a"}, /* ..^..... */ \
+ {0x000002d8, "\x02\x10\x93\xe1\x0c\x00\x00\x1a"}, /* ........ */ \
+ {0x000002e0, "\x00\x00\xa0\xe3\x04\xf0\x9d\xe4"}, /* ........ */ \
+ {0x000002e8, "\x12\x00\x5e\xe3\x04\xc0\x91\x05"}, /* ..^..... */ \
+ {0x000002f0, "\x05\x00\x00\x0a\x13\x00\x5e\xe3"}, /* ......^. */ \
+ {0x000002f8, "\x04\x20\x91\x05\x02\x00\x00\x0a"}, /* . ...... */ \
+ {0x00000300, "\x11\x00\x5e\xe3\x04\x30\x91\x05"}, /* ..^..0.. */ \
+ {0x00000308, "\x03\x30\x80\x00\x08\x10\x81\xe2"}, /* .0...... */ \
+ {0x00000310, "\xed\xff\xff\xea\x00\x00\x52\xe3"}, /* ......R. */ \
+ {0x00000318, "\x00\x00\x53\x13\x09\x00\x00\x1a"}, /* ..S..... */ \
+ {0x00000320, "\x06\x01\xa0\xe3\x04\xf0\x9d\xe4"}, /* ........ */ \
+ {0x00000328, "\x04\x10\xd3\xe5\x02\xc0\x4c\xe0"}, /* ......L. */ \
+ {0x00000330, "\x17\x00\x51\xe3\x00\xe0\x93\x05"}, /* ..Q..... */ \
+ {0x00000338, "\x02\x30\x83\xe0\x0e\x10\x90\x07"}, /* .0...... */ \
+ {0x00000340, "\x00\x10\x81\x00\x0e\x10\x80\x07"}, /* ........ */ \
+ {0x00000348, "\x00\x00\x5c\xe3\xf5\xff\xff\xca"}, /* ..\..... */ \
+ {0x00000350, "\xe2\xff\xff\xea\x01\x10\x41\xe2"}, /* ......A. */ \
+ {0x00000358, "\x02\x20\x80\xe0\x02\x00\x50\xe1"}, /* . ....P. */ \
+ {0x00000360, "\x01\x00\x00\x1a\x00\x00\xa0\xe3"}, /* ........ */ \
+ {0x00000368, "\x1e\xff\x2f\xe1\x00\x30\xd0\xe5"}, /* ../..0.. */ \
+ {0x00000370, "\x01\xc0\xf1\xe5\x0c\x00\x53\xe1"}, /* ......S. */ \
+ {0x00000378, "\x01\x00\x00\x0a\x0c\x00\x43\xe0"}, /* ......C. */ \
+ {0x00000380, "\x1e\xff\x2f\xe1\x01\x00\x80\xe2"}, /* ../..... */ \
+ {0x00000388, "\xf3\xff\xff\xea\x01\x00\x50\xe1"}, /* ......P. */ \
+ {0x00000390, "\x02\x30\x81\xe0\x01\x20\x40\x92"}, /* .0... @. */ \
+ {0x00000398, "\x08\x00\x00\x9a\x00\x10\xa0\xe1"}, /* ........ */ \
+ {0x000003a0, "\x02\x20\x80\xe0\x01\x00\x52\xe1"}, /* . ....R. */ \
+ {0x000003a8, "\x1e\xff\x2f\x01\x01\xc0\x73\xe5"}, /* ../...s. */ \
+ {0x000003b0, "\x01\xc0\x62\xe5\xfa\xff\xff\xea"}, /* ..b..... */ \
+ {0x000003b8, "\x01\xc0\xd1\xe4\x01\xc0\xe2\xe5"}, /* ........ */ \
+ {0x000003c0, "\x03\x00\x51\xe1\xfb\xff\xff\x1a"}, /* ..Q..... */ \
+ {0x000003c8, "\x1e\xff\x2f\xe1\xee\xff\xff\xea"}, /* ../..... */ \
+ {0x000003d0, "\x00\x30\xa0\xe1\x02\x20\x80\xe0"}, /* .0... .. */ \
+ {0x000003d8, "\x02\x00\x53\xe1\x1e\xff\x2f\x01"}, /* ..S.../. */ \
+ {0x000003e0, "\x01\x10\xc3\xe4\xfb\xff\xff\xea"}, /* ........ */ \
+ {0x000003e8, "\x1e\xff\x2f\xe1\x1e\xff\x2f\xe1"}, /* ../.../. */ \
+ {0x000003f0, "\x43\x00\x6f\x00\x75\x00\x6c\x00"}, /* C.o.u.l. */ \
+ {0x000003f8, "\x64\x00\x20\x00\x6e\x00\x6f\x00"}, /* d. .n.o. */ \
+ {0x00000400, "\x74\x00\x20\x00\x6f\x00\x70\x00"}, /* t. .o.p. */ \
+ {0x00000408, "\x65\x00\x6e\x00\x20\x00\x6c\x00"}, /* e.n. .l. */ \
+ {0x00000410, "\x6f\x00\x61\x00\x64\x00\x65\x00"}, /* o.a.d.e. */ \
+ {0x00000418, "\x64\x00\x20\x00\x69\x00\x6d\x00"}, /* d. .i.m. */ \
+ {0x00000420, "\x61\x00\x67\x00\x65\x00\x20\x00"}, /* a.g.e. . */ \
+ {0x00000428, "\x70\x00\x72\x00\x6f\x00\x74\x00"}, /* p.r.o.t. */ \
+ {0x00000430, "\x6f\x00\x63\x00\x6f\x00\x6c\x00"}, /* o.c.o.l. */ \
+ {0x00000438, "\x00\x00\x49\x00\x6e\x00\x63\x00"}, /* ..I.n.c. */ \
+ {0x00000440, "\x6f\x00\x72\x00\x72\x00\x65\x00"}, /* o.r.r.e. */ \
+ {0x00000448, "\x63\x00\x74\x00\x20\x00\x69\x00"}, /* c.t. .i. */ \
+ {0x00000450, "\x6d\x00\x61\x00\x67\x00\x65\x00"}, /* m.a.g.e. */ \
+ {0x00000458, "\x5f\x00\x62\x00\x61\x00\x73\x00"}, /* _.b.a.s. */ \
+ {0x00000460, "\x65\x00\x20\x00\x6f\x00\x72\x00"}, /* e. .o.r. */ \
+ {0x00000468, "\x20\x00\x69\x00\x6d\x00\x61\x00"}, /* .i.m.a. */ \
+ {0x00000470, "\x67\x00\x65\x00\x5f\x00\x73\x00"}, /* g.e._.s. */ \
+ {0x00000478, "\x69\x00\x7a\x00\x65\x00\x0a\x00"}, /* i.z.e... */ \
+ {0x00000480, "\x00\x00\x45\x00\x46\x00\x49\x00"}, /* ..E.F.I. */ \
+ {0x00000488, "\x20\x00\x61\x00\x70\x00\x70\x00"}, /* .a.p.p. */ \
+ {0x00000490, "\x6c\x00\x69\x00\x63\x00\x61\x00"}, /* l.i.c.a. */ \
+ {0x00000498, "\x74\x00\x69\x00\x6f\x00\x6e\x00"}, /* t.i.o.n. */ \
+ {0x000004a0, "\x20\x00\x63\x00\x61\x00\x6c\x00"}, /* .c.a.l. */ \
+ {0x000004a8, "\x6c\x00\x69\x00\x6e\x00\x67\x00"}, /* l.i.n.g. */ \
+ {0x000004b0, "\x20\x00\x45\x00\x78\x00\x69\x00"}, /* .E.x.i. */ \
+ {0x000004b8, "\x74\x00\x0a\x00\x00\x00\x4c\x00"}, /* t.....L. */ \
+ {0x000004c0, "\x6f\x00\x61\x00\x64\x00\x65\x00"}, /* o.a.d.e. */ \
+ {0x000004c8, "\x64\x00\x20\x00\x69\x00\x6d\x00"}, /* d. .i.m. */ \
+ {0x000004d0, "\x61\x00\x67\x00\x65\x00\x20\x00"}, /* a.g.e. . */ \
+ {0x000004d8, "\x70\x00\x72\x00\x6f\x00\x74\x00"}, /* p.r.o.t. */ \
+ {0x000004e0, "\x6f\x00\x63\x00\x6f\x00\x6c\x00"}, /* o.c.o.l. */ \
+ {0x000004e8, "\x20\x00\x6d\x00\x69\x00\x73\x00"}, /* .m.i.s. */ \
+ {0x000004f0, "\x73\x00\x69\x00\x6e\x00\x67\x00"}, /* s.i.n.g. */ \
+ {0x000004f8, "\x0a\x00\x00\x00\x53\x00\x55\x00"}, /* ....S.U. */ \
+ {0x00000500, "\x43\x00\x43\x00\x45\x00\x53\x00"}, /* C.C.E.S. */ \
+ {0x00000508, "\x53\x00\x00\x00\x00\x00\x00\x00"}, /* S....... */ \
+ {0x00000510, "\x10\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000548, "\xa1\x31\x1b\x5b\x62\x95\xd2\x11"}, /* .1.[b... */ \
+ {0x00000550, "\x8e\x3f\x00\xa0\xc9\x69\x72\x3b"}, /* .?...ir; */ \
+ {0x00000558, "\x10\x05\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0, NULL} } }
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * This file contains a precompiled EFI binary built from
+ * lib/efi_selftest/efi_miniapp_file_image_exit.c and converted to an include
+ * using tools/file2include. It is used to testing the EFI_TCG2_PROTOCOL.
+ * The precompiled form is needed to avoid the problem of reproducible builds.
+ */
+
+#define EFI_ST_DISK_IMG { 0x000011e0, { \
+ {0x00000000, "\x4d\x5a\x00\x00\x00\x00\x00\x00"}, /* MZ...... */ \
+ {0x00000038, "\x41\x52\x4d\x64\x40\x00\x00\x00"}, /* ARMd@... */ \
+ {0x00000040, "\x50\x45\x00\x00\x64\xaa\x02\x00"}, /* PE..d... */ \
+ {0x00000050, "\x00\x00\x00\x00\xa0\x00\x0e\x02"}, /* ........ */ \
+ {0x00000058, "\x0b\x02\x02\x14\xd8\x04\x00\x00"}, /* ........ */ \
+ {0x00000068, "\x48\x01\x00\x00\x48\x01\x00\x00"}, /* H...H... */ \
+ {0x00000078, "\x20\x00\x00\x00\x08\x00\x00\x00"}, /* ....... */ \
+ {0x00000090, "\x20\x06\x00\x00\x48\x01\x00\x00"}, /* ...H... */ \
+ {0x00000098, "\x00\x00\x00\x00\x0a\x00\x00\x00"}, /* ........ */ \
+ {0x000000c0, "\x00\x00\x00\x00\x06\x00\x00\x00"}, /* ........ */ \
+ {0x000000f8, "\x2e\x72\x65\x6c\x6f\x63\x00\x00"}, /* .reloc.. */ \
+ {0x00000118, "\x00\x00\x00\x00\x40\x00\x10\x42"}, /* ....@..B */ \
+ {0x00000120, "\x2e\x74\x65\x78\x74\x00\x00\x00"}, /* .text... */ \
+ {0x00000128, "\xd8\x04\x00\x00\x48\x01\x00\x00"}, /* ....H... */ \
+ {0x00000130, "\xd8\x04\x00\x00\x48\x01\x00\x00"}, /* ....H... */ \
+ {0x00000140, "\x00\x00\x00\x00\x20\x00\x50\xe0"}, /* .... .P. */ \
+ {0x00000148, "\xfd\x7b\xbe\xa9\xfd\x03\x00\x91"}, /* .{...... */ \
+ {0x00000150, "\xe0\x07\x01\xa9\x60\xf5\xff\x10"}, /* ....`... */ \
+ {0x00000158, "\x01\x00\x00\x90\x21\xc0\x14\x91"}, /* ....!... */ \
+ {0x00000160, "\x5a\x00\x00\x94\x60\x00\x00\xb5"}, /* Z...`... */ \
+ {0x00000168, "\xe0\x07\x41\xa9\x2d\x00\x00\x94"}, /* ..A.-... */ \
+ {0x00000170, "\xfd\x7b\xc2\xa8\xc0\x03\x5f\xd6"}, /* .{...._. */ \
+ {0x00000178, "\xfd\x7b\xbd\xa9\x45\x00\x80\x52"}, /* .{..E..R */ \
+ {0x00000180, "\x04\x00\x80\xd2\x03\x00\x80\xd2"}, /* ........ */ \
+ {0x00000188, "\xfd\x03\x00\x91\xf3\x53\x01\xa9"}, /* .....S.. */ \
+ {0x00000190, "\xa2\xa3\x00\x91\x33\x20\x40\xf9"}, /* ....3 @. */ \
+ {0x00000198, "\x21\x30\x40\xf9\x26\x8c\x40\xf9"}, /* !0@.&.@. */ \
+ {0x000001a0, "\x01\x00\x00\x90\x21\xc0\x17\x91"}, /* ....!... */ \
+ {0x000001a8, "\xc0\x00\x3f\xd6\xf4\x03\x00\xaa"}, /* ..?..... */ \
+ {0x000001b0, "\x40\x01\x00\xb4\x62\x06\x40\xf9"}, /* @...b.@. */ \
+ {0x000001b8, "\x01\x00\x00\x90\xe0\x03\x13\xaa"}, /* ........ */ \
+ {0x000001c0, "\x21\x50\x10\x91\x40\x00\x3f\xd6"}, /* !P..@.?. */ \
+ {0x000001c8, "\xe0\x03\x14\xaa\xf3\x53\x41\xa9"}, /* .....SA. */ \
+ {0x000001d0, "\xfd\x7b\xc3\xa8\xc0\x03\x5f\xd6"}, /* .{...._. */ \
+ {0x000001d8, "\xa2\x17\x40\xf9\x00\x00\x00\x90"}, /* ..@..... */ \
+ {0x000001e0, "\x00\xe0\x05\x91\x41\x20\x40\xf9"}, /* ....A @. */ \
+ {0x000001e8, "\x3f\x00\x00\xeb\xa8\x00\x00\x54"}, /* ?......T */ \
+ {0x000001f0, "\x42\x24\x40\xf9\x21\x00\x02\x8b"}, /* B$@.!... */ \
+ {0x000001f8, "\x3f\x00\x00\xeb\x68\xfe\xff\x54"}, /* ?...h..T */ \
+ {0x00000200, "\x62\x06\x40\xf9\xd4\x01\x80\xd2"}, /* b.@..... */ \
+ {0x00000208, "\x01\x00\x00\x90\xe0\x03\x13\xaa"}, /* ........ */ \
+ {0x00000210, "\x21\x78\x11\x91\x14\x00\xf0\xf2"}, /* !x...... */ \
+ {0x00000218, "\x40\x00\x3f\xd6\xeb\xff\xff\x17"}, /* @.?..... */ \
+ {0x00000220, "\xfd\x7b\xbc\xa9\x02\x02\x80\xd2"}, /* .{...... */ \
+ {0x00000228, "\xfd\x03\x00\x91\xf5\x5b\x02\xa9"}, /* .....[.. */ \
+ {0x00000230, "\xb6\xc3\x00\x91\xf3\x53\x01\xa9"}, /* .....S.. */ \
+ {0x00000238, "\xf5\x03\x00\xaa\xf4\x03\x01\xaa"}, /* ........ */ \
+ {0x00000240, "\xe0\x03\x16\xaa\x33\x20\x40\xf9"}, /* ....3 @. */ \
+ {0x00000248, "\x01\x00\x00\x90\x21\x80\x14\x91"}, /* ....!... */ \
+ {0x00000250, "\x67\x00\x00\x94\x01\x00\x00\x90"}, /* g....... */ \
+ {0x00000258, "\xe0\x03\x13\xaa\x62\x06\x40\xf9"}, /* ....b.@. */ \
+ {0x00000260, "\x21\x98\x12\x91\x40\x00\x3f\xd6"}, /* !...@.?. */ \
+ {0x00000268, "\xe1\x03\x14\xaa\xe0\x03\x15\xaa"}, /* ........ */ \
+ {0x00000270, "\xc2\xff\xff\x97\x60\x02\x00\xb4"}, /* ....`... */ \
+ {0x00000278, "\x62\x06\x40\xf9\x01\x00\x00\x90"}, /* b.@..... */ \
+ {0x00000280, "\xe0\x03\x13\xaa\x21\x88\x13\x91"}, /* ....!... */ \
+ {0x00000288, "\x40\x00\x3f\xd6\xc1\x01\x80\xd2"}, /* @.?..... */ \
+ {0x00000290, "\x01\x00\xf0\xf2\x80\x32\x40\xf9"}, /* .....2@. */ \
+ {0x00000298, "\xe3\x03\x16\xaa\x02\x02\x80\xd2"}, /* ........ */ \
+ {0x000002a0, "\x04\x6c\x40\xf9\xe0\x03\x15\xaa"}, /* .l@..... */ \
+ {0x000002a8, "\x80\x00\x3f\xd6\x00\x00\x80\xd2"}, /* ..?..... */ \
+ {0x000002b0, "\xf3\x53\x41\xa9\xf5\x5b\x42\xa9"}, /* .SA..[B. */ \
+ {0x000002b8, "\xfd\x7b\xc4\xa8\xc0\x03\x5f\xd6"}, /* .{...._. */ \
+ {0x000002c0, "\xe1\x0b\x41\xb2\xf4\xff\xff\x17"}, /* ..A..... */ \
+ {0x000002c8, "\x21\x20\x00\x91\x02\x00\x80\xd2"}, /* ! ...... */ \
+ {0x000002d0, "\x04\x00\x80\xd2\x03\x00\x80\xd2"}, /* ........ */ \
+ {0x000002d8, "\x25\x80\x5f\xf8\x25\x01\x00\xb5"}, /* %._.%... */ \
+ {0x000002e0, "\x5f\x00\x00\xf1\xe1\x17\x9f\x1a"}, /* _....... */ \
+ {0x000002e8, "\x9f\x00\x00\xf1\xe5\x17\x9f\x1a"}, /* ........ */ \
+ {0x000002f0, "\x3f\x00\x05\x6a\x20\x02\x00\x54"}, /* ?..j ..T */ \
+ {0x000002f8, "\x00\x00\x80\xd2\xc0\x03\x5f\xd6"}, /* ......_. */ \
+ {0x00000300, "\xbf\x20\x00\xf1\x20\x01\x00\x54"}, /* . .. ..T */ \
+ {0x00000308, "\xbf\x24\x00\xf1\x20\x01\x00\x54"}, /* .$.. ..T */ \
+ {0x00000310, "\xbf\x1c\x00\xf1\x61\x00\x00\x54"}, /* ....a..T */ \
+ {0x00000318, "\x22\x00\x40\xf9\x02\x00\x02\x8b"}, /* ".@..... */ \
+ {0x00000320, "\x21\x40\x00\x91\xed\xff\xff\x17"}, /* !@...... */ \
+ {0x00000328, "\x23\x00\x40\xf9\xfd\xff\xff\x17"}, /* #.@..... */ \
+ {0x00000330, "\x24\x00\x40\xf9\xfb\xff\xff\x17"}, /* $.@..... */ \
+ {0x00000338, "\x21\x00\x05\x2a\xa1\x01\x00\x35"}, /* !......5 */ \
+ {0x00000340, "\x7f\x00\x00\xf1\xad\xfd\xff\x54"}, /* .......T */ \
+ {0x00000348, "\x41\x08\x40\xb9\x3f\x0c\x10\xf1"}, /* A.@.?... */ \
+ {0x00000350, "\xa1\x00\x00\x54\x45\x00\x40\xf9"}, /* ...TE.@. */ \
+ {0x00000358, "\x41\x08\x40\xf9\x21\x00\x00\x8b"}, /* A.@.!... */ \
+ {0x00000360, "\xa1\x68\x20\xf8\x42\x00\x04\x8b"}, /* .h .B... */ \
+ {0x00000368, "\x63\x00\x04\xcb\xf5\xff\xff\x17"}, /* c....... */ \
+ {0x00000370, "\xe0\x07\x41\xb2\xc0\x03\x5f\xd6"}, /* ..A..._. */ \
+ {0x00000378, "\x04\x00\x80\xd2\x5f\x00\x04\xeb"}, /* ...._... */ \
+ {0x00000380, "\x61\x00\x00\x54\x00\x00\x80\x52"}, /* a..T...R */ \
+ {0x00000388, "\xc0\x03\x5f\xd6\x03\x68\x64\x38"}, /* .._..hd8 */ \
+ {0x00000390, "\x84\x04\x00\x91\x25\x00\x04\x8b"}, /* ....%... */ \
+ {0x00000398, "\xa5\xf0\x5f\x38\x7f\x00\x05\x6b"}, /* .._8...k */ \
+ {0x000003a0, "\xe0\xfe\xff\x54\x60\x00\x05\x4b"}, /* ...T`..K */ \
+ {0x000003a8, "\xc0\x03\x5f\xd6\x1f\x00\x01\xeb"}, /* .._..... */ \
+ {0x000003b0, "\x68\x01\x00\x54\x03\x00\x80\xd2"}, /* h..T.... */ \
+ {0x000003b8, "\x7f\x00\x02\xeb\x41\x00\x00\x54"}, /* ....A..T */ \
+ {0x000003c0, "\xc0\x03\x5f\xd6\x24\x68\x63\x38"}, /* .._.$hc8 */ \
+ {0x000003c8, "\x04\x68\x23\x38\x63\x04\x00\x91"}, /* .h#8c... */ \
+ {0x000003d0, "\xfa\xff\xff\x17\x23\x68\x62\x38"}, /* ....#hb8 */ \
+ {0x000003d8, "\x03\x68\x22\x38\x42\x04\x00\xd1"}, /* .h"8B... */ \
+ {0x000003e0, "\x5f\x04\x00\xb1\x81\xff\xff\x54"}, /* _......T */ \
+ {0x000003e8, "\xc0\x03\x5f\xd6\xf0\xff\xff\x17"}, /* .._..... */ \
+ {0x000003f0, "\x03\x00\x80\xd2\x5f\x00\x03\xeb"}, /* ...._... */ \
+ {0x000003f8, "\x41\x00\x00\x54\xc0\x03\x5f\xd6"}, /* A..T.._. */ \
+ {0x00000400, "\x01\x68\x23\x38\x63\x04\x00\x91"}, /* .h#8c... */ \
+ {0x00000408, "\xfb\xff\xff\x17\xc0\x03\x5f\xd6"}, /* ......_. */ \
+ {0x00000410, "\xc0\x03\x5f\xd6\x43\x00\x6f\x00"}, /* .._.C.o. */ \
+ {0x00000418, "\x75\x00\x6c\x00\x64\x00\x20\x00"}, /* u.l.d. . */ \
+ {0x00000420, "\x6e\x00\x6f\x00\x74\x00\x20\x00"}, /* n.o.t. . */ \
+ {0x00000428, "\x6f\x00\x70\x00\x65\x00\x6e\x00"}, /* o.p.e.n. */ \
+ {0x00000430, "\x20\x00\x6c\x00\x6f\x00\x61\x00"}, /* .l.o.a. */ \
+ {0x00000438, "\x64\x00\x65\x00\x64\x00\x20\x00"}, /* d.e.d. . */ \
+ {0x00000440, "\x69\x00\x6d\x00\x61\x00\x67\x00"}, /* i.m.a.g. */ \
+ {0x00000448, "\x65\x00\x20\x00\x70\x00\x72\x00"}, /* e. .p.r. */ \
+ {0x00000450, "\x6f\x00\x74\x00\x6f\x00\x63\x00"}, /* o.t.o.c. */ \
+ {0x00000458, "\x6f\x00\x6c\x00\x00\x00\x49\x00"}, /* o.l...I. */ \
+ {0x00000460, "\x6e\x00\x63\x00\x6f\x00\x72\x00"}, /* n.c.o.r. */ \
+ {0x00000468, "\x72\x00\x65\x00\x63\x00\x74\x00"}, /* r.e.c.t. */ \
+ {0x00000470, "\x20\x00\x69\x00\x6d\x00\x61\x00"}, /* .i.m.a. */ \
+ {0x00000478, "\x67\x00\x65\x00\x5f\x00\x62\x00"}, /* g.e._.b. */ \
+ {0x00000480, "\x61\x00\x73\x00\x65\x00\x20\x00"}, /* a.s.e. . */ \
+ {0x00000488, "\x6f\x00\x72\x00\x20\x00\x69\x00"}, /* o.r. .i. */ \
+ {0x00000490, "\x6d\x00\x61\x00\x67\x00\x65\x00"}, /* m.a.g.e. */ \
+ {0x00000498, "\x5f\x00\x73\x00\x69\x00\x7a\x00"}, /* _.s.i.z. */ \
+ {0x000004a0, "\x65\x00\x0a\x00\x00\x00\x45\x00"}, /* e.....E. */ \
+ {0x000004a8, "\x46\x00\x49\x00\x20\x00\x61\x00"}, /* F.I. .a. */ \
+ {0x000004b0, "\x70\x00\x70\x00\x6c\x00\x69\x00"}, /* p.p.l.i. */ \
+ {0x000004b8, "\x63\x00\x61\x00\x74\x00\x69\x00"}, /* c.a.t.i. */ \
+ {0x000004c0, "\x6f\x00\x6e\x00\x20\x00\x63\x00"}, /* o.n. .c. */ \
+ {0x000004c8, "\x61\x00\x6c\x00\x6c\x00\x69\x00"}, /* a.l.l.i. */ \
+ {0x000004d0, "\x6e\x00\x67\x00\x20\x00\x45\x00"}, /* n.g. .E. */ \
+ {0x000004d8, "\x78\x00\x69\x00\x74\x00\x0a\x00"}, /* x.i.t... */ \
+ {0x000004e0, "\x00\x00\x4c\x00\x6f\x00\x61\x00"}, /* ..L.o.a. */ \
+ {0x000004e8, "\x64\x00\x65\x00\x64\x00\x20\x00"}, /* d.e.d. . */ \
+ {0x000004f0, "\x69\x00\x6d\x00\x61\x00\x67\x00"}, /* i.m.a.g. */ \
+ {0x000004f8, "\x65\x00\x20\x00\x70\x00\x72\x00"}, /* e. .p.r. */ \
+ {0x00000500, "\x6f\x00\x74\x00\x6f\x00\x63\x00"}, /* o.t.o.c. */ \
+ {0x00000508, "\x6f\x00\x6c\x00\x20\x00\x6d\x00"}, /* o.l. .m. */ \
+ {0x00000510, "\x69\x00\x73\x00\x73\x00\x69\x00"}, /* i.s.s.i. */ \
+ {0x00000518, "\x6e\x00\x67\x00\x0a\x00\x00\x00"}, /* n.g..... */ \
+ {0x00000520, "\x53\x00\x55\x00\x43\x00\x43\x00"}, /* S.U.C.C. */ \
+ {0x00000528, "\x45\x00\x53\x00\x53\x00\x00\x00"}, /* E.S.S... */ \
+ {0x00000530, "\x10\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000540, "\x04\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000548, "\xb0\x20\x00\x00\x00\x00\x00\x00"}, /* . ...... */ \
+ {0x00000550, "\x05\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000558, "\x00\x20\x00\x00\x00\x00\x00\x00"}, /* . ...... */ \
+ {0x00000560, "\x06\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000568, "\x00\x10\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000570, "\x0a\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000578, "\xaa\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000580, "\x0b\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000588, "\x18\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000005f0, "\xa1\x31\x1b\x5b\x62\x95\xd2\x11"}, /* .1.[b... */ \
+ {0x000005f8, "\x8e\x3f\x00\xa0\xc9\x69\x72\x3b"}, /* .?...ir; */ \
+ {0x00000618, "\x30\x05\x00\x00\x00\x00\x00\x00"}, /* 0....... */ \
+ {0x00001018, "\x00\x00\x00\x00\x03\x00\x01\x00"}, /* ........ */ \
+ {0x00001030, "\x00\x00\x00\x00\x03\x00\x03\x00"}, /* ........ */ \
+ {0x00001038, "\xf0\x05\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00001048, "\x33\x00\x00\x00\x12\x00\x01\x00"}, /* 3....... */ \
+ {0x00001050, "\xac\x03\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00001058, "\x40\x00\x00\x00\x00\x00\x00\x00"}, /* @....... */ \
+ {0x00001060, "\x5b\x00\x00\x00\x12\x00\x01\x00"}, /* [....... */ \
+ {0x00001068, "\x10\x04\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00001070, "\x04\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00001078, "\x79\x00\x00\x00\x10\x00\x01\x00"}, /* y....... */ \
+ {0x00001080, "\x30\x05\x00\x00\x00\x00\x00\x00"}, /* 0....... */ \
+ {0x00001090, "\x01\x00\x00\x00\x12\x00\x01\x00"}, /* ........ */ \
+ {0x00001098, "\x20\x02\x00\x00\x00\x00\x00\x00"}, /* ....... */ \
+ {0x000010a0, "\xa8\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000010a8, "\x0a\x00\x00\x00\x12\x00\x01\x00"}, /* ........ */ \
+ {0x000010b0, "\xec\x03\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000010b8, "\x04\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000010c0, "\x96\x00\x00\x00\x10\x00\x03\x00"}, /* ........ */ \
+ {0x000010c8, "\x20\x06\x00\x00\x00\x00\x00\x00"}, /* ....... */ \
+ {0x000010d8, "\x22\x00\x00\x00\x12\x00\x01\x00"}, /* "....... */ \
+ {0x000010e0, "\xc8\x02\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000010e8, "\xb0\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000010f0, "\x91\x00\x00\x00\x10\x00\x03\x00"}, /* ........ */ \
+ {0x000010f8, "\x20\x06\x00\x00\x00\x00\x00\x00"}, /* ....... */ \
+ {0x00001108, "\x2c\x00\x00\x00\x12\x00\x01\x00"}, /* ,....... */ \
+ {0x00001110, "\x78\x03\x00\x00\x00\x00\x00\x00"}, /* x....... */ \
+ {0x00001118, "\x34\x00\x00\x00\x00\x00\x00\x00"}, /* 4....... */ \
+ {0x00001120, "\x73\x00\x00\x00\x10\x00\x01\x00"}, /* s....... */ \
+ {0x00001138, "\x9f\x00\x00\x00\x10\x00\x03\x00"}, /* ........ */ \
+ {0x00001140, "\xf0\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00001150, "\x11\x00\x00\x00\x10\x00\x01\x00"}, /* ........ */ \
+ {0x00001168, "\x42\x00\x00\x00\x12\x00\x01\x00"}, /* B....... */ \
+ {0x00001170, "\x0c\x04\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00001178, "\x04\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00001180, "\x3b\x00\x00\x00\x12\x00\x01\x00"}, /* ;....... */ \
+ {0x00001188, "\xf0\x03\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00001190, "\x1c\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00001198, "\x8b\x00\x00\x00\x10\x00\x03\x00"}, /* ........ */ \
+ {0x000011a0, "\xf0\x05\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000011b0, "\x1b\x00\x00\x00\x10\x00\x03\x00"}, /* ........ */ \
+ {0x000011b8, "\x20\x06\x00\x00\x00\x00\x00\x00"}, /* ....... */ \
+ {0x000011c8, "\x80\x00\x00\x00\x10\x00\xf1\xff"}, /* ........ */ \
+ {0x000011d0, "\x30\x05\x00\x00\x00\x00\x00\x00"}, /* 0....... */ \
+ {0, NULL} } }
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * This file contains a precompiled EFI binary built from
+ * lib/efi_selftest/efi_miniapp_file_image_exit.c and converted to an include
+ * using tools/file2include. It is used to testing the EFI_TCG2_PROTOCOL.
+ * The precompiled form is needed to avoid the problem of reproducible builds.
+ */
+
+#define EFI_ST_DISK_IMG { 0x00001200, { \
+ {0x00000000, "\x4d\x5a\x90\x00\x03\x00\x00\x00"}, /* MZ...... */ \
+ {0x00000008, "\x04\x00\x00\x00\xff\xff\x00\x00"}, /* ........ */ \
+ {0x00000010, "\xb8\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000018, "\x40\x00\x00\x00\x00\x00\x00\x00"}, /* @....... */ \
+ {0x00000038, "\x00\x00\x00\x00\x80\x00\x00\x00"}, /* ........ */ \
+ {0x00000040, "\x0e\x1f\xba\x0e\x00\xb4\x09\xcd"}, /* ........ */ \
+ {0x00000048, "\x21\xb8\x01\x4c\xcd\x21\x54\x68"}, /* !..L.!Th */ \
+ {0x00000050, "\x69\x73\x20\x70\x72\x6f\x67\x72"}, /* is progr */ \
+ {0x00000058, "\x61\x6d\x20\x63\x61\x6e\x6e\x6f"}, /* am canno */ \
+ {0x00000060, "\x74\x20\x62\x65\x20\x72\x75\x6e"}, /* t be run */ \
+ {0x00000068, "\x20\x69\x6e\x20\x44\x4f\x53\x20"}, /* in DOS */ \
+ {0x00000070, "\x6d\x6f\x64\x65\x2e\x0d\x0d\x0a"}, /* mode.... */ \
+ {0x00000078, "\x24\x00\x00\x00\x00\x00\x00\x00"}, /* $....... */ \
+ {0x00000080, "\x50\x45\x00\x00\x4c\x01\x06\x00"}, /* PE..L... */ \
+ {0x00000090, "\x00\x00\x00\x00\xe0\x00\x0e\x03"}, /* ........ */ \
+ {0x00000098, "\x0b\x01\x02\x1e\x00\x04\x00\x00"}, /* ........ */ \
+ {0x000000a0, "\x00\x0a\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000000a8, "\x00\x10\x00\x00\x00\x10\x00\x00"}, /* ........ */ \
+ {0x000000b0, "\x00\x30\x00\x00\x00\x00\x00\x00"}, /* .0...... */ \
+ {0x000000b8, "\x00\x10\x00\x00\x00\x02\x00\x00"}, /* ........ */ \
+ {0x000000d0, "\x00\x70\x00\x00\x00\x04\x00\x00"}, /* .p...... */ \
+ {0x000000d8, "\x6c\xdf\x00\x00\x0a\x00\x00\x00"}, /* l....... */ \
+ {0x000000f0, "\x00\x00\x00\x00\x10\x00\x00\x00"}, /* ........ */ \
+ {0x00000120, "\x00\x50\x00\x00\x0a\x00\x00\x00"}, /* .P...... */ \
+ {0x00000178, "\x2e\x74\x65\x78\x74\x00\x00\x00"}, /* .text... */ \
+ {0x00000180, "\x1b\x02\x00\x00\x00\x10\x00\x00"}, /* ........ */ \
+ {0x00000188, "\x00\x04\x00\x00\x00\x04\x00\x00"}, /* ........ */ \
+ {0x00000198, "\x00\x00\x00\x00\x20\x00\x30\x60"}, /* .... .0` */ \
+ {0x000001a0, "\x2e\x73\x64\x61\x74\x61\x00\x00"}, /* .sdata.. */ \
+ {0x000001a8, "\x0c\x00\x00\x00\x00\x20\x00\x00"}, /* ..... .. */ \
+ {0x000001b0, "\x00\x02\x00\x00\x00\x08\x00\x00"}, /* ........ */ \
+ {0x000001c0, "\x00\x00\x00\x00\x40\x00\x30\xc0"}, /* ....@.0. */ \
+ {0x000001c8, "\x2e\x64\x61\x74\x61\x00\x00\x00"}, /* .data... */ \
+ {0x000001d0, "\x38\x01\x00\x00\x00\x30\x00\x00"}, /* 8....0.. */ \
+ {0x000001d8, "\x00\x02\x00\x00\x00\x0a\x00\x00"}, /* ........ */ \
+ {0x000001e8, "\x00\x00\x00\x00\x40\x00\x40\xc0"}, /* ....@.@. */ \
+ {0x000001f0, "\x2e\x64\x79\x6e\x61\x6d\x69\x63"}, /* .dynamic */ \
+ {0x000001f8, "\x70\x00\x00\x00\x00\x40\x00\x00"}, /* p....@.. */ \
+ {0x00000200, "\x00\x02\x00\x00\x00\x0c\x00\x00"}, /* ........ */ \
+ {0x00000210, "\x00\x00\x00\x00\x40\x00\x30\xc0"}, /* ....@.0. */ \
+ {0x00000218, "\x2e\x72\x65\x6c\x6f\x63\x00\x00"}, /* .reloc.. */ \
+ {0x00000220, "\x0a\x00\x00\x00\x00\x50\x00\x00"}, /* .....P.. */ \
+ {0x00000228, "\x00\x02\x00\x00\x00\x0e\x00\x00"}, /* ........ */ \
+ {0x00000238, "\x00\x00\x00\x00\x40\x00\x10\x42"}, /* ....@..B */ \
+ {0x00000240, "\x2e\x64\x79\x6e\x73\x79\x6d\x00"}, /* .dynsym. */ \
+ {0x00000248, "\x30\x00\x00\x00\x00\x60\x00\x00"}, /* 0....`.. */ \
+ {0x00000250, "\x00\x02\x00\x00\x00\x10\x00\x00"}, /* ........ */ \
+ {0x00000260, "\x00\x00\x00\x00\x40\x00\x30\x40"}, /* ....@.0@ */ \
+ {0x00000400, "\x55\x89\xe5\xff\x75\x0c\xff\x75"}, /* U...u..u */ \
+ {0x00000408, "\x08\xe8\x00\x00\x00\x00\x58\x89"}, /* ......X. */ \
+ {0x00000410, "\xc3\x05\xf2\xef\xff\xff\x81\xc3"}, /* ........ */ \
+ {0x00000418, "\xf2\x2f\x00\x00\x53\x50\xe8\x20"}, /* ./..SP. */ \
+ {0x00000420, "\x01\x00\x00\x5b\x5b\x85\xc0\x75"}, /* ...[[..u */ \
+ {0x00000428, "\x05\xe8\x8a\x00\x00\x00\xc9\xc3"}, /* ........ */ \
+ {0x00000430, "\x57\x56\x53\x83\xec\x18\xe8\x00"}, /* WVS..... */ \
+ {0x00000438, "\x01\x00\x00\x81\xc6\xc5\x0f\x00"}, /* ........ */ \
+ {0x00000440, "\x00\x8b\x44\x24\x2c\x8b\x58\x2c"}, /* ..D$,.X, */ \
+ {0x00000448, "\x8b\x40\x3c\x6a\x02\x6a\x00\x6a"}, /* .@<j.j.j */ \
+ {0x00000450, "\x00\x8d\x54\x24\x20\x52\x8d\x96"}, /* ..T$ R.. */ \
+ {0x00000458, "\x28\x11\x00\x00\x52\xff\x74\x24"}, /* (...R.t$ */ \
+ {0x00000460, "\x3c\xff\x90\x98\x00\x00\x00\x89"}, /* <....... */ \
+ {0x00000468, "\xc7\x83\xc4\x20\x85\xc0\x74\x12"}, /* ... ..t. */ \
+ {0x00000470, "\x52\x52\x8d\x86\x02\x10\x00\x00"}, /* RR...... */ \
+ {0x00000478, "\x50\x53\xff\x53\x04\x83\xc4\x10"}, /* PS.S.... */ \
+ {0x00000480, "\xeb\x2d\x8b\x4c\x24\x0c\x8b\x41"}, /* .-.L$..A */ \
+ {0x00000488, "\x20\x8d\x96\x30\xf0\xff\xff\x39"}, /* ..0...9 */ \
+ {0x00000490, "\xd0\x77\x07\x03\x41\x28\x39\xd0"}, /* .w..A(9. */ \
+ {0x00000498, "\x77\x15\x50\x50\x8d\x86\x4c\x10"}, /* w.PP..L. */ \
+ {0x000004a0, "\x00\x00\x50\x53\xff\x53\x04\x83"}, /* ..PS.S.. */ \
+ {0x000004a8, "\xc4\x10\xbf\x0e\x00\x00\x80\x89"}, /* ........ */ \
+ {0x000004b0, "\xf8\x83\xc4\x10\x5b\x5e\x5f\xc3"}, /* ....[^_. */ \
+ {0x000004b8, "\x55\x57\x56\x53\x83\xec\x1c\xe8"}, /* UWVS.... */ \
+ {0x000004c0, "\x7b\x00\x00\x00\x81\xc5\x3c\x0f"}, /* {.....<. */ \
+ {0x000004c8, "\x00\x00\x8b\x44\x24\x34\x8b\x58"}, /* ...D$4.X */ \
+ {0x000004d0, "\x2c\x89\xe7\x8d\xb5\x0e\x11\x00"}, /* ,....... */ \
+ {0x000004d8, "\x00\xb9\x04\x00\x00\x00\xf3\xa5"}, /* ........ */ \
+ {0x000004e0, "\x52\x52\x8d\x85\x94\x10\x00\x00"}, /* RR...... */ \
+ {0x000004e8, "\x50\x53\xff\x53\x04\x59\x5e\xff"}, /* PS.S.Y^. */ \
+ {0x000004f0, "\x74\x24\x3c\xff\x74\x24\x3c\xe8"}, /* t$<.t$<. */ \
+ {0x000004f8, "\x34\xff\xff\xff\x83\xc4\x10\xba"}, /* 4....... */ \
+ {0x00000500, "\x03\x00\x00\x80\x85\xc0\x74\x15"}, /* ......t. */ \
+ {0x00000508, "\x50\x50\x8d\x85\xd0\x10\x00\x00"}, /* PP...... */ \
+ {0x00000510, "\x50\x53\xff\x53\x04\x83\xc4\x10"}, /* PS.S.... */ \
+ {0x00000518, "\xba\x0e\x00\x00\x80\x8b\x44\x24"}, /* ......D$ */ \
+ {0x00000520, "\x34\x8b\x40\x3c\x89\xe1\x51\x6a"}, /* 4.@<..Qj */ \
+ {0x00000528, "\x10\x52\xff\x74\x24\x3c\xff\x50"}, /* .R.t$<.P */ \
+ {0x00000530, "\x78\x31\xc0\x83\xc4\x2c\x5b\x5e"}, /* x1...,[^ */ \
+ {0x00000538, "\x5f\x5d\xc3\x8b\x34\x24\xc3\x8b"}, /* _]..4$.. */ \
+ {0x00000540, "\x2c\x24\xc3\x57\x56\x53\x8b\x7c"}, /* ,$.WVS.| */ \
+ {0x00000548, "\x24\x10\x8b\x44\x24\x14\x83\xc0"}, /* $..D$... */ \
+ {0x00000550, "\x04\x31\xd2\x31\xc9\x31\xdb\x8b"}, /* .1.1.1.. */ \
+ {0x00000558, "\x70\xfc\x85\xf6\x74\x20\x83\xfe"}, /* p...t .. */ \
+ {0x00000560, "\x12\x74\x10\x83\xfe\x13\x74\x0f"}, /* .t....t. */ \
+ {0x00000568, "\x83\xfe\x11\x75\x0c\x8b\x10\x01"}, /* ...u.... */ \
+ {0x00000570, "\xfa\xeb\x06\x8b\x18\xeb\x02\x8b"}, /* ........ */ \
+ {0x00000578, "\x08\x83\xc0\x08\xeb\xd9\xb8\x01"}, /* ........ */ \
+ {0x00000580, "\x00\x00\x80\x85\xd2\x75\x08\x85"}, /* .....u.. */ \
+ {0x00000588, "\xc9\x75\x1e\x31\xc0\xeb\x1a\x85"}, /* .u.1.... */ \
+ {0x00000590, "\xc9\x74\x16\x85\xdb\x7e\xf4\x80"}, /* .t...~.. */ \
+ {0x00000598, "\x7a\x04\x08\x75\x06\x8b\x02\x01"}, /* z..u.... */ \
+ {0x000005a0, "\xf8\x01\x38\x01\xca\x29\xcb\xeb"}, /* ..8..).. */ \
+ {0x000005a8, "\xea\x5b\x5e\x5f\xc3\x57\x56\x53"}, /* .[^_.WVS */ \
+ {0x000005b0, "\x53\x89\xc7\x31\xf6\x39\xf1\x74"}, /* S..1.9.t */ \
+ {0x000005b8, "\x1c\x8a\x1c\x37\x46\x8a\x44\x32"}, /* ...7F.D2 */ \
+ {0x000005c0, "\xff\x88\x44\x24\x03\x38\xc3\x74"}, /* ..D$.8.t */ \
+ {0x000005c8, "\xec\x0f\xb6\xc3\x0f\xb6\x54\x24"}, /* ......T$ */ \
+ {0x000005d0, "\x03\x29\xd0\xeb\x02\x31\xc0\x5a"}, /* .)...1.Z */ \
+ {0x000005d8, "\x5b\x5e\x5f\xc3\x56\x53\x89\xce"}, /* [^_.VS.. */ \
+ {0x000005e0, "\x39\xd0\x77\x0f\x31\xdb\x39\xde"}, /* 9.w.1.9. */ \
+ {0x000005e8, "\x74\x18\x8a\x0c\x1a\x88\x0c\x18"}, /* t....... */ \
+ {0x000005f0, "\x43\xeb\xf3\x85\xf6\x74\x0b\x8a"}, /* C....t.. */ \
+ {0x000005f8, "\x5c\x32\xff\x88\x5c\x30\xff\x4e"}, /* \2..\0.N */ \
+ {0x00000600, "\xeb\xf1\x5b\x5e\xc3\xe9\xd2\xff"}, /* ..[^.... */ \
+ {0x00000608, "\xff\xff\x53\x31\xdb\x39\xd9\x74"}, /* ..S1.9.t */ \
+ {0x00000610, "\x06\x88\x14\x18\x43\xeb\xf6\x5b"}, /* ....C..[ */ \
+ {0x00000618, "\xc3\xc3\xc3\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000800, "\x00\x40\x00\x00\x00\x00\x00\x00"}, /* .@...... */ \
+ {0x00000a00, "\x00\x00\x43\x00\x6f\x00\x75\x00"}, /* ..C.o.u. */ \
+ {0x00000a08, "\x6c\x00\x64\x00\x20\x00\x6e\x00"}, /* l.d. .n. */ \
+ {0x00000a10, "\x6f\x00\x74\x00\x20\x00\x6f\x00"}, /* o.t. .o. */ \
+ {0x00000a18, "\x70\x00\x65\x00\x6e\x00\x20\x00"}, /* p.e.n. . */ \
+ {0x00000a20, "\x6c\x00\x6f\x00\x61\x00\x64\x00"}, /* l.o.a.d. */ \
+ {0x00000a28, "\x65\x00\x64\x00\x20\x00\x69\x00"}, /* e.d. .i. */ \
+ {0x00000a30, "\x6d\x00\x61\x00\x67\x00\x65\x00"}, /* m.a.g.e. */ \
+ {0x00000a38, "\x20\x00\x70\x00\x72\x00\x6f\x00"}, /* .p.r.o. */ \
+ {0x00000a40, "\x74\x00\x6f\x00\x63\x00\x6f\x00"}, /* t.o.c.o. */ \
+ {0x00000a48, "\x6c\x00\x00\x00\x49\x00\x6e\x00"}, /* l...I.n. */ \
+ {0x00000a50, "\x63\x00\x6f\x00\x72\x00\x72\x00"}, /* c.o.r.r. */ \
+ {0x00000a58, "\x65\x00\x63\x00\x74\x00\x20\x00"}, /* e.c.t. . */ \
+ {0x00000a60, "\x69\x00\x6d\x00\x61\x00\x67\x00"}, /* i.m.a.g. */ \
+ {0x00000a68, "\x65\x00\x5f\x00\x62\x00\x61\x00"}, /* e._.b.a. */ \
+ {0x00000a70, "\x73\x00\x65\x00\x20\x00\x6f\x00"}, /* s.e. .o. */ \
+ {0x00000a78, "\x72\x00\x20\x00\x69\x00\x6d\x00"}, /* r. .i.m. */ \
+ {0x00000a80, "\x61\x00\x67\x00\x65\x00\x5f\x00"}, /* a.g.e._. */ \
+ {0x00000a88, "\x73\x00\x69\x00\x7a\x00\x65\x00"}, /* s.i.z.e. */ \
+ {0x00000a90, "\x0a\x00\x00\x00\x45\x00\x46\x00"}, /* ....E.F. */ \
+ {0x00000a98, "\x49\x00\x20\x00\x61\x00\x70\x00"}, /* I. .a.p. */ \
+ {0x00000aa0, "\x70\x00\x6c\x00\x69\x00\x63\x00"}, /* p.l.i.c. */ \
+ {0x00000aa8, "\x61\x00\x74\x00\x69\x00\x6f\x00"}, /* a.t.i.o. */ \
+ {0x00000ab0, "\x6e\x00\x20\x00\x63\x00\x61\x00"}, /* n. .c.a. */ \
+ {0x00000ab8, "\x6c\x00\x6c\x00\x69\x00\x6e\x00"}, /* l.l.i.n. */ \
+ {0x00000ac0, "\x67\x00\x20\x00\x45\x00\x78\x00"}, /* g. .E.x. */ \
+ {0x00000ac8, "\x69\x00\x74\x00\x0a\x00\x00\x00"}, /* i.t..... */ \
+ {0x00000ad0, "\x4c\x00\x6f\x00\x61\x00\x64\x00"}, /* L.o.a.d. */ \
+ {0x00000ad8, "\x65\x00\x64\x00\x20\x00\x69\x00"}, /* e.d. .i. */ \
+ {0x00000ae0, "\x6d\x00\x61\x00\x67\x00\x65\x00"}, /* m.a.g.e. */ \
+ {0x00000ae8, "\x20\x00\x70\x00\x72\x00\x6f\x00"}, /* .p.r.o. */ \
+ {0x00000af0, "\x74\x00\x6f\x00\x63\x00\x6f\x00"}, /* t.o.c.o. */ \
+ {0x00000af8, "\x6c\x00\x20\x00\x6d\x00\x69\x00"}, /* l. .m.i. */ \
+ {0x00000b00, "\x73\x00\x73\x00\x69\x00\x6e\x00"}, /* s.s.i.n. */ \
+ {0x00000b08, "\x67\x00\x0a\x00\x00\x00\x53\x00"}, /* g.....S. */ \
+ {0x00000b10, "\x55\x00\x43\x00\x43\x00\x45\x00"}, /* U.C.C.E. */ \
+ {0x00000b18, "\x53\x00\x53\x00\x00\x00\x00\x00"}, /* S.S..... */ \
+ {0x00000b28, "\xa1\x31\x1b\x5b\x62\x95\xd2\x11"}, /* .1.[b... */ \
+ {0x00000b30, "\x8e\x3f\x00\xa0\xc9\x69\x72\x3b"}, /* .?...ir; */ \
+ {0x00000c00, "\x10\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000c08, "\x04\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000c10, "\xf5\xfe\xff\x6f\x14\x70\x00\x00"}, /* ...o.p.. */ \
+ {0x00000c18, "\x05\x00\x00\x00\x00\x70\x00\x00"}, /* .....p.. */ \
+ {0x00000c20, "\x06\x00\x00\x00\x00\x60\x00\x00"}, /* .....`.. */ \
+ {0x00000c28, "\x0a\x00\x00\x00\x13\x00\x00\x00"}, /* ........ */ \
+ {0x00000c30, "\x0b\x00\x00\x00\x10\x00\x00\x00"}, /* ........ */ \
+ {0x00000c38, "\x1e\x00\x00\x00\x02\x00\x00\x00"}, /* ........ */ \
+ {0x00000e00, "\x20\x31\x00\x00\x0a\x00\x00\x00"}, /* 1...... */ \
+ {0x00001010, "\x01\x00\x00\x00\x00\x10\x00\x00"}, /* ........ */ \
+ {0x00001018, "\x00\x00\x00\x00\x10\x00\x02\x00"}, /* ........ */ \
+ {0x00001020, "\x08\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00001028, "\x00\x00\x00\x00\x10\x00\x01\x00"}, /* ........ */ \
+ {0, NULL} } }
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * This file contains a precompiled EFI binary built from
+ * lib/efi_selftest/efi_miniapp_file_image_exit.c and converted to an include
+ * using tools/file2include. It is used to testing the EFI_TCG2_PROTOCOL.
+ * The precompiled form is needed to avoid the problem of reproducible builds.
+ */
+
+#define EFI_ST_DISK_IMG { 0x00001130, { \
+ {0x00000000, "\x4d\x5a\x00\x00\x00\x00\x00\x00"}, /* MZ...... */ \
+ {0x00000030, "\x52\x49\x53\x43\x56\x00\x00\x00"}, /* RISCV... */ \
+ {0x00000038, "\x52\x53\x43\x05\x40\x00\x00\x00"}, /* RSC.@... */ \
+ {0x00000040, "\x50\x45\x00\x00\x32\x50\x02\x00"}, /* PE..2P.. */ \
+ {0x00000050, "\x00\x00\x00\x00\xe0\x00\x0e\x02"}, /* ........ */ \
+ {0x00000058, "\x0b\x01\x02\x14\xb8\x03\x00\x00"}, /* ........ */ \
+ {0x00000068, "\x88\x01\x00\x00\x88\x01\x00\x00"}, /* ........ */ \
+ {0x00000078, "\x20\x00\x00\x00\x08\x00\x00\x00"}, /* ....... */ \
+ {0x00000080, "\x00\x00\x00\x00\x01\x00\x00\x00"}, /* ........ */ \
+ {0x00000090, "\x40\x05\x00\x00\x88\x01\x00\x00"}, /* @....... */ \
+ {0x00000098, "\x00\x00\x00\x00\x0a\x00\x00\x00"}, /* ........ */ \
+ {0x000000b0, "\x00\x00\x00\x00\x06\x00\x00\x00"}, /* ........ */ \
+ {0x00000138, "\x2e\x72\x65\x6c\x6f\x63\x00\x00"}, /* .reloc.. */ \
+ {0x00000158, "\x00\x00\x00\x00\x40\x00\x10\x42"}, /* ....@..B */ \
+ {0x00000160, "\x2e\x74\x65\x78\x74\x00\x00\x00"}, /* .text... */ \
+ {0x00000168, "\xb8\x03\x00\x00\x88\x01\x00\x00"}, /* ........ */ \
+ {0x00000170, "\xb8\x03\x00\x00\x88\x01\x00\x00"}, /* ........ */ \
+ {0x00000180, "\x00\x00\x00\x00\x20\x00\x50\xe0"}, /* .... .P. */ \
+ {0x00000188, "\x51\x11\x2a\xc0\x2e\xc2\x06\xc4"}, /* Q....... */ \
+ {0x00000190, "\x17\x05\x00\x00\x13\x05\x05\xe7"}, /* ........ */ \
+ {0x00000198, "\x97\x05\x00\x00\x93\x85\x85\x30"}, /* .......0 */ \
+ {0x000001a0, "\xe5\x28\x09\xe5\x92\x45\x02\x45"}, /* .(...E.E */ \
+ {0x000001a8, "\x9d\x28\xa2\x40\x31\x01\x82\x80"}, /* .(.@1... */ \
+ {0x000001b0, "\x01\x11\x22\xcc\x06\xce\x26\xca"}, /* .."...&. */ \
+ {0x000001b8, "\xdc\x5d\xc4\x55\x01\x47\x03\xa8"}, /* .].U.G.. */ \
+ {0x000001c0, "\x87\x09\x81\x46\x89\x47\x70\x00"}, /* ...F.Gp. */ \
+ {0x000001c8, "\x97\x05\x00\x00\x93\x85\x85\x35"}, /* .......5 */ \
+ {0x000001d0, "\x02\x98\x2a\x84\x11\xcd\xdc\x40"}, /* .......@ */ \
+ {0x000001d8, "\x97\x05\x00\x00\x93\x85\x05\x1a"}, /* ........ */ \
+ {0x000001e0, "\x26\x85\x82\x97\xf2\x40\x22\x85"}, /* &....@". */ \
+ {0x000001e8, "\x62\x44\xd2\x44\x05\x61\x82\x80"}, /* bD.D.a.. */ \
+ {0x000001f0, "\xb2\x46\x17\x07\x00\x00\x13\x07"}, /* .F...... */ \
+ {0x000001f8, "\xe7\xfb\x9c\x52\x63\x66\xf7\x00"}, /* ...Rcf.. */ \
+ {0x00000200, "\x94\x56\xb6\x97\xe3\x60\xf7\xfe"}, /* .V...`.. */ \
+ {0x00000208, "\xdc\x40\x97\x05\x00\x00\x93\x85"}, /* .@...... */ \
+ {0x00000210, "\xa5\x1b\x26\x85\x37\x04\x00\x80"}, /* ..&.7... */ \
+ {0x00000218, "\x82\x97\x39\x04\xe1\xb7\x79\x71"}, /* ..9...yq */ \
+ {0x00000220, "\x06\xd6\x22\xd4\x26\xd2\x4e\xce"}, /* ..".&.N. */ \
+ {0x00000228, "\x4a\xd0\x03\xa9\xc5\x02\x8a\x89"}, /* J....... */ \
+ {0x00000230, "\xaa\x84\x2e\x84\x41\x46\x97\x05"}, /* ....AF.. */ \
+ {0x00000238, "\x00\x00\x93\x85\x25\x25\x4e\x85"}, /* ....%%N. */ \
+ {0x00000240, "\x39\x2a\x83\x27\x49\x00\x97\x05"}, /* 9..'I... */ \
+ {0x00000248, "\x00\x00\x93\x85\x65\x1c\x4a\x85"}, /* ....e.J. */ \
+ {0x00000250, "\x82\x97\xa2\x85\x26\x85\xa9\x3f"}, /* ....&..? */ \
+ {0x00000258, "\x1d\xc9\x83\x27\x49\x00\x97\x05"}, /* ...'I... */ \
+ {0x00000260, "\x00\x00\x93\x85\xa5\x1e\x4a\x85"}, /* ......J. */ \
+ {0x00000268, "\x82\x97\xb7\x07\x00\x80\x93\x85"}, /* ........ */ \
+ {0x00000270, "\xe7\x00\x5c\x5c\xce\x86\x26\x85"}, /* ..\\..&. */ \
+ {0x00000278, "\xbc\x5f\x41\x46\x82\x97\xb2\x50"}, /* ._AF...P */ \
+ {0x00000280, "\x22\x54\x92\x54\x02\x59\xf2\x49"}, /* "T.T.Y.I */ \
+ {0x00000288, "\x01\x45\x45\x61\x82\x80\xb7\x07"}, /* .EEa.... */ \
+ {0x00000290, "\x00\x80\x93\x85\x37\x00\xf1\xbf"}, /* ....7... */ \
+ {0x00000298, "\x81\x47\x01\x47\x81\x46\x21\x48"}, /* .G.G.F!H */ \
+ {0x000002a0, "\xa5\x48\x1d\x43\x90\x41\x09\xe6"}, /* .H.C.A.. */ \
+ {0x000002a8, "\x95\xe3\x1d\xe3\x01\x45\x82\x80"}, /* .....E.. */ \
+ {0x000002b0, "\x63\x0a\x06\x01\x63\x0a\x16\x01"}, /* c...c... */ \
+ {0x000002b8, "\x63\x14\x66\x00\xdc\x41\xaa\x97"}, /* c.f..A.. */ \
+ {0x000002c0, "\xa1\x05\xcd\xb7\xd4\x41\xed\xbf"}, /* .....A.. */ \
+ {0x000002c8, "\xd8\x41\xdd\xbf\x0d\x48\x05\xe3"}, /* .A...H.. */ \
+ {0x000002d0, "\x37\x05\x00\x80\x05\x05\x82\x80"}, /* 7....... */ \
+ {0x000002d8, "\x03\xc6\x47\x00\x63\x1c\x06\x01"}, /* ..G.c... */ \
+ {0x000002e0, "\x90\x43\x8c\x47\x99\x8e\x2a\x96"}, /* .C.G.... */ \
+ {0x000002e8, "\xaa\x95\x0c\xc2\xba\x97\xe3\x45"}, /* .......E */ \
+ {0x000002f0, "\xd0\xfe\x6d\xbf\x01\xa0\x01\x47"}, /* ..m....G */ \
+ {0x000002f8, "\x63\x14\xe6\x00\x01\x45\x82\x80"}, /* c....E.. */ \
+ {0x00000300, "\xb3\x07\xe5\x00\x05\x07\xb3\x86"}, /* ........ */ \
+ {0x00000308, "\xe5\x00\x83\xc7\x07\x00\x83\xc6"}, /* ........ */ \
+ {0x00000310, "\xf6\xff\xe3\x83\xd7\xfe\x33\x85"}, /* ......3. */ \
+ {0x00000318, "\xd7\x40\x82\x80\x63\xf5\xa5\x02"}, /* .@..c... */ \
+ {0x00000320, "\x93\x46\xf6\xff\x81\x47\xfd\x17"}, /* .F...G.. */ \
+ {0x00000328, "\x63\x91\xd7\x02\x82\x80\x33\x87"}, /* c.....3. */ \
+ {0x00000330, "\xf5\x00\x83\x46\x07\x00\x33\x07"}, /* ...F..3. */ \
+ {0x00000338, "\xf5\x00\x85\x07\x23\x00\xd7\x00"}, /* ....#... */ \
+ {0x00000340, "\xe3\x97\xc7\xfe\x82\x80\x81\x47"}, /* .......G */ \
+ {0x00000348, "\xe5\xbf\x33\x07\xf6\x00\x33\x88"}, /* ..3...3. */ \
+ {0x00000350, "\xe5\x00\x03\x48\x08\x00\x2a\x97"}, /* ...H.... */ \
+ {0x00000358, "\x23\x00\x07\x01\xe9\xb7\x7d\xbf"}, /* #.....}. */ \
+ {0x00000360, "\x2a\x96\xaa\x87\x63\x93\xc7\x00"}, /* ....c... */ \
+ {0x00000368, "\x82\x80\x85\x07\xa3\x8f\xb7\xfe"}, /* ........ */ \
+ {0x00000370, "\xd5\xbf\x82\x80\x82\x80\x00\x00"}, /* ........ */ \
+ {0x00000378, "\x43\x00\x6f\x00\x75\x00\x6c\x00"}, /* C.o.u.l. */ \
+ {0x00000380, "\x64\x00\x20\x00\x6e\x00\x6f\x00"}, /* d. .n.o. */ \
+ {0x00000388, "\x74\x00\x20\x00\x6f\x00\x70\x00"}, /* t. .o.p. */ \
+ {0x00000390, "\x65\x00\x6e\x00\x20\x00\x6c\x00"}, /* e.n. .l. */ \
+ {0x00000398, "\x6f\x00\x61\x00\x64\x00\x65\x00"}, /* o.a.d.e. */ \
+ {0x000003a0, "\x64\x00\x20\x00\x69\x00\x6d\x00"}, /* d. .i.m. */ \
+ {0x000003a8, "\x61\x00\x67\x00\x65\x00\x20\x00"}, /* a.g.e. . */ \
+ {0x000003b0, "\x70\x00\x72\x00\x6f\x00\x74\x00"}, /* p.r.o.t. */ \
+ {0x000003b8, "\x6f\x00\x63\x00\x6f\x00\x6c\x00"}, /* o.c.o.l. */ \
+ {0x000003c0, "\x00\x00\x00\x00\x49\x00\x6e\x00"}, /* ....I.n. */ \
+ {0x000003c8, "\x63\x00\x6f\x00\x72\x00\x72\x00"}, /* c.o.r.r. */ \
+ {0x000003d0, "\x65\x00\x63\x00\x74\x00\x20\x00"}, /* e.c.t. . */ \
+ {0x000003d8, "\x69\x00\x6d\x00\x61\x00\x67\x00"}, /* i.m.a.g. */ \
+ {0x000003e0, "\x65\x00\x5f\x00\x62\x00\x61\x00"}, /* e._.b.a. */ \
+ {0x000003e8, "\x73\x00\x65\x00\x20\x00\x6f\x00"}, /* s.e. .o. */ \
+ {0x000003f0, "\x72\x00\x20\x00\x69\x00\x6d\x00"}, /* r. .i.m. */ \
+ {0x000003f8, "\x61\x00\x67\x00\x65\x00\x5f\x00"}, /* a.g.e._. */ \
+ {0x00000400, "\x73\x00\x69\x00\x7a\x00\x65\x00"}, /* s.i.z.e. */ \
+ {0x00000408, "\x0a\x00\x00\x00\x45\x00\x46\x00"}, /* ....E.F. */ \
+ {0x00000410, "\x49\x00\x20\x00\x61\x00\x70\x00"}, /* I. .a.p. */ \
+ {0x00000418, "\x70\x00\x6c\x00\x69\x00\x63\x00"}, /* p.l.i.c. */ \
+ {0x00000420, "\x61\x00\x74\x00\x69\x00\x6f\x00"}, /* a.t.i.o. */ \
+ {0x00000428, "\x6e\x00\x20\x00\x63\x00\x61\x00"}, /* n. .c.a. */ \
+ {0x00000430, "\x6c\x00\x6c\x00\x69\x00\x6e\x00"}, /* l.l.i.n. */ \
+ {0x00000438, "\x67\x00\x20\x00\x45\x00\x78\x00"}, /* g. .E.x. */ \
+ {0x00000440, "\x69\x00\x74\x00\x0a\x00\x00\x00"}, /* i.t..... */ \
+ {0x00000448, "\x4c\x00\x6f\x00\x61\x00\x64\x00"}, /* L.o.a.d. */ \
+ {0x00000450, "\x65\x00\x64\x00\x20\x00\x69\x00"}, /* e.d. .i. */ \
+ {0x00000458, "\x6d\x00\x61\x00\x67\x00\x65\x00"}, /* m.a.g.e. */ \
+ {0x00000460, "\x20\x00\x70\x00\x72\x00\x6f\x00"}, /* .p.r.o. */ \
+ {0x00000468, "\x74\x00\x6f\x00\x63\x00\x6f\x00"}, /* t.o.c.o. */ \
+ {0x00000470, "\x6c\x00\x20\x00\x6d\x00\x69\x00"}, /* l. .m.i. */ \
+ {0x00000478, "\x73\x00\x73\x00\x69\x00\x6e\x00"}, /* s.s.i.n. */ \
+ {0x00000480, "\x67\x00\x0a\x00\x00\x00\x00\x00"}, /* g....... */ \
+ {0x00000488, "\x53\x00\x55\x00\x43\x00\x43\x00"}, /* S.U.C.C. */ \
+ {0x00000490, "\x45\x00\x53\x00\x53\x00\x00\x00"}, /* E.S.S... */ \
+ {0x000004a0, "\x10\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000004a8, "\x04\x00\x00\x00\xac\x20\x00\x00"}, /* ..... .. */ \
+ {0x000004b0, "\xf5\xfe\xff\x6f\x44\x21\x00\x00"}, /* ...oD!.. */ \
+ {0x000004b8, "\x05\x00\x00\x00\x00\x20\x00\x00"}, /* ..... .. */ \
+ {0x000004c0, "\x06\x00\x00\x00\x00\x10\x00\x00"}, /* ........ */ \
+ {0x000004c8, "\x0a\x00\x00\x00\xaa\x00\x00\x00"}, /* ........ */ \
+ {0x000004d0, "\x0b\x00\x00\x00\x10\x00\x00\x00"}, /* ........ */ \
+ {0x000004d8, "\x07\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000004e0, "\x08\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000004e8, "\x09\x00\x00\x00\x0c\x00\x00\x00"}, /* ........ */ \
+ {0x00000520, "\xa1\x31\x1b\x5b\x62\x95\xd2\x11"}, /* .1.[b... */ \
+ {0x00000528, "\x8e\x3f\x00\xa0\xc9\x69\x72\x3b"}, /* .?...ir; */ \
+ {0x00000530, "\xa0\x04\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00001018, "\x00\x00\x00\x00\x03\x00\x01\x00"}, /* ........ */ \
+ {0x00001020, "\x42\x00\x00\x00\x72\x03\x00\x00"}, /* B...r... */ \
+ {0x00001028, "\x02\x00\x00\x00\x12\x00\x01\x00"}, /* ........ */ \
+ {0x00001030, "\x73\x00\x00\x00\x00\x00\x00\x00"}, /* s....... */ \
+ {0x00001038, "\x00\x00\x00\x00\x10\x00\x01\x00"}, /* ........ */ \
+ {0x00001040, "\x3b\x00\x00\x00\x60\x03\x00\x00"}, /* ;...`... */ \
+ {0x00001048, "\x12\x00\x00\x00\x12\x00\x01\x00"}, /* ........ */ \
+ {0x00001050, "\x96\x00\x00\x00\x40\x05\x00\x00"}, /* ....@... */ \
+ {0x00001058, "\x00\x00\x00\x00\x10\x00\x03\x00"}, /* ........ */ \
+ {0x00001060, "\x22\x00\x00\x00\x98\x02\x00\x00"}, /* "....... */ \
+ {0x00001068, "\x5e\x00\x00\x00\x12\x00\x01\x00"}, /* ^....... */ \
+ {0x00001070, "\x2c\x00\x00\x00\xf6\x02\x00\x00"}, /* ,....... */ \
+ {0x00001078, "\x26\x00\x00\x00\x12\x00\x01\x00"}, /* &....... */ \
+ {0x00001080, "\x1b\x00\x00\x00\x40\x05\x00\x00"}, /* ....@... */ \
+ {0x00001088, "\x00\x00\x00\x00\x10\x00\x03\x00"}, /* ........ */ \
+ {0x00001090, "\x5b\x00\x00\x00\x74\x03\x00\x00"}, /* [...t... */ \
+ {0x00001098, "\x02\x00\x00\x00\x12\x00\x01\x00"}, /* ........ */ \
+ {0x000010a0, "\x9f\x00\x00\x00\xa0\x00\x00\x00"}, /* ........ */ \
+ {0x000010a8, "\x00\x00\x00\x00\x10\x00\x03\x00"}, /* ........ */ \
+ {0x000010b0, "\x79\x00\x00\x00\xa0\x04\x00\x00"}, /* y....... */ \
+ {0x000010b8, "\x00\x00\x00\x00\x10\x00\x01\x00"}, /* ........ */ \
+ {0x000010c0, "\x33\x00\x00\x00\x1c\x03\x00\x00"}, /* 3....... */ \
+ {0x000010c8, "\x42\x00\x00\x00\x12\x00\x01\x00"}, /* B....... */ \
+ {0x000010d0, "\x01\x00\x00\x00\x1e\x02\x00\x00"}, /* ........ */ \
+ {0x000010d8, "\x7a\x00\x00\x00\x12\x00\x01\x00"}, /* z....... */ \
+ {0x000010e0, "\x91\x00\x00\x00\x40\x05\x00\x00"}, /* ....@... */ \
+ {0x000010e8, "\x00\x00\x00\x00\x10\x00\x03\x00"}, /* ........ */ \
+ {0x000010f0, "\x11\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000010f8, "\x00\x00\x00\x00\x10\x00\x01\x00"}, /* ........ */ \
+ {0x00001100, "\x80\x00\x00\x00\xa0\x04\x00\x00"}, /* ........ */ \
+ {0x00001108, "\x00\x00\x00\x00\x10\x00\xf1\xff"}, /* ........ */ \
+ {0x00001110, "\x0a\x00\x00\x00\x5e\x03\x00\x00"}, /* ....^... */ \
+ {0x00001118, "\x02\x00\x00\x00\x12\x00\x01\x00"}, /* ........ */ \
+ {0x00001120, "\x8b\x00\x00\x00\x20\x05\x00\x00"}, /* .... ... */ \
+ {0x00001128, "\x00\x00\x00\x00\x10\x00\x03\x00"}, /* ........ */ \
+ {0, NULL} } }
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * This file contains a precompiled EFI binary built from
+ * lib/efi_selftest/efi_miniapp_file_image_exit.c and converted to an include
+ * using tools/file2include. It is used to testing the EFI_TCG2_PROTOCOL.
+ * The precompiled form is needed to avoid the problem of reproducible builds.
+ */
+
+#define EFI_ST_DISK_IMG { 0x000011c8, { \
+ {0x00000000, "\x4d\x5a\x00\x00\x00\x00\x00\x00"}, /* MZ...... */ \
+ {0x00000030, "\x52\x49\x53\x43\x56\x00\x00\x00"}, /* RISCV... */ \
+ {0x00000038, "\x52\x53\x43\x05\x40\x00\x00\x00"}, /* RSC.@... */ \
+ {0x00000040, "\x50\x45\x00\x00\x64\x50\x02\x00"}, /* PE..dP.. */ \
+ {0x00000050, "\x00\x00\x00\x00\xf0\x00\x0e\x02"}, /* ........ */ \
+ {0x00000058, "\x0b\x02\x02\x14\x58\x04\x00\x00"}, /* ....X... */ \
+ {0x00000068, "\x98\x01\x00\x00\x98\x01\x00\x00"}, /* ........ */ \
+ {0x00000078, "\x20\x00\x00\x00\x08\x00\x00\x00"}, /* ....... */ \
+ {0x00000080, "\x00\x00\x00\x00\x01\x00\x00\x00"}, /* ........ */ \
+ {0x00000090, "\xf0\x05\x00\x00\x98\x01\x00\x00"}, /* ........ */ \
+ {0x00000098, "\x00\x00\x00\x00\x0a\x00\x00\x00"}, /* ........ */ \
+ {0x000000c0, "\x00\x00\x00\x00\x06\x00\x00\x00"}, /* ........ */ \
+ {0x00000148, "\x2e\x72\x65\x6c\x6f\x63\x00\x00"}, /* .reloc.. */ \
+ {0x00000168, "\x00\x00\x00\x00\x40\x00\x10\x42"}, /* ....@..B */ \
+ {0x00000170, "\x2e\x74\x65\x78\x74\x00\x00\x00"}, /* .text... */ \
+ {0x00000178, "\x58\x04\x00\x00\x98\x01\x00\x00"}, /* X....... */ \
+ {0x00000180, "\x58\x04\x00\x00\x98\x01\x00\x00"}, /* X....... */ \
+ {0x00000190, "\x00\x00\x00\x00\x20\x00\x50\xe0"}, /* .... .P. */ \
+ {0x00000198, "\x21\x11\x2a\xe0\x2e\xe4\x06\xe8"}, /* !....... */ \
+ {0x000001a0, "\x17\x05\x00\x00\x13\x05\x05\xe6"}, /* ........ */ \
+ {0x000001a8, "\x97\x05\x00\x00\x93\x85\x85\x31"}, /* .......1 */ \
+ {0x000001b0, "\xef\x00\x20\x0f\x63\x17\x05\x00"}, /* .. .c... */ \
+ {0x000001b8, "\xa2\x65\x02\x65\xef\x00\x80\x07"}, /* .e.e.... */ \
+ {0x000001c0, "\xc2\x60\x61\x01\x82\x80\x79\x71"}, /* .`a...yq */ \
+ {0x000001c8, "\x22\xf0\x06\xf4\x26\xec\xbc\x71"}, /* "...&..q */ \
+ {0x000001d0, "\xa4\x61\x01\x47\x03\xb8\x87\x11"}, /* .a.G.... */ \
+ {0x000001d8, "\x81\x46\x89\x47\x30\x00\x97\x05"}, /* .F.G0... */ \
+ {0x000001e0, "\x00\x00\x93\x85\x25\x3f\x02\x98"}, /* ....%?.. */ \
+ {0x000001e8, "\x2a\x84\x11\xcd\x9c\x64\x97\x05"}, /* .....d.. */ \
+ {0x000001f0, "\x00\x00\x93\x85\x25\x1a\x26\x85"}, /* ....%.&. */ \
+ {0x000001f8, "\x82\x97\x22\x85\xa2\x70\x02\x74"}, /* .."..p.t */ \
+ {0x00000200, "\xe2\x64\x45\x61\x82\x80\xa2\x66"}, /* .dEa...f */ \
+ {0x00000208, "\x17\x07\x00\x00\x13\x07\xe7\xfb"}, /* ........ */ \
+ {0x00000210, "\xbc\x62\x63\x66\xf7\x00\xb4\x66"}, /* .bcf...f */ \
+ {0x00000218, "\xb6\x97\xe3\x60\xf7\xfe\x9c\x64"}, /* ...`...d */ \
+ {0x00000220, "\x7d\x54\x97\x05\x00\x00\x93\x85"}, /* }T...... */ \
+ {0x00000228, "\xe5\x1b\x26\x85\x7e\x14\x82\x97"}, /* ..&.~... */ \
+ {0x00000230, "\x39\x04\xe1\xb7\x79\x71\x97\x07"}, /* 9...yq.. */ \
+ {0x00000238, "\x00\x00\x93\x87\x27\x27\x26\xec"}, /* ....''&. */ \
+ {0x00000240, "\x4a\xe8\x06\xf4\x22\xf0\x98\x63"}, /* J..."..c */ \
+ {0x00000248, "\x9c\x67\xa0\x61\x3a\xe0\x3e\xe4"}, /* .g.a:.>. */ \
+ {0x00000250, "\x1c\x64\x2a\x89\xae\x84\x22\x85"}, /* .d....". */ \
+ {0x00000258, "\x97\x05\x00\x00\x93\x85\x05\x1d"}, /* ........ */ \
+ {0x00000260, "\x82\x97\xa6\x85\x4a\x85\xef\xf0"}, /* ....J... */ \
+ {0x00000268, "\x1f\xf6\x05\xc9\x1c\x64\x97\x05"}, /* .....d.. */ \
+ {0x00000270, "\x00\x00\x93\x85\xa5\x1f\x22\x85"}, /* ......". */ \
+ {0x00000278, "\x82\x97\xfd\x55\xfe\x15\xb9\x05"}, /* ...U.... */ \
+ {0x00000280, "\xbc\x70\x8a\x86\x4a\x85\xfc\x6f"}, /* .p..J..o */ \
+ {0x00000288, "\x41\x46\x82\x97\xa2\x70\x02\x74"}, /* AF...p.t */ \
+ {0x00000290, "\xe2\x64\x42\x69\x01\x45\x45\x61"}, /* .dBi.EEa */ \
+ {0x00000298, "\x82\x80\xfd\x55\xfe\x15\x8d\x05"}, /* ...U.... */ \
+ {0x000002a0, "\xc5\xb7\xa1\x05\x81\x47\x01\x47"}, /* .....G.G */ \
+ {0x000002a8, "\x81\x46\x21\x48\xa5\x48\x1d\x43"}, /* .F!H.H.C */ \
+ {0x000002b0, "\x03\xb6\x85\xff\x09\xe6\x95\xe3"}, /* ........ */ \
+ {0x000002b8, "\x31\xe7\x01\x45\x82\x80\x63\x0a"}, /* 1..E..c. */ \
+ {0x000002c0, "\x06\x01\x63\x0a\x16\x01\x63\x14"}, /* ..c...c. */ \
+ {0x000002c8, "\x66\x00\x9c\x61\xaa\x97\xc1\x05"}, /* f..a.... */ \
+ {0x000002d0, "\xc5\xb7\x94\x61\xed\xbf\x98\x61"}, /* ...a...a */ \
+ {0x000002d8, "\xdd\xbf\x0d\xc7\x7d\x56\x01\x92"}, /* ....}V.. */ \
+ {0x000002e0, "\x8d\x48\xe3\x5c\xd0\xfc\x8c\x67"}, /* .H.\...g */ \
+ {0x000002e8, "\xf1\x8d\x63\x9c\x15\x01\x8c\x63"}, /* ..c....c */ \
+ {0x000002f0, "\x03\xb8\x07\x01\x99\x8e\xaa\x95"}, /* ........ */ \
+ {0x000002f8, "\x2a\x98\x23\xb0\x05\x01\xba\x97"}, /* ..#..... */ \
+ {0x00000300, "\xcd\xb7\x01\xa0\x7d\x55\x7e\x15"}, /* ....}U~. */ \
+ {0x00000308, "\x05\x05\x82\x80\x01\x47\x63\x14"}, /* .....Gc. */ \
+ {0x00000310, "\xe6\x00\x01\x45\x82\x80\xb3\x07"}, /* ...E.... */ \
+ {0x00000318, "\xe5\x00\x05\x07\xb3\x86\xe5\x00"}, /* ........ */ \
+ {0x00000320, "\x83\xc7\x07\x00\x83\xc6\xf6\xff"}, /* ........ */ \
+ {0x00000328, "\xe3\x83\xd7\xfe\x3b\x85\xd7\x40"}, /* ....;..@ */ \
+ {0x00000330, "\x82\x80\x63\xf5\xa5\x02\x93\x46"}, /* ..c....F */ \
+ {0x00000338, "\xf6\xff\x81\x47\xfd\x17\x63\x91"}, /* ...G..c. */ \
+ {0x00000340, "\xd7\x02\x82\x80\x33\x87\xf5\x00"}, /* ....3... */ \
+ {0x00000348, "\x83\x46\x07\x00\x33\x07\xf5\x00"}, /* .F..3... */ \
+ {0x00000350, "\x85\x07\x23\x00\xd7\x00\xe3\x17"}, /* ..#..... */ \
+ {0x00000358, "\xf6\xfe\x82\x80\x81\x47\xe5\xbf"}, /* .....G.. */ \
+ {0x00000360, "\x33\x07\xf6\x00\x33\x88\xe5\x00"}, /* 3...3... */ \
+ {0x00000368, "\x03\x48\x08\x00\x2a\x97\x23\x00"}, /* .H....#. */ \
+ {0x00000370, "\x07\x01\xe9\xb7\x6f\xf0\xff\xfb"}, /* ....o... */ \
+ {0x00000378, "\x2a\x96\xaa\x87\x63\x93\xc7\x00"}, /* ....c... */ \
+ {0x00000380, "\x82\x80\x85\x07\xa3\x8f\xb7\xfe"}, /* ........ */ \
+ {0x00000388, "\xd5\xbf\x82\x80\x82\x80\x00\x00"}, /* ........ */ \
+ {0x00000390, "\x43\x00\x6f\x00\x75\x00\x6c\x00"}, /* C.o.u.l. */ \
+ {0x00000398, "\x64\x00\x20\x00\x6e\x00\x6f\x00"}, /* d. .n.o. */ \
+ {0x000003a0, "\x74\x00\x20\x00\x6f\x00\x70\x00"}, /* t. .o.p. */ \
+ {0x000003a8, "\x65\x00\x6e\x00\x20\x00\x6c\x00"}, /* e.n. .l. */ \
+ {0x000003b0, "\x6f\x00\x61\x00\x64\x00\x65\x00"}, /* o.a.d.e. */ \
+ {0x000003b8, "\x64\x00\x20\x00\x69\x00\x6d\x00"}, /* d. .i.m. */ \
+ {0x000003c0, "\x61\x00\x67\x00\x65\x00\x20\x00"}, /* a.g.e. . */ \
+ {0x000003c8, "\x70\x00\x72\x00\x6f\x00\x74\x00"}, /* p.r.o.t. */ \
+ {0x000003d0, "\x6f\x00\x63\x00\x6f\x00\x6c\x00"}, /* o.c.o.l. */ \
+ {0x000003e0, "\x49\x00\x6e\x00\x63\x00\x6f\x00"}, /* I.n.c.o. */ \
+ {0x000003e8, "\x72\x00\x72\x00\x65\x00\x63\x00"}, /* r.r.e.c. */ \
+ {0x000003f0, "\x74\x00\x20\x00\x69\x00\x6d\x00"}, /* t. .i.m. */ \
+ {0x000003f8, "\x61\x00\x67\x00\x65\x00\x5f\x00"}, /* a.g.e._. */ \
+ {0x00000400, "\x62\x00\x61\x00\x73\x00\x65\x00"}, /* b.a.s.e. */ \
+ {0x00000408, "\x20\x00\x6f\x00\x72\x00\x20\x00"}, /* .o.r. . */ \
+ {0x00000410, "\x69\x00\x6d\x00\x61\x00\x67\x00"}, /* i.m.a.g. */ \
+ {0x00000418, "\x65\x00\x5f\x00\x73\x00\x69\x00"}, /* e._.s.i. */ \
+ {0x00000420, "\x7a\x00\x65\x00\x0a\x00\x00\x00"}, /* z.e..... */ \
+ {0x00000428, "\x45\x00\x46\x00\x49\x00\x20\x00"}, /* E.F.I. . */ \
+ {0x00000430, "\x61\x00\x70\x00\x70\x00\x6c\x00"}, /* a.p.p.l. */ \
+ {0x00000438, "\x69\x00\x63\x00\x61\x00\x74\x00"}, /* i.c.a.t. */ \
+ {0x00000440, "\x69\x00\x6f\x00\x6e\x00\x20\x00"}, /* i.o.n. . */ \
+ {0x00000448, "\x63\x00\x61\x00\x6c\x00\x6c\x00"}, /* c.a.l.l. */ \
+ {0x00000450, "\x69\x00\x6e\x00\x67\x00\x20\x00"}, /* i.n.g. . */ \
+ {0x00000458, "\x45\x00\x78\x00\x69\x00\x74\x00"}, /* E.x.i.t. */ \
+ {0x00000460, "\x0a\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000468, "\x4c\x00\x6f\x00\x61\x00\x64\x00"}, /* L.o.a.d. */ \
+ {0x00000470, "\x65\x00\x64\x00\x20\x00\x69\x00"}, /* e.d. .i. */ \
+ {0x00000478, "\x6d\x00\x61\x00\x67\x00\x65\x00"}, /* m.a.g.e. */ \
+ {0x00000480, "\x20\x00\x70\x00\x72\x00\x6f\x00"}, /* .p.r.o. */ \
+ {0x00000488, "\x74\x00\x6f\x00\x63\x00\x6f\x00"}, /* t.o.c.o. */ \
+ {0x00000490, "\x6c\x00\x20\x00\x6d\x00\x69\x00"}, /* l. .m.i. */ \
+ {0x00000498, "\x73\x00\x73\x00\x69\x00\x6e\x00"}, /* s.s.i.n. */ \
+ {0x000004a0, "\x67\x00\x0a\x00\x00\x00\x00\x00"}, /* g....... */ \
+ {0x000004a8, "\x53\x00\x55\x00\x43\x00\x43\x00"}, /* S.U.C.C. */ \
+ {0x000004b0, "\x45\x00\x53\x00\x53\x00\x00\x00"}, /* E.S.S... */ \
+ {0x000004c0, "\x10\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000004d0, "\x04\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000004d8, "\xb0\x20\x00\x00\x00\x00\x00\x00"}, /* . ...... */ \
+ {0x000004e0, "\xf5\xfe\xff\x6f\x00\x00\x00\x00"}, /* ...o.... */ \
+ {0x000004e8, "\x48\x21\x00\x00\x00\x00\x00\x00"}, /* H!...... */ \
+ {0x000004f0, "\x05\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000004f8, "\x00\x20\x00\x00\x00\x00\x00\x00"}, /* . ...... */ \
+ {0x00000500, "\x06\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000508, "\x00\x10\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000510, "\x0a\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000518, "\xaa\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000520, "\x0b\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000528, "\x18\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000530, "\x07\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000540, "\x08\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000550, "\x09\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000558, "\x18\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000560, "\x1e\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000568, "\x02\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000005d0, "\xa1\x31\x1b\x5b\x62\x95\xd2\x11"}, /* .1.[b... */ \
+ {0x000005d8, "\x8e\x3f\x00\xa0\xc9\x69\x72\x3b"}, /* .?...ir; */ \
+ {0x000005e0, "\xc0\x04\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00001018, "\x00\x00\x00\x00\x03\x00\x01\x00"}, /* ........ */ \
+ {0x00001030, "\x42\x00\x00\x00\x12\x00\x01\x00"}, /* B....... */ \
+ {0x00001038, "\x8a\x03\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00001040, "\x02\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00001048, "\x73\x00\x00\x00\x10\x00\x01\x00"}, /* s....... */ \
+ {0x00001060, "\x3b\x00\x00\x00\x12\x00\x01\x00"}, /* ;....... */ \
+ {0x00001068, "\x78\x03\x00\x00\x00\x00\x00\x00"}, /* x....... */ \
+ {0x00001070, "\x12\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00001078, "\x96\x00\x00\x00\x10\x00\x03\x00"}, /* ........ */ \
+ {0x00001080, "\xf0\x05\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00001090, "\x1b\x00\x00\x00\x12\x00\x01\x00"}, /* ........ */ \
+ {0x00001098, "\xa2\x02\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000010a0, "\x6a\x00\x00\x00\x00\x00\x00\x00"}, /* j....... */ \
+ {0x000010a8, "\x25\x00\x00\x00\x12\x00\x01\x00"}, /* %....... */ \
+ {0x000010b0, "\x0c\x03\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000010b8, "\x26\x00\x00\x00\x00\x00\x00\x00"}, /* &....... */ \
+ {0x000010c0, "\x14\x00\x00\x00\x10\x00\x03\x00"}, /* ........ */ \
+ {0x000010c8, "\xf0\x05\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000010d8, "\x5b\x00\x00\x00\x12\x00\x01\x00"}, /* [....... */ \
+ {0x000010e0, "\x8c\x03\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000010e8, "\x02\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000010f0, "\x9f\x00\x00\x00\x10\x00\x03\x00"}, /* ........ */ \
+ {0x000010f8, "\x30\x01\x00\x00\x00\x00\x00\x00"}, /* 0....... */ \
+ {0x00001108, "\x79\x00\x00\x00\x10\x00\x01\x00"}, /* y....... */ \
+ {0x00001110, "\xc0\x04\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00001120, "\x2c\x00\x00\x00\x12\x00\x01\x00"}, /* ,....... */ \
+ {0x00001128, "\x32\x03\x00\x00\x00\x00\x00\x00"}, /* 2....... */ \
+ {0x00001130, "\x42\x00\x00\x00\x00\x00\x00\x00"}, /* B....... */ \
+ {0x00001138, "\x01\x00\x00\x00\x12\x00\x01\x00"}, /* ........ */ \
+ {0x00001140, "\x34\x02\x00\x00\x00\x00\x00\x00"}, /* 4....... */ \
+ {0x00001148, "\x6e\x00\x00\x00\x00\x00\x00\x00"}, /* n....... */ \
+ {0x00001150, "\x91\x00\x00\x00\x10\x00\x03\x00"}, /* ........ */ \
+ {0x00001158, "\xf0\x05\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00001168, "\x0a\x00\x00\x00\x10\x00\x01\x00"}, /* ........ */ \
+ {0x00001180, "\x80\x00\x00\x00\x10\x00\xf1\xff"}, /* ........ */ \
+ {0x00001188, "\xc0\x04\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00001198, "\x34\x00\x00\x00\x12\x00\x01\x00"}, /* 4....... */ \
+ {0x000011a0, "\x74\x03\x00\x00\x00\x00\x00\x00"}, /* t....... */ \
+ {0x000011a8, "\x04\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000011b0, "\x8b\x00\x00\x00\x10\x00\x03\x00"}, /* ........ */ \
+ {0x000011b8, "\xd0\x05\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0, NULL} } }
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * This file contains a precompiled EFI binary built from
+ * lib/efi_selftest/efi_miniapp_file_image_exit.c and converted to an include
+ * using tools/file2include. It is used to testing the EFI_TCG2_PROTOCOL.
+ * The precompiled form is needed to avoid the problem of reproducible builds.
+ */
+
+#define EFI_ST_DISK_IMG { 0x00001000, { \
+ {0x00000000, "\x4d\x5a\x90\x00\x03\x00\x00\x00"}, /* MZ...... */ \
+ {0x00000008, "\x04\x00\x00\x00\xff\xff\x00\x00"}, /* ........ */ \
+ {0x00000010, "\xb8\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000018, "\x40\x00\x00\x00\x00\x00\x00\x00"}, /* @....... */ \
+ {0x00000038, "\x00\x00\x00\x00\x80\x00\x00\x00"}, /* ........ */ \
+ {0x00000040, "\x0e\x1f\xba\x0e\x00\xb4\x09\xcd"}, /* ........ */ \
+ {0x00000048, "\x21\xb8\x01\x4c\xcd\x21\x54\x68"}, /* !..L.!Th */ \
+ {0x00000050, "\x69\x73\x20\x70\x72\x6f\x67\x72"}, /* is progr */ \
+ {0x00000058, "\x61\x6d\x20\x63\x61\x6e\x6e\x6f"}, /* am canno */ \
+ {0x00000060, "\x74\x20\x62\x65\x20\x72\x75\x6e"}, /* t be run */ \
+ {0x00000068, "\x20\x69\x6e\x20\x44\x4f\x53\x20"}, /* in DOS */ \
+ {0x00000070, "\x6d\x6f\x64\x65\x2e\x0d\x0d\x0a"}, /* mode.... */ \
+ {0x00000078, "\x24\x00\x00\x00\x00\x00\x00\x00"}, /* $....... */ \
+ {0x00000080, "\x50\x45\x00\x00\x64\x86\x05\x00"}, /* PE..d... */ \
+ {0x00000090, "\x00\x00\x00\x00\xf0\x00\x0e\x02"}, /* ........ */ \
+ {0x00000098, "\x0b\x02\x02\x1e\x00\x04\x00\x00"}, /* ........ */ \
+ {0x000000a0, "\x00\x08\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000000a8, "\x00\x20\x00\x00\x00\x20\x00\x00"}, /* . ... .. */ \
+ {0x000000b8, "\x00\x10\x00\x00\x00\x02\x00\x00"}, /* ........ */ \
+ {0x000000d0, "\x00\x70\x00\x00\x00\x04\x00\x00"}, /* .p...... */ \
+ {0x000000d8, "\x24\xe3\x00\x00\x0a\x00\x00\x00"}, /* $....... */ \
+ {0x00000100, "\x00\x00\x00\x00\x10\x00\x00\x00"}, /* ........ */ \
+ {0x00000130, "\x00\x30\x00\x00\x0a\x00\x00\x00"}, /* .0...... */ \
+ {0x00000188, "\x2e\x74\x65\x78\x74\x00\x00\x00"}, /* .text... */ \
+ {0x00000190, "\x29\x02\x00\x00\x00\x20\x00\x00"}, /* ).... .. */ \
+ {0x00000198, "\x00\x04\x00\x00\x00\x04\x00\x00"}, /* ........ */ \
+ {0x000001a8, "\x00\x00\x00\x00\x20\x00\x30\x60"}, /* .... .0` */ \
+ {0x000001b0, "\x2e\x72\x65\x6c\x6f\x63\x00\x00"}, /* .reloc.. */ \
+ {0x000001b8, "\x0a\x00\x00\x00\x00\x30\x00\x00"}, /* .....0.. */ \
+ {0x000001c0, "\x00\x02\x00\x00\x00\x08\x00\x00"}, /* ........ */ \
+ {0x000001d0, "\x00\x00\x00\x00\x40\x00\x10\x42"}, /* ....@..B */ \
+ {0x000001d8, "\x2e\x64\x61\x74\x61\x00\x00\x00"}, /* .data... */ \
+ {0x000001e0, "\x38\x01\x00\x00\x00\x40\x00\x00"}, /* 8....@.. */ \
+ {0x000001e8, "\x00\x02\x00\x00\x00\x0a\x00\x00"}, /* ........ */ \
+ {0x000001f8, "\x00\x00\x00\x00\x40\x00\x50\xc0"}, /* ....@.P. */ \
+ {0x00000200, "\x2e\x64\x79\x6e\x61\x6d\x69\x63"}, /* .dynamic */ \
+ {0x00000208, "\xe0\x00\x00\x00\x00\x50\x00\x00"}, /* .....P.. */ \
+ {0x00000210, "\x00\x02\x00\x00\x00\x0c\x00\x00"}, /* ........ */ \
+ {0x00000220, "\x00\x00\x00\x00\x40\x00\x40\xc0"}, /* ....@.@. */ \
+ {0x00000228, "\x2e\x64\x79\x6e\x73\x79\x6d\x00"}, /* .dynsym. */ \
+ {0x00000230, "\x48\x00\x00\x00\x00\x60\x00\x00"}, /* H....`.. */ \
+ {0x00000238, "\x00\x02\x00\x00\x00\x0e\x00\x00"}, /* ........ */ \
+ {0x00000248, "\x00\x00\x00\x00\x40\x00\x40\x40"}, /* ....@.@@ */ \
+ {0x00000400, "\x48\x83\xec\x08\x51\x52\x48\x8d"}, /* H...QRH. */ \
+ {0x00000408, "\x0d\xf3\xdf\xff\xff\x48\x8d\x15"}, /* .....H.. */ \
+ {0x00000410, "\xec\x2f\x00\x00\xe8\x24\x01\x00"}, /* ./...$.. */ \
+ {0x00000418, "\x00\x5a\x59\x48\x85\xc0\x75\x05"}, /* .ZYH..u. */ \
+ {0x00000420, "\xe8\x8f\x00\x00\x00\x48\x83\xc4"}, /* .....H.. */ \
+ {0x00000428, "\x08\xc3\x56\x45\x31\xc9\x53\x48"}, /* ..VE1.SH */ \
+ {0x00000430, "\x83\xec\x48\x48\x8b\x42\x60\x48"}, /* ..HH.B`H */ \
+ {0x00000438, "\x8b\x5a\x40\x4c\x8d\x44\x24\x38"}, /* .Z@L.D$8 */ \
+ {0x00000440, "\xc7\x44\x24\x28\x02\x00\x00\x00"}, /* .D$(.... */ \
+ {0x00000448, "\x48\xc7\x44\x24\x20\x00\x00\x00"}, /* H.D$ ... */ \
+ {0x00000450, "\x00\x48\x8d\x15\xc8\x20\x00\x00"}, /* .H... .. */ \
+ {0x00000458, "\xff\x90\x18\x01\x00\x00\x48\x85"}, /* ......H. */ \
+ {0x00000460, "\xc0\x48\x89\xc6\x74\x0f\x48\x8d"}, /* .H..t.H. */ \
+ {0x00000468, "\x15\x95\x1f\x00\x00\x48\x89\xd9"}, /* .....H.. */ \
+ {0x00000470, "\xff\x53\x08\xeb\x35\x48\x8b\x4c"}, /* .S..5H.L */ \
+ {0x00000478, "\x24\x38\x48\x8d\x15\xa9\xff\xff"}, /* $8H..... */ \
+ {0x00000480, "\xff\x48\x8b\x41\x40\x48\x39\xd0"}, /* .H.A@H9. */ \
+ {0x00000488, "\x77\x09\x48\x03\x41\x48\x48\x39"}, /* w.H.AHH9 */ \
+ {0x00000490, "\xd0\x77\x17\x48\x8d\x15\xb2\x1f"}, /* .w.H.... */ \
+ {0x00000498, "\x00\x00\x48\x89\xd9\x48\xbe\x0e"}, /* ..H..H.. */ \
+ {0x000004a0, "\x00\x00\x00\x00\x00\x00\x80\xff"}, /* ........ */ \
+ {0x000004a8, "\x53\x08\x48\x83\xc4\x48\x48\x89"}, /* S.H..HH. */ \
+ {0x000004b0, "\xf0\x5b\x5e\xc3\x57\x48\x89\xcf"}, /* .[^.WH.. */ \
+ {0x000004b8, "\x56\x48\x89\xd6\x53\x48\x83\xec"}, /* VH..SH.. */ \
+ {0x000004c0, "\x30\x48\x8b\x5a\x40\x48\x8b\x05"}, /* 0H.Z@H.. */ \
+ {0x000004c8, "\x42\x20\x00\x00\x48\x8b\x15\x43"}, /* B ..H..C */ \
+ {0x000004d0, "\x20\x00\x00\x48\x89\xd9\x48\x89"}, /* ..H..H. */ \
+ {0x000004d8, "\x44\x24\x20\x48\x89\x54\x24\x28"}, /* D$ H.T$( */ \
+ {0x000004e0, "\x48\x8d\x15\xad\x1f\x00\x00\xff"}, /* H....... */ \
+ {0x000004e8, "\x53\x08\x48\x89\xf2\x48\x89\xf9"}, /* S.H..H.. */ \
+ {0x000004f0, "\xe8\x35\xff\xff\xff\x48\xba\x03"}, /* .5...H.. */ \
+ {0x000004f8, "\x00\x00\x00\x00\x00\x00\x80\x48"}, /* .......H */ \
+ {0x00000500, "\x85\xc0\x74\x17\x48\x8d\x15\xc5"}, /* ..t.H... */ \
+ {0x00000508, "\x1f\x00\x00\x48\x89\xd9\xff\x53"}, /* ...H...S */ \
+ {0x00000510, "\x08\x48\xba\x0e\x00\x00\x00\x00"}, /* .H...... */ \
+ {0x00000518, "\x00\x00\x80\x48\x8b\x46\x60\x4c"}, /* ...H.F`L */ \
+ {0x00000520, "\x8d\x4c\x24\x20\x48\x89\xf9\x41"}, /* .L$ H..A */ \
+ {0x00000528, "\xb8\x10\x00\x00\x00\xff\x90\xd8"}, /* ........ */ \
+ {0x00000530, "\x00\x00\x00\x48\x83\xc4\x30\x31"}, /* ...H..01 */ \
+ {0x00000538, "\xc0\x5b\x5e\x5f\xc3\x48\x83\xc2"}, /* .[^_.H.. */ \
+ {0x00000540, "\x08\x31\xc0\x45\x31\xc9\x45\x31"}, /* .1.E1.E1 */ \
+ {0x00000548, "\xc0\x4c\x8b\x52\xf8\x4d\x85\xd2"}, /* .L.R.M.. */ \
+ {0x00000550, "\x74\x28\x49\x83\xfa\x08\x74\x14"}, /* t(I...t. */ \
+ {0x00000558, "\x49\x83\xfa\x09\x74\x13\x49\x83"}, /* I...t.I. */ \
+ {0x00000560, "\xfa\x07\x75\x10\x48\x8b\x02\x48"}, /* ..u.H..H */ \
+ {0x00000568, "\x01\xc8\xeb\x08\x4c\x8b\x02\xeb"}, /* ....L... */ \
+ {0x00000570, "\x03\x4c\x8b\x0a\x48\x83\xc2\x10"}, /* .L..H... */ \
+ {0x00000578, "\xeb\xcf\x48\x85\xc0\x41\x0f\x94"}, /* ..H..A.. */ \
+ {0x00000580, "\xc2\x4d\x85\xc9\x0f\x94\xc2\x45"}, /* .M.....E */ \
+ {0x00000588, "\x84\xd2\x74\x07\x84\xd2\x74\x23"}, /* ..t...t# */ \
+ {0x00000590, "\x31\xc0\xc3\x84\xd2\x75\x1c\x4d"}, /* 1....u.M */ \
+ {0x00000598, "\x85\xc0\x7e\xf4\x83\x78\x08\x08"}, /* ..~..x.. */ \
+ {0x000005a0, "\x75\x09\x48\x8b\x10\x48\x01\xca"}, /* u.H..H.. */ \
+ {0x000005a8, "\x48\x01\x0a\x4c\x01\xc8\x4d\x29"}, /* H..L..M) */ \
+ {0x000005b0, "\xc8\xeb\xe4\x48\xb8\x01\x00\x00"}, /* ...H.... */ \
+ {0x000005b8, "\x00\x00\x00\x00\x80\xc3\x31\xc9"}, /* ......1. */ \
+ {0x000005c0, "\x48\x39\xca\x74\x16\x0f\xb6\x04"}, /* H9.t.... */ \
+ {0x000005c8, "\x0f\x48\xff\xc1\x44\x0f\xb6\x44"}, /* .H..D..D */ \
+ {0x000005d0, "\x0e\xff\x44\x38\xc0\x74\xe9\x44"}, /* ..D8.t.D */ \
+ {0x000005d8, "\x29\xc0\xc3\x31\xc0\xc3\x48\x39"}, /* )..1..H9 */ \
+ {0x000005e0, "\xf7\x48\x89\xf8\x77\x15\x31\xc9"}, /* .H..w.1. */ \
+ {0x000005e8, "\x48\x39\xca\x74\x0d\x40\x8a\x3c"}, /* H9.t.@.< */ \
+ {0x000005f0, "\x0e\x40\x88\x3c\x08\x48\xff\xc1"}, /* .@.<.H.. */ \
+ {0x000005f8, "\xeb\xee\xc3\x48\x85\xd2\x74\x0d"}, /* ...H..t. */ \
+ {0x00000600, "\x8a\x4c\x16\xff\x88\x4c\x10\xff"}, /* .L...L.. */ \
+ {0x00000608, "\x48\xff\xca\xeb\xee\xc3\xe9\xcb"}, /* H....... */ \
+ {0x00000610, "\xff\xff\xff\x48\x89\xf8\x31\xc9"}, /* ...H..1. */ \
+ {0x00000618, "\x48\x39\xca\x74\x09\x40\x88\x34"}, /* H9.t.@.4 */ \
+ {0x00000620, "\x08\x48\xff\xc1\xeb\xf2\xc3\xc3"}, /* .H...... */ \
+ {0x00000628, "\xc3\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000800, "\x30\x11\x00\x00\x0a\x00\x00\x00"}, /* 0....... */ \
+ {0x00000a00, "\x00\x00\x43\x00\x6f\x00\x75\x00"}, /* ..C.o.u. */ \
+ {0x00000a08, "\x6c\x00\x64\x00\x20\x00\x6e\x00"}, /* l.d. .n. */ \
+ {0x00000a10, "\x6f\x00\x74\x00\x20\x00\x6f\x00"}, /* o.t. .o. */ \
+ {0x00000a18, "\x70\x00\x65\x00\x6e\x00\x20\x00"}, /* p.e.n. . */ \
+ {0x00000a20, "\x6c\x00\x6f\x00\x61\x00\x64\x00"}, /* l.o.a.d. */ \
+ {0x00000a28, "\x65\x00\x64\x00\x20\x00\x69\x00"}, /* e.d. .i. */ \
+ {0x00000a30, "\x6d\x00\x61\x00\x67\x00\x65\x00"}, /* m.a.g.e. */ \
+ {0x00000a38, "\x20\x00\x70\x00\x72\x00\x6f\x00"}, /* .p.r.o. */ \
+ {0x00000a40, "\x74\x00\x6f\x00\x63\x00\x6f\x00"}, /* t.o.c.o. */ \
+ {0x00000a48, "\x6c\x00\x00\x00\x49\x00\x6e\x00"}, /* l...I.n. */ \
+ {0x00000a50, "\x63\x00\x6f\x00\x72\x00\x72\x00"}, /* c.o.r.r. */ \
+ {0x00000a58, "\x65\x00\x63\x00\x74\x00\x20\x00"}, /* e.c.t. . */ \
+ {0x00000a60, "\x69\x00\x6d\x00\x61\x00\x67\x00"}, /* i.m.a.g. */ \
+ {0x00000a68, "\x65\x00\x5f\x00\x62\x00\x61\x00"}, /* e._.b.a. */ \
+ {0x00000a70, "\x73\x00\x65\x00\x20\x00\x6f\x00"}, /* s.e. .o. */ \
+ {0x00000a78, "\x72\x00\x20\x00\x69\x00\x6d\x00"}, /* r. .i.m. */ \
+ {0x00000a80, "\x61\x00\x67\x00\x65\x00\x5f\x00"}, /* a.g.e._. */ \
+ {0x00000a88, "\x73\x00\x69\x00\x7a\x00\x65\x00"}, /* s.i.z.e. */ \
+ {0x00000a90, "\x0a\x00\x00\x00\x45\x00\x46\x00"}, /* ....E.F. */ \
+ {0x00000a98, "\x49\x00\x20\x00\x61\x00\x70\x00"}, /* I. .a.p. */ \
+ {0x00000aa0, "\x70\x00\x6c\x00\x69\x00\x63\x00"}, /* p.l.i.c. */ \
+ {0x00000aa8, "\x61\x00\x74\x00\x69\x00\x6f\x00"}, /* a.t.i.o. */ \
+ {0x00000ab0, "\x6e\x00\x20\x00\x63\x00\x61\x00"}, /* n. .c.a. */ \
+ {0x00000ab8, "\x6c\x00\x6c\x00\x69\x00\x6e\x00"}, /* l.l.i.n. */ \
+ {0x00000ac0, "\x67\x00\x20\x00\x45\x00\x78\x00"}, /* g. .E.x. */ \
+ {0x00000ac8, "\x69\x00\x74\x00\x0a\x00\x00\x00"}, /* i.t..... */ \
+ {0x00000ad0, "\x4c\x00\x6f\x00\x61\x00\x64\x00"}, /* L.o.a.d. */ \
+ {0x00000ad8, "\x65\x00\x64\x00\x20\x00\x69\x00"}, /* e.d. .i. */ \
+ {0x00000ae0, "\x6d\x00\x61\x00\x67\x00\x65\x00"}, /* m.a.g.e. */ \
+ {0x00000ae8, "\x20\x00\x70\x00\x72\x00\x6f\x00"}, /* .p.r.o. */ \
+ {0x00000af0, "\x74\x00\x6f\x00\x63\x00\x6f\x00"}, /* t.o.c.o. */ \
+ {0x00000af8, "\x6c\x00\x20\x00\x6d\x00\x69\x00"}, /* l. .m.i. */ \
+ {0x00000b00, "\x73\x00\x73\x00\x69\x00\x6e\x00"}, /* s.s.i.n. */ \
+ {0x00000b08, "\x67\x00\x0a\x00\x00\x00\x53\x00"}, /* g.....S. */ \
+ {0x00000b10, "\x55\x00\x43\x00\x43\x00\x45\x00"}, /* U.C.C.E. */ \
+ {0x00000b18, "\x53\x00\x53\x00\x00\x00\x00\x00"}, /* S.S..... */ \
+ {0x00000b20, "\xa1\x31\x1b\x5b\x62\x95\xd2\x11"}, /* .1.[b... */ \
+ {0x00000b28, "\x8e\x3f\x00\xa0\xc9\x69\x72\x3b"}, /* .?...ir; */ \
+ {0x00000c00, "\x10\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000c10, "\x04\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000c20, "\xf5\xfe\xff\x6f\x00\x00\x00\x00"}, /* ...o.... */ \
+ {0x00000c28, "\x00\x80\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000c30, "\x05\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000c38, "\x00\x70\x00\x00\x00\x00\x00\x00"}, /* .p...... */ \
+ {0x00000c40, "\x06\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000c48, "\x00\x60\x00\x00\x00\x00\x00\x00"}, /* .`...... */ \
+ {0x00000c50, "\x0a\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000c58, "\x13\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000c60, "\x0b\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000c68, "\x18\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000c70, "\x1e\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000c78, "\x02\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000e18, "\x01\x00\x00\x00\x10\x00\x03\x00"}, /* ........ */ \
+ {0x00000e20, "\x00\x20\x00\x00\x00\x00\x00\x00"}, /* . ...... */ \
+ {0x00000e30, "\x08\x00\x00\x00\x10\x00\x01\x00"}, /* ........ */ \
+ {0, NULL} } }
return EFI_ST_FAILURE;
}
+ /* Check media connected */
+ ret = net->get_status(net, NULL, NULL);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to get status");
+ return EFI_ST_FAILURE;
+ }
+ if (net->mode && net->mode->media_present_supported &&
+ !net->mode->media_present) {
+ efi_st_error("Network media is not connected");
+ return EFI_ST_FAILURE;
+ }
+
/*
* Send DHCP discover message
*/
events[0] = timer;
events[1] = net->wait_for_packet;
for (;;) {
- u32 int_status;
-
/*
* Wait for packet to be received or timer event.
*/
continue;
}
/*
- * Receive packet
+ * Receive packets until buffer is empty
*/
- buffer_size = sizeof(buffer);
- ret = net->get_status(net, &int_status, NULL);
- if (ret != EFI_SUCCESS) {
- efi_st_error("Failed to get status");
- return EFI_ST_FAILURE;
- }
- if (!(int_status & EFI_SIMPLE_NETWORK_RECEIVE_INTERRUPT)) {
- efi_st_error("RX interrupt not set");
- return EFI_ST_FAILURE;
- }
- ret = net->receive(net, NULL, &buffer_size, &buffer,
- &srcaddr, &destaddr, NULL);
- if (ret != EFI_SUCCESS) {
- efi_st_error("Failed to receive packet");
- return EFI_ST_FAILURE;
+ for (;;) {
+ buffer_size = sizeof(buffer);
+ ret = net->receive(net, NULL, &buffer_size, &buffer,
+ &srcaddr, &destaddr, NULL);
+ if (ret == EFI_NOT_READY) {
+ /* The received buffer is empty. */
+ break;
+ }
+
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to receive packet");
+ return EFI_ST_FAILURE;
+ }
+ /*
+ * Check the packet is meant for this system.
+ * Unfortunately QEMU ignores the broadcast flag.
+ * So we have to check for broadcasts too.
+ */
+ if (memcmp(&destaddr, &net->mode->current_address, ARP_HLEN) &&
+ memcmp(&destaddr, BROADCAST_MAC, ARP_HLEN))
+ continue;
+ /*
+ * Check this is a DHCP reply
+ */
+ if (buffer.p.eth_hdr.et_protlen != ntohs(PROT_IP) ||
+ buffer.p.ip_udp.ip_hl_v != 0x45 ||
+ buffer.p.ip_udp.ip_p != IPPROTO_UDP ||
+ buffer.p.ip_udp.udp_src != ntohs(67) ||
+ buffer.p.ip_udp.udp_dst != ntohs(68) ||
+ buffer.p.dhcp_hdr.op != BOOTREPLY)
+ continue;
+ /*
+ * We successfully received a DHCP reply.
+ */
+ goto received;
}
- /*
- * Check the packet is meant for this system.
- * Unfortunately QEMU ignores the broadcast flag.
- * So we have to check for broadcasts too.
- */
- if (memcmp(&destaddr, &net->mode->current_address, ARP_HLEN) &&
- memcmp(&destaddr, BROADCAST_MAC, ARP_HLEN))
- continue;
- /*
- * Check this is a DHCP reply
- */
- if (buffer.p.eth_hdr.et_protlen != ntohs(PROT_IP) ||
- buffer.p.ip_udp.ip_hl_v != 0x45 ||
- buffer.p.ip_udp.ip_p != IPPROTO_UDP ||
- buffer.p.ip_udp.udp_src != ntohs(67) ||
- buffer.p.ip_udp.udp_dst != ntohs(68) ||
- buffer.p.dhcp_hdr.op != BOOTREPLY)
- continue;
- /*
- * We successfully received a DHCP reply.
- */
- break;
}
-
+received:
/*
* Write a log message.
*/
#include <efi_selftest.h>
#include <efi_tcg2.h>
+/*
+ * Include containing the miniapp.efi application.
+ * Note that tcg2 selftest measures the PE/COFF image,
+ * so we must have the pre-build efi application for
+ * each architecture.
+ */
+#if defined(__arm__)
+#include "efi_miniapp_tcg2_arm.h"
+#elif defined(__aarch64__)
+#include "efi_miniapp_tcg2_arm64.h"
+#elif defined(__i386__)
+#include "efi_miniapp_tcg2_ia32.h"
+#elif defined(__x86_64__)
+#include "efi_miniapp_tcg2_x86_64.h"
+#elif defined(__riscv) && (__riscv_xlen == 32)
+#include "efi_miniapp_tcg2_riscv32.h"
+#elif defined(__riscv) && (__riscv_xlen == 64)
+#include "efi_miniapp_tcg2_riscv64.h"
+#endif
+
+#include <linux/unaligned/be_byteshift.h>
+#include <linux/unaligned/le_byteshift.h>
+#include <mapmem.h>
+#include <smbios.h>
+#include <tables_csum.h>
static struct efi_boot_services *boottime;
static const efi_guid_t guid_tcg2 = EFI_TCG2_PROTOCOL_GUID;
+/* Block size of compressed disk image */
+#define COMPRESSED_DISK_IMAGE_BLOCK_SIZE 8
+
+static efi_handle_t image_handle;
+/* Decompressed file image */
+static u8 *image;
+
+/* One 8 byte block of the compressed disk image */
+struct line {
+ size_t addr;
+ char *line;
+};
+
+/* Compressed file image */
+struct compressed_file_image {
+ size_t length;
+ struct line lines[];
+};
+
+static struct compressed_file_image img = EFI_ST_DISK_IMG;
+
+static struct efi_tcg2_event *efi_tcg2_event;
+
+static struct efi_runtime_services *runtime;
+#define BOOT_NAME_1000 u"Boot1000"
+#define BOOT_NAME_1001 u"Boot1001"
+#define BOOT_NAME_1002 u"Boot1002"
+
+#define DEFAULT_ATTR (EFI_VARIABLE_NON_VOLATILE | \
+ EFI_VARIABLE_BOOTSERVICE_ACCESS | \
+ EFI_VARIABLE_RUNTIME_ACCESS)
+
+/* "efidebug boot add -b 1000 test1000 virtio 0:1 /EFI/debian/grubaa64.efi" */
+static const u8 boot_1000[] = {
+0x01, 0x00, 0x00, 0x00, 0x8d, 0x00, 0x74, 0x00, 0x65, 0x00, 0x73, 0x00,
+0x74, 0x00, 0x30, 0x00, 0x00, 0x00, 0x01, 0x04, 0x14, 0x00, 0xb9, 0x73,
+0x1d, 0xe6, 0x84, 0xa3, 0xcc, 0x4a, 0xae, 0xab, 0x82, 0xe8, 0x28, 0xf3,
+0x62, 0x8b, 0x01, 0x04, 0x15, 0x00, 0x92, 0x37, 0x29, 0x63, 0xf5, 0xad,
+0x25, 0x93, 0xb9, 0x9f, 0x4e, 0x0e, 0x45, 0x5c, 0x1b, 0x1e, 0x00, 0x04,
+0x01, 0x2a, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x57,
+0x5a, 0x47, 0xc2, 0x35, 0x27, 0x44, 0x47, 0x9f, 0x01, 0x67, 0xfe, 0xfa,
+0x1d, 0x06, 0xae, 0x02, 0x02, 0x04, 0x04, 0x36, 0x00, 0x5c, 0x00, 0x45,
+0x00, 0x46, 0x00, 0x49, 0x00, 0x5c, 0x00, 0x64, 0x00, 0x65, 0x00, 0x62,
+0x00, 0x69, 0x00, 0x61, 0x00, 0x6e, 0x00, 0x5c, 0x00, 0x67, 0x00, 0x72,
+0x00, 0x75, 0x00, 0x62, 0x00, 0x61, 0x00, 0x61, 0x00, 0x36, 0x00, 0x34,
+0x00, 0x2e, 0x00, 0x65, 0x00, 0x66, 0x00, 0x69, 0x00, 0x00, 0x00, 0x7f,
+0xff, 0x04, 0x00 };
+
+/* "efidebug boot add -b 1001 test1001 virtio 0:1 /EFI/debian/grubaa64.efi" */
+static const u8 boot_1001[] = {
+0x01, 0x00, 0x00, 0x00, 0x8d, 0x00, 0x74, 0x00, 0x65, 0x00, 0x73, 0x00,
+0x74, 0x00, 0x31, 0x00, 0x00, 0x00, 0x01, 0x04, 0x14, 0x00, 0xb9, 0x73,
+0x1d, 0xe6, 0x84, 0xa3, 0xcc, 0x4a, 0xae, 0xab, 0x82, 0xe8, 0x28, 0xf3,
+0x62, 0x8b, 0x01, 0x04, 0x15, 0x00, 0x92, 0x37, 0x29, 0x63, 0xf5, 0xad,
+0x25, 0x93, 0xb9, 0x9f, 0x4e, 0x0e, 0x45, 0x5c, 0x1b, 0x1e, 0x00, 0x04,
+0x01, 0x2a, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x57,
+0x5a, 0x47, 0xc2, 0x35, 0x27, 0x44, 0x47, 0x9f, 0x01, 0x67, 0xfe, 0xfa,
+0x1d, 0x06, 0xae, 0x02, 0x02, 0x04, 0x04, 0x36, 0x00, 0x5c, 0x00, 0x45,
+0x00, 0x46, 0x00, 0x49, 0x00, 0x5c, 0x00, 0x64, 0x00, 0x65, 0x00, 0x62,
+0x00, 0x69, 0x00, 0x61, 0x00, 0x6e, 0x00, 0x5c, 0x00, 0x67, 0x00, 0x72,
+0x00, 0x75, 0x00, 0x62, 0x00, 0x61, 0x00, 0x61, 0x00, 0x36, 0x00, 0x34,
+0x00, 0x2e, 0x00, 0x65, 0x00, 0x66, 0x00, 0x69, 0x00, 0x00, 0x00, 0x7f,
+0xff, 0x04, 0x00 };
+
+/* "efidebug boot add -b 1002 test1002 virtio 0:1 /EFI/debian/grubaa64.efi" */
+static const u8 boot_1002[] = {
+0x01, 0x00, 0x00, 0x00, 0x8d, 0x00, 0x74, 0x00, 0x65, 0x00, 0x73, 0x00,
+0x74, 0x00, 0x32, 0x00, 0x00, 0x00, 0x01, 0x04, 0x14, 0x00, 0xb9, 0x73,
+0x1d, 0xe6, 0x84, 0xa3, 0xcc, 0x4a, 0xae, 0xab, 0x82, 0xe8, 0x28, 0xf3,
+0x62, 0x8b, 0x01, 0x04, 0x15, 0x00, 0x92, 0x37, 0x29, 0x63, 0xf5, 0xad,
+0x25, 0x93, 0xb9, 0x9f, 0x4e, 0x0e, 0x45, 0x5c, 0x1b, 0x1e, 0x00, 0x04,
+0x01, 0x2a, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x57,
+0x5a, 0x47, 0xc2, 0x35, 0x27, 0x44, 0x47, 0x9f, 0x01, 0x67, 0xfe, 0xfa,
+0x1d, 0x06, 0xae, 0x02, 0x02, 0x04, 0x04, 0x36, 0x00, 0x5c, 0x00, 0x45,
+0x00, 0x46, 0x00, 0x49, 0x00, 0x5c, 0x00, 0x64, 0x00, 0x65, 0x00, 0x62,
+0x00, 0x69, 0x00, 0x61, 0x00, 0x6e, 0x00, 0x5c, 0x00, 0x67, 0x00, 0x72,
+0x00, 0x75, 0x00, 0x62, 0x00, 0x61, 0x00, 0x61, 0x00, 0x36, 0x00, 0x34,
+0x00, 0x2e, 0x00, 0x65, 0x00, 0x66, 0x00, 0x69, 0x00, 0x00, 0x00, 0x7f,
+0xff, 0x04, 0x00};
+
+/* "efidebug boot order 1002 1000 1001" */
+static u8 boot_order[] = {0x02, 0x10, 0x00, 0x10, 0x01, 0x10};
+
+static void *orig_smbios_table;
+static u64 dmi_addr = U32_MAX;
+#define SMBIOS_ENTRY_HEADER_SIZE 0x20
+/* smbios table for the measurement test */
+static u8 smbios_table_test[] = {
+0x5f, 0x53, 0x4d, 0x5f, 0x2c, 0x1f, 0x03, 0x00, 0x54, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x5f, 0x44, 0x4d, 0x49, 0x5f, 0xe4, 0x5c, 0x01,
+0x20, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00,
+0x01, 0x02, 0x00, 0x00, 0x03, 0x00, 0x80, 0x08, 0x01, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x0c, 0x15, 0x0a, 0xff, 0xff, 0x55, 0x2d, 0x42, 0x6f,
+0x6f, 0x74, 0x00, 0x32, 0x30, 0x32, 0x31, 0x2e, 0x31, 0x30, 0x2d, 0x72,
+0x63, 0x34, 0x2d, 0x30, 0x30, 0x30, 0x30, 0x35, 0x2d, 0x67, 0x37, 0x32,
+0x37, 0x63, 0x33, 0x66, 0x33, 0x32, 0x35, 0x39, 0x2d, 0x64, 0x69, 0x72,
+0x74, 0x79, 0x00, 0x31, 0x30, 0x2f, 0x30, 0x31, 0x2f, 0x32, 0x30, 0x32,
+0x31, 0x00, 0x00, 0x01, 0x1b, 0x01, 0x00, 0x01, 0x02, 0x00, 0x03, 0x31,
+0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x55, 0x6e, 0x6b, 0x6e, 0x6f, 0x77,
+0x6e, 0x00, 0x55, 0x6e, 0x6b, 0x6e, 0x6f, 0x77, 0x6e, 0x20, 0x50, 0x72,
+0x6f, 0x64, 0x75, 0x63, 0x74, 0x00, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36,
+0x37, 0x38, 0x00, 0x00, 0x02, 0x0e, 0x02, 0x00, 0x01, 0x02, 0x00, 0x04,
+0x03, 0x01, 0x01, 0x01, 0x00, 0x0a, 0x55, 0x6e, 0x6b, 0x6e, 0x6f, 0x77,
+0x6e, 0x00, 0x55, 0x6e, 0x6b, 0x6e, 0x6f, 0x77, 0x6e, 0x20, 0x50, 0x72,
+0x6f, 0x64, 0x75, 0x63, 0x74, 0x00, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33,
+0x33, 0x33, 0x00, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x00,
+0x00, 0x03, 0x15, 0x03, 0x00, 0x01, 0x03, 0x00, 0x02, 0x03, 0x03, 0x03,
+0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x6e,
+0x6b, 0x6e, 0x6f, 0x77, 0x6e, 0x00, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36,
+0x37, 0x38, 0x00, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x00,
+0x00, 0x04, 0x30, 0x04, 0x00, 0x00, 0x03, 0x02, 0x01, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x01, 0x06, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x02, 0x03, 0x04,
+0x04, 0x04, 0x08, 0x00, 0x00, 0x02, 0x00, 0x08, 0x00, 0x08, 0x00, 0x01,
+0x00, 0x55, 0x6e, 0x6b, 0x6e, 0x6f, 0x77, 0x6e, 0x00, 0x31, 0x32, 0x33,
+0x34, 0x35, 0x36, 0x37, 0x38, 0x00, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33,
+0x33, 0x33, 0x00, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x00,
+0x00, 0x20, 0x0b, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x7f, 0x04, 0x06, 0x00, 0x00, 0x00
+};
+
+#define IDX_ARRAY_SZ 3 /* support 24 PCRs */
+#define TPM2_CMD_BUF_SIZE 64
+/* TPM command is big endian */
+#define __MSB(x) ((x) >> 8)
+#define __LSB(x) ((x) & 0xFF)
+#define tpm_u16(x) __MSB(x), __LSB(x)
+#define tpm_u32(x) tpm_u16((x) >> 16), tpm_u16((x) & 0xFFFF)
+#define TPM2_PCR_READ_HEADER_SIZE 30
+
+static u8 (*pcrs)[TPM2_SHA256_DIGEST_SIZE];
+static u8 expected_pcrs[EFI_TCG2_MAX_PCR_INDEX + 1][TPM2_SHA256_DIGEST_SIZE] = {
+ {0x91, 0x21, 0x37, 0xc7, 0x1a, 0x49, 0x19, 0xc8,
+ 0xf1, 0xfb, 0xa9, 0x84, 0x5c, 0x65, 0xa9, 0xdd,
+ 0x7b, 0xb9, 0xfe, 0xa1, 0xcd, 0x64, 0x49, 0xdd,
+ 0xed, 0xe2, 0x65, 0x82, 0xc5, 0x3e, 0xf4, 0xc4},
+
+ {0xf5, 0x79, 0xf3, 0x20, 0x62, 0x6e, 0x8b, 0x58,
+ 0x62, 0xa3, 0x4e, 0x2f, 0xb7, 0x10, 0xac, 0x34,
+ 0x4e, 0x68, 0x94, 0x37, 0x87, 0x29, 0xc4, 0xbe,
+ 0xa3, 0xc4, 0xd9, 0x14, 0x2b, 0x66, 0x79, 0x9b},
+
+ {0x3d, 0x45, 0x8c, 0xfe, 0x55, 0xcc, 0x03, 0xea,
+ 0x1f, 0x44, 0x3f, 0x15, 0x62, 0xbe, 0xec, 0x8d,
+ 0xf5, 0x1c, 0x75, 0xe1, 0x4a, 0x9f, 0xcf, 0x9a,
+ 0x72, 0x34, 0xa1, 0x3f, 0x19, 0x8e, 0x79, 0x69},
+
+ {0x3d, 0x45, 0x8c, 0xfe, 0x55, 0xcc, 0x03, 0xea,
+ 0x1f, 0x44, 0x3f, 0x15, 0x62, 0xbe, 0xec, 0x8d,
+ 0xf5, 0x1c, 0x75, 0xe1, 0x4a, 0x9f, 0xcf, 0x9a,
+ 0x72, 0x34, 0xa1, 0x3f, 0x19, 0x8e, 0x79, 0x69},
+
+ /* PCR[4] is different per architecture */
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+
+ {0x3d, 0x45, 0x8c, 0xfe, 0x55, 0xcc, 0x03, 0xea,
+ 0x1f, 0x44, 0x3f, 0x15, 0x62, 0xbe, 0xec, 0x8d,
+ 0xf5, 0x1c, 0x75, 0xe1, 0x4a, 0x9f, 0xcf, 0x9a,
+ 0x72, 0x34, 0xa1, 0x3f, 0x19, 0x8e, 0x79, 0x69},
+
+ /* PCR[6] is different per architecture */
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+
+ {0x96, 0x74, 0xae, 0xcd, 0x3f, 0x40, 0xb4, 0xa9,
+ 0x36, 0xae, 0x19, 0xc8, 0x84, 0x8a, 0xb9, 0x5a,
+ 0x87, 0x99, 0xd8, 0x89, 0x7f, 0xfc, 0x40, 0x48,
+ 0x05, 0x99, 0x65, 0x2e, 0x55, 0xd4, 0x93, 0x32},
+
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+
+ {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+
+ {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+
+ {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+
+ {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+
+ {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+
+ {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+};
+
+/*
+ * PCR[4] and PCR[6] have the PE/COFF image measurement,
+ * this PCRs have different value in each architecture.
+ */
+#if defined(__arm__)
+static u8 expected_pcrs_per_arch[][TPM2_SHA256_DIGEST_SIZE] = {
+ /* PCR[4] */
+ {0xcd, 0xa2, 0x06, 0xad, 0x83, 0x9b, 0x8f, 0x92,
+ 0x01, 0xf9, 0xc8, 0x3d, 0xc9, 0x54, 0x66, 0xb3,
+ 0x97, 0x35, 0x88, 0xe1, 0xea, 0xd3, 0x1a, 0xd6,
+ 0x56, 0xee, 0x43, 0x1c, 0xdb, 0x4b, 0xf9, 0x1f},
+ /* PCR[6] */
+ {0x9c, 0xb8, 0x9d, 0x4a, 0xf6, 0x63, 0x95, 0xb0,
+ 0x95, 0xfe, 0x44, 0x30, 0x0f, 0x3a, 0x0b, 0x7c,
+ 0xef, 0xc7, 0xb6, 0x6a, 0x59, 0xae, 0xcb, 0xf6,
+ 0xbd, 0x2d, 0xb5, 0xb9, 0xb4, 0x95, 0x7d, 0xaf}
+};
+#elif defined(__aarch64__)
+static u8 expected_pcrs_per_arch[][TPM2_SHA256_DIGEST_SIZE] = {
+ /* PCR[4] */
+ {0x69, 0xdb, 0x01, 0x5e, 0x07, 0xed, 0x9c, 0xbb,
+ 0x27, 0x65, 0xb1, 0xf0, 0x7b, 0x04, 0xbc, 0x31,
+ 0xd1, 0xec, 0x00, 0xe4, 0xe1, 0x49, 0xdb, 0x1e,
+ 0x8b, 0x2d, 0xa2, 0x26, 0xb5, 0x8d, 0x07, 0xe2},
+ /* PCR[6] */
+ {0x53, 0x1b, 0x27, 0xb2, 0x6f, 0x2d, 0xab, 0x9b,
+ 0x6f, 0xbc, 0xd1, 0x8f, 0xc9, 0x14, 0x48, 0xe7,
+ 0x6d, 0x1b, 0xfb, 0x1b, 0x53, 0xc5, 0x8e, 0xf4,
+ 0x41, 0x50, 0x79, 0x24, 0x66, 0x57, 0x7b, 0xf8}
+};
+#elif defined(__i386__)
+static u8 expected_pcrs_per_arch[][TPM2_SHA256_DIGEST_SIZE] = {
+ /* PCR[4] */
+ {0xec, 0x5e, 0xdb, 0x68, 0x13, 0x48, 0x36, 0x0a,
+ 0x3a, 0xbc, 0x7b, 0x7b, 0xbc, 0x74, 0x7a, 0xa5,
+ 0x55, 0xea, 0xb9, 0x09, 0x6a, 0x6e, 0xc3, 0x21,
+ 0x51, 0x46, 0x22, 0xd2, 0x9d, 0xc9, 0xd5, 0x6a},
+ /* PCR[6] */
+ {0x26, 0x14, 0xe7, 0xde, 0x91, 0xd1, 0xf3, 0xde,
+ 0x7a, 0xc2, 0x78, 0xaf, 0x4b, 0x2e, 0x05, 0x9d,
+ 0x35, 0x17, 0xee, 0xcc, 0x0e, 0x77, 0x8d, 0x3f,
+ 0x7e, 0x20, 0x75, 0xfa, 0xbc, 0xbc, 0x24, 0x3e}
+};
+#elif defined(__x86_64__)
+static u8 expected_pcrs_per_arch[][TPM2_SHA256_DIGEST_SIZE] = {
+ /* PCR[4] */
+ {0x9a, 0x75, 0x99, 0x8b, 0x74, 0x45, 0xb6, 0x26,
+ 0x50, 0xe0, 0xbb, 0xfa, 0x2a, 0xa6, 0x19, 0xec,
+ 0x97, 0x12, 0x0c, 0xb5, 0xc8, 0x2a, 0xfe, 0xe5,
+ 0x29, 0xc8, 0xd3, 0x98, 0xe9, 0xd1, 0x9d, 0xd5},
+ /* PCR[6] */
+ {0xa2, 0xa2, 0xd3, 0xa7, 0x84, 0xc2, 0x95, 0x2a,
+ 0xab, 0x6f, 0xe7, 0xe8, 0x86, 0x9f, 0x99, 0xc6,
+ 0x6a, 0x8c, 0xcc, 0x5c, 0xb8, 0x83, 0xfa, 0x86,
+ 0x56, 0x5e, 0x91, 0x17, 0x0b, 0x5f, 0x54, 0xa8}
+};
+#elif defined(__riscv) && (__riscv_xlen == 32)
+static u8 expected_pcrs_per_arch[][TPM2_SHA256_DIGEST_SIZE] = {
+ /* PCR[4] */
+ {0x64, 0xe9, 0x25, 0xb3, 0xd8, 0x33, 0xb3, 0x1b,
+ 0x74, 0x0c, 0x81, 0x45, 0xef, 0x61, 0xf1, 0x87,
+ 0xef, 0x65, 0x67, 0x28, 0x1a, 0x54, 0x97, 0xb2,
+ 0xd3, 0x62, 0x00, 0xe7, 0xb6, 0x7a, 0xd5, 0x8e},
+ /* PCR[6] */
+ {0x82, 0xab, 0xc5, 0x6a, 0xbf, 0x08, 0x43, 0x3f,
+ 0x85, 0xbd, 0x8f, 0x8e, 0x23, 0x62, 0x48, 0x4a,
+ 0x44, 0x53, 0xf0, 0xae, 0x8d, 0x4c, 0xda, 0x04,
+ 0x89, 0x9c, 0x0b, 0x81, 0x3a, 0x53, 0xf3, 0xac}
+};
+#elif defined(__riscv) && (__riscv_xlen == 64)
+static u8 expected_pcrs_per_arch[][TPM2_SHA256_DIGEST_SIZE] = {
+ /* PCR[4] */
+ {0x9b, 0x5f, 0x10, 0x24, 0x28, 0x5d, 0x7d, 0x1f,
+ 0x9f, 0xee, 0xe9, 0x90, 0xf1, 0x7a, 0x03, 0xb1,
+ 0x68, 0x7b, 0x28, 0x45, 0x98, 0x5e, 0xf5, 0x5e,
+ 0xc1, 0x22, 0x61, 0x8c, 0x2f, 0xb5, 0xbf, 0x80},
+ /* PCR[6] */
+ {0x6d, 0x16, 0x17, 0xf4, 0x9a, 0xa8, 0x49, 0xc2,
+ 0xf4, 0x9c, 0x35, 0x30, 0x0c, 0xde, 0x65, 0xdb,
+ 0xd3, 0x37, 0x9c, 0xe2, 0x9f, 0x14, 0x81, 0x74,
+ 0xc3, 0x94, 0x8a, 0x9e, 0x26, 0xbf, 0xfb, 0xb2}
+};
+#endif
+
+struct boot_variable {
+ u16 name[16];
+ u8 *buf;
+ efi_uintn_t size;
+ u32 attr;
+ const u8 *test_data;
+ efi_uintn_t test_data_size;
+};
+
+static struct boot_variable boot_variable_test[] = {
+ {u"BootOrder", NULL, 0, DEFAULT_ATTR, boot_order, sizeof(boot_order)},
+ {BOOT_NAME_1000, NULL, 0, DEFAULT_ATTR, boot_1000, sizeof(boot_1000)},
+ {BOOT_NAME_1001, NULL, 0, DEFAULT_ATTR, boot_1001, sizeof(boot_1001)},
+ {BOOT_NAME_1002, NULL, 0, DEFAULT_ATTR, boot_1002, sizeof(boot_1002)},
+};
+
+/*
+ * efi_status_t decompress() - Decompress the disk image.
+ *
+ * @image decompressed disk image
+ * @return status code
+ */
+static efi_status_t decompress(u8 **image)
+{
+ u8 *buf;
+ size_t i;
+ size_t addr;
+ size_t len;
+ efi_status_t ret;
+
+ ret = boottime->allocate_pool(EFI_LOADER_DATA, img.length,
+ (void **)&buf);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Out of memory\n");
+ return ret;
+ }
+ boottime->set_mem(buf, img.length, 0);
+
+ for (i = 0; ; ++i) {
+ if (!img.lines[i].line)
+ break;
+ addr = img.lines[i].addr;
+ len = COMPRESSED_DISK_IMAGE_BLOCK_SIZE;
+ if (addr + len > img.length)
+ len = img.length - addr;
+ boottime->copy_mem(buf + addr, img.lines[i].line, len);
+ }
+ *image = buf;
+ return ret;
+}
+
+/*
+ * efi_status_t setup_boot_variable() - configure dummy boot variables
+ *
+ * Preexisting variable values are saved and will be restored by
+ * calling restore_boot_variable().
+ *
+ * @return status code
+ */
+static efi_status_t setup_boot_variable(void)
+{
+ efi_status_t ret;
+ u32 i;
+ efi_uintn_t size;
+
+ for (i = 0; i < ARRAY_SIZE(boot_variable_test); i++) {
+ size = 0;
+ ret = runtime->get_variable(boot_variable_test[i].name,
+ &efi_global_variable_guid,
+ &boot_variable_test[i].attr,
+ &size,
+ NULL);
+ if (ret == EFI_BUFFER_TOO_SMALL) {
+ /* Variable exists, save the current value */
+ boot_variable_test[i].size = size;
+ ret = boottime->allocate_pool(EFI_LOADER_DATA,
+ boot_variable_test[i].size,
+ (void **)&boot_variable_test[i].buf);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to allocate buffer for boot variable\n");
+ return ret;
+ }
+ ret = runtime->get_variable(boot_variable_test[i].name,
+ &efi_global_variable_guid,
+ &boot_variable_test[i].attr,
+ &boot_variable_test[i].size,
+ boot_variable_test[i].buf);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to get current boot variable\n");
+ return ret;
+ }
+ }
+
+ /* set boot variable for the measurement test */
+ ret = runtime->set_variable(boot_variable_test[i].name,
+ &efi_global_variable_guid,
+ boot_variable_test[i].attr,
+ boot_variable_test[i].test_data_size,
+ boot_variable_test[i].test_data);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to set test boot variable(%d)n", i);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+/*
+ * efi_status_t restore_boot_variable() - restore original values
+ *
+ * Restore the variable values saved in setup_boot_variable().
+ *
+ * @return status code
+ */
+static efi_status_t restore_boot_variable(void)
+{
+ int i;
+ efi_status_t ret;
+
+ for (i = 0; i < ARRAY_SIZE(boot_variable_test); i++) {
+ if (boot_variable_test[i].buf) {
+ ret = runtime->set_variable(boot_variable_test[i].name,
+ &efi_global_variable_guid,
+ boot_variable_test[i].attr,
+ boot_variable_test[i].size,
+ boot_variable_test[i].buf);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to restore boot variable\n");
+ return ret;
+ }
+ ret = boottime->free_pool(boot_variable_test[i].buf);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to free boot variable\n");
+ return ret;
+ }
+ } else {
+ /* delete the variable used only for testing */
+ ret = runtime->set_variable(boot_variable_test[i].name,
+ &efi_global_variable_guid,
+ 0, 0, NULL);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to delete boot variable\n");
+ return ret;
+ }
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ * void *find_smbios_table() - Find smbios table
+ *
+ * @systable system table
+ * @return status code
+ */
+static void *find_smbios_table(const struct efi_system_table *systable)
+{
+ u32 i;
+
+ for (i = 0; i < systable->nr_tables; i++) {
+ if (!guidcmp(&smbios_guid, &systable->tables[i].guid))
+ return systable->tables[i].table;
+ }
+
+ return NULL;
+}
+
+/**
+ * efi_status_t setup_smbios_table() - Prepare the dummy SMBIOS table
+ *
+ * @systable system table
+ * @return status code
+ */
+static efi_status_t setup_smbios_table(const struct efi_system_table *systable)
+{
+ struct smbios_entry *se;
+ efi_status_t ret;
+ /* Map within the low 32 bits, to allow for 32bit SMBIOS tables */
+ void *dmi;
+ char *istart;
+ int isize;
+
+ if (sizeof(smbios_table_test) > EFI_PAGE_SIZE)
+ return EFI_OUT_OF_RESOURCES;
+
+ orig_smbios_table = find_smbios_table(systable);
+
+ /* Reserve 4kiB page for SMBIOS */
+ ret = boottime->allocate_pages(EFI_ALLOCATE_MAX_ADDRESS,
+ EFI_RUNTIME_SERVICES_DATA, 1, &dmi_addr);
+
+ if (ret != EFI_SUCCESS) {
+ /* Could not find space in lowmem, use highmem instead */
+ ret = boottime->allocate_pages(EFI_ALLOCATE_ANY_PAGES,
+ EFI_RUNTIME_SERVICES_DATA, 1,
+ &dmi_addr);
+
+ if (ret != EFI_SUCCESS)
+ return ret;
+ }
+
+ dmi = (void *)(uintptr_t)dmi_addr;
+ se = dmi;
+ boottime->copy_mem(se, smbios_table_test, sizeof(smbios_table_test));
+
+ /* update smbios table start address */
+ se->struct_table_address = (uintptr_t)((u8 *)dmi + SMBIOS_ENTRY_HEADER_SIZE);
+
+ /* calculate checksums */
+ istart = (char *)se + SMBIOS_INTERMEDIATE_OFFSET;
+ isize = sizeof(struct smbios_entry) - SMBIOS_INTERMEDIATE_OFFSET;
+ se->intermediate_checksum = table_compute_checksum(istart, isize);
+ se->checksum = table_compute_checksum(se, sizeof(struct smbios_entry));
+
+ /* Install SMBIOS information as configuration table */
+ ret = boottime->install_configuration_table(&smbios_guid, dmi);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Cannot install SMBIOS table\n");
+ boottime->free_pages(dmi_addr, 1);
+ }
+
+ return ret;
+}
+
/**
* efi_st_tcg2_setup() - setup test
*
static int efi_st_tcg2_setup(const efi_handle_t img_handle,
const struct efi_system_table *systable)
{
+ efi_status_t ret;
+ struct uefi_image_load_event image_load_event;
+
+ image_handle = img_handle;
boottime = systable->boottime;
+ runtime = systable->runtime;
+
+ /* Load the application image into memory */
+ decompress(&image);
+
+ ret = boottime->allocate_pool(EFI_LOADER_DATA,
+ sizeof(struct efi_tcg2_event) +
+ sizeof(struct uefi_image_load_event),
+ (void **)&efi_tcg2_event);
+ if (!efi_tcg2_event)
+ return EFI_ST_FAILURE;
+
+ efi_tcg2_event->size = sizeof(struct efi_tcg2_event) +
+ sizeof(struct uefi_image_load_event);
+ efi_tcg2_event->header.header_size = sizeof(struct efi_tcg2_event_header);
+ efi_tcg2_event->header.header_version = 1;
+ efi_tcg2_event->header.pcr_index = 6;
+ efi_tcg2_event->header.event_type = EV_EFI_RUNTIME_SERVICES_DRIVER;
+ image_load_event.image_location_in_memory = 0x12345678;
+ image_load_event.image_length_in_memory = 0x300000;
+ image_load_event.image_link_time_address = 0x87654321;
+ image_load_event.length_of_device_path = 0;
+ boottime->copy_mem(efi_tcg2_event->event, &image_load_event,
+ sizeof(struct uefi_image_load_event));
+
+ ret = setup_boot_variable();
+ if (ret != EFI_SUCCESS)
+ return EFI_ST_FAILURE;
+
+ ret = setup_smbios_table(systable);
+ if (ret != EFI_SUCCESS)
+ return EFI_ST_FAILURE;
+
+ ret = boottime->allocate_pool(EFI_LOADER_DATA,
+ (EFI_TCG2_MAX_PCR_INDEX + 1) *
+ TPM2_SHA256_DIGEST_SIZE,
+ (void **)&pcrs);
+ if (!pcrs)
+ return EFI_ST_FAILURE;
+
+ boottime->set_mem(pcrs, (EFI_TCG2_MAX_PCR_INDEX + 1) * TPM2_SHA256_DIGEST_SIZE, 0);
+
+ /* setup expected PCRs per architecture */
+ boottime->copy_mem(&expected_pcrs[4], &expected_pcrs_per_arch[0], TPM2_SHA256_DIGEST_SIZE);
+ boottime->copy_mem(&expected_pcrs[6], &expected_pcrs_per_arch[1], TPM2_SHA256_DIGEST_SIZE);
+
+ return EFI_ST_SUCCESS;
+}
+
+/**
+ * efi_status_t get_manufacturer_id() - Get manufacturer_id through submit_command API
+ *
+ * @tcg2 tcg2 protocol
+ * @manufacturer_id pointer to the manufacturer_id
+ * @return status code
+ */
+static efi_status_t get_manufacturer_id(struct efi_tcg2_protocol *tcg2, u32 *manufacturer_id)
+{
+ efi_status_t ret;
+ u8 cmd[TPM2_CMD_BUF_SIZE] = {
+ tpm_u16(TPM2_ST_NO_SESSIONS), /* TAG */
+ tpm_u32(22), /* Length */
+ tpm_u32(TPM2_CC_GET_CAPABILITY), /* Command code */
+
+ tpm_u32(TPM2_CAP_TPM_PROPERTIES), /* Capability */
+ tpm_u32(TPM2_PT_MANUFACTURER), /* Property */
+ tpm_u32(1), /* Property count */
+ };
+ u8 resp[TPM2_CMD_BUF_SIZE];
+ unsigned int value_off;
+
+ ret = tcg2->submit_command(tcg2, 22, cmd,
+ TPM2_CMD_BUF_SIZE, resp);
+ if (ret != EFI_SUCCESS)
+ return ret;
+
+ /*
+ * In the response buffer, the properties are located after the:
+ * tag (u16), response size (u32), response code (u32),
+ * YES/NO flag (u8), TPM_CAP (u32).
+ * The value is located after count (u32), property (u32).
+ */
+ value_off = sizeof(u16) + sizeof(u32) + sizeof(u32) +
+ sizeof(u8) + sizeof(u32) + sizeof(u32) + sizeof(u32);
+ *manufacturer_id = get_unaligned_be32(&resp[value_off]);
+
+ return ret;
+}
+
+/**
+ * efi_status_t get_manufacturer_id_buffer_small() - call submit_command with small resp buffer
+ *
+ * @tcg2 tcg2 protocol
+ * @manufacturer_id pointer to the manufacturer_id
+ * @return status code
+ */
+static efi_status_t get_manufacturer_id_buffer_small(struct efi_tcg2_protocol *tcg2)
+{
+ efi_status_t ret;
+ u8 cmd[TPM2_CMD_BUF_SIZE] = {
+ tpm_u16(TPM2_ST_NO_SESSIONS), /* TAG */
+ tpm_u32(22), /* Length */
+ tpm_u32(TPM2_CC_GET_CAPABILITY), /* Command code */
+
+ tpm_u32(TPM2_CAP_TPM_PROPERTIES), /* Capability */
+ tpm_u32(TPM2_PT_MANUFACTURER), /* Property */
+ tpm_u32(1), /* Property count */
+ };
+ u8 resp[1]; /* set smaller buffer than expected */
+
+ ret = tcg2->submit_command(tcg2, 22, cmd, 1, resp);
+
+ return ret;
+}
+
+/**
+ * efi_status_t read_pcr() - Read the PCR from the TPM device
+ *
+ * @tcg2 tcg2 protocol
+ * @idx pcr index to read
+ * @return status code
+ */
+static efi_status_t read_pcr(struct efi_tcg2_protocol *tcg2, u32 idx)
+{
+ efi_status_t ret;
+ u32 cmd_len = 17 + IDX_ARRAY_SZ;
+ u8 cmd[TPM2_CMD_BUF_SIZE] = {
+ tpm_u16(TPM2_ST_NO_SESSIONS), /* TAG */
+ tpm_u32(cmd_len), /* Length */
+ tpm_u32(TPM2_CC_PCR_READ), /* Command code */
+ /* TPML_PCR_SELECTION */
+ tpm_u32(1), /* Number of selections */
+ tpm_u16(TPM2_ALG_SHA256), /* Algorithm of the hash */
+ IDX_ARRAY_SZ, /* Array size for selection */
+ /* bitmap(idx), Selected PCR bitmap */
+ };
+ u8 resp[TPM2_CMD_BUF_SIZE];
+ u32 pcr_sel_idx = idx / 8;
+ u8 pcr_sel_bit = BIT(idx % 8);
+
+ cmd[17 + pcr_sel_idx] = pcr_sel_bit;
+ ret = tcg2->submit_command(tcg2, cmd_len, cmd,
+ TPM2_CMD_BUF_SIZE, resp);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("tcg2->submit_command fail to read PCR\n");
+ return ret;
+ }
+
+ boottime->copy_mem(pcrs[idx], &resp[TPM2_PCR_READ_HEADER_SIZE],
+ TPM2_SHA256_DIGEST_SIZE);
+
+ return ret;
+}
+
+/**
+ * int validate_pcrs() - Compare the expected and actual pcrs
+ *
+ * @return status code
+ */
+static int validate_pcrs(void)
+{
+ u32 i;
+
+ /*
+ * - Skip PCR[0] validation. PCR[0] contains U-Boot version measurement
+ * it contains the commit hash, so the measurement varies every build
+ * with different commit hash.
+ * - Skip PCR[7] validation. PCR[7] contains UEFI Secure Boot variables
+ * measurement. These variables can not be updated through efi_selftest and
+ * vary depending on the platform.
+ * - Skip PCR[17..22] validation, they are not used in TCG PC Client
+ * Platform Firmware Profile Specification
+ */
+ for (i = 1; i < (EFI_TCG2_MAX_PCR_INDEX + 1); i++) {
+ if (i == 7 || (i > 16 && i < 23))
+ continue; /* skip validation */
+
+ if (memcmp(pcrs[i], expected_pcrs[i], TPM2_SHA256_DIGEST_SIZE)) {
+ efi_st_error("PCR[%d] is not the expected value\n", i);
+ return EFI_ST_FAILURE;
+ }
+ }
return EFI_ST_SUCCESS;
}
/**
* efi_st_tcg2_execute() - execute test
*
- * Call the GetCapability service of the EFI_TCG2_PROTOCOL.
+ * Call EFI_TCG2_PROTOCOL services and check the
+ * Measured Boot behavior.
*
* Return: status code
*/
struct efi_tcg2_protocol *tcg2;
struct efi_tcg2_boot_service_capability capability;
efi_status_t ret;
+ u32 active_pcr_banks;
+ u64 eventlog, eventlog_last_entry;
+ bool eventlog_truncated;
+ efi_handle_t handle;
+ efi_uintn_t exit_data_size = 0;
+ u16 *exit_data = NULL;
+ u32 i;
+ u32 manufacturer_id;
ret = boottime->locate_protocol(&guid_tcg2, NULL, (void **)&tcg2);
if (ret != EFI_SUCCESS) {
efi_st_error("TCG2 protocol is not available.\n");
return EFI_ST_FAILURE;
}
+
+ /* EFI_TCG2_PROTOCOL.GetCapability test */
capability.size = sizeof(struct efi_tcg2_boot_service_capability) - 1;
ret = tcg2->get_capability(tcg2, &capability);
if (ret != EFI_BUFFER_TOO_SMALL) {
}
efi_st_printf("TPM supports 0x%.8x event logs\n",
capability.supported_event_logs);
+
+ /* EFI_TCG2_PROTOCOL.GetActivePcrBanks test */
+ ret = tcg2->get_active_pcr_banks(tcg2, &active_pcr_banks);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("tcg2->get_active_pcr_banks failed\n");
+ return EFI_ST_FAILURE;
+ }
+ if (active_pcr_banks != capability.active_pcr_banks) {
+ efi_st_error("tcg2->get_active_pcr_banks return wrong value\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /* EFI_TCG2_PROTOCOL.HashLogExtendEvent test */
+ ret = tcg2->hash_log_extend_event(tcg2, EFI_TCG2_EXTEND_ONLY,
+ (uintptr_t)image,
+ img.length, efi_tcg2_event);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("tcg2->hash_log_extend_event(EXTEND_ONLY) failed\n");
+ return EFI_ST_FAILURE;
+ }
+
+ ret = tcg2->hash_log_extend_event(tcg2, PE_COFF_IMAGE, (uintptr_t)image,
+ img.length, efi_tcg2_event);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("tcg2->hash_log_extend_event(PE_COFF_IMAGE) failed\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /* EFI_TCG2_PROTOCOL.SubmitCommand test */
+ ret = get_manufacturer_id_buffer_small(tcg2);
+ if (ret != EFI_OUT_OF_RESOURCES) {
+ efi_st_error("get_manufacturer_id buffer too small failed\n");
+ return EFI_ST_FAILURE;
+ }
+
+ ret = get_manufacturer_id(tcg2, &manufacturer_id);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("get_manufacturer_id failed\n");
+ return EFI_ST_FAILURE;
+ }
+ if (capability.manufacturer_id != manufacturer_id) {
+ efi_st_error("tcg2->submit_command test failed\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /* tcg2_measure_pe_image test */
+ ret = boottime->load_image(false, image_handle, NULL, image,
+ img.length, &handle);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to load image\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /* measure ready_to_boot event(boot variables, smbios table, etc.) */
+ /* TODO: add GPT measurement test */
+ ret = boottime->start_image(handle, &exit_data_size, &exit_data);
+ if (ret != EFI_UNSUPPORTED) {
+ efi_st_error("Wrong return value from application\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->free_pool(exit_data);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to free exit data\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /* validate PCR read from the TPM device */
+ for (i = 0; i < (EFI_TCG2_MAX_PCR_INDEX + 1); i++) {
+ ret = read_pcr(tcg2, i);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("read pcr error\n");
+ return EFI_ST_FAILURE;
+ }
+ }
+ if (validate_pcrs()) {
+ efi_st_error("PCR validation failed\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /* EFI_TCG2_PROTOCOL.GetEventLog test */
+ ret = tcg2->get_eventlog(tcg2, TCG2_EVENT_LOG_FORMAT_TCG_2, &eventlog,
+ &eventlog_last_entry, &eventlog_truncated);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("tcg2->get_eventlog failed\n");
+ return EFI_ST_FAILURE;
+ }
+ /* TODO: eventlog format check */
+
return EFI_ST_SUCCESS;
}
+/*
+ * efi_st_tcg2_teardown() - Tear down unit test
+ *
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int efi_st_tcg2_teardown(void)
+{
+ efi_status_t r = EFI_ST_SUCCESS;
+
+ if (image) {
+ r = boottime->free_pool(image);
+ if (r != EFI_SUCCESS) {
+ efi_st_error("Failed to free image\n");
+ return EFI_ST_FAILURE;
+ }
+ }
+ if (efi_tcg2_event) {
+ r = boottime->free_pool(efi_tcg2_event);
+ if (r != EFI_SUCCESS) {
+ efi_st_error("Failed to free efi_tcg2_event\n");
+ return EFI_ST_FAILURE;
+ }
+ }
+ if (pcrs) {
+ r = boottime->free_pool(pcrs);
+ if (r != EFI_SUCCESS) {
+ efi_st_error("Failed to free pcr\n");
+ return EFI_ST_FAILURE;
+ }
+ }
+
+ r = restore_boot_variable();
+ if (r != EFI_SUCCESS) {
+ efi_st_error("Failed to restore boot variables\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /*
+ * Restore SMBIOS table
+ * If orig_smbios_table is NULL, calling install_configuration_table()
+ * removes dummy SMBIOS table form systab.
+ */
+ r = boottime->install_configuration_table(&smbios_guid, orig_smbios_table);
+ if (r != EFI_SUCCESS) {
+ efi_st_error("Failed to restore SMBOIS table\n");
+ return EFI_ST_FAILURE;
+ }
+
+ if (dmi_addr) {
+ r = boottime->free_pages(dmi_addr, 1);
+ if (r != EFI_SUCCESS) {
+ efi_st_error("Failed to free dummy smbios table\n");
+ return EFI_ST_FAILURE;
+ }
+ }
+
+ return r;
+}
+
EFI_UNIT_TEST(tcg2) = {
.name = "tcg2",
.phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
.execute = efi_st_tcg2_execute,
.setup = efi_st_tcg2_setup,
+ .teardown = efi_st_tcg2_teardown,
+ .on_request = true,
};
* For CONFIG_OF_SEPARATE, the board may optionally implement this to
* provide and/or fixup the fdt.
*/
-__weak void *board_fdt_blob_setup(void)
+__weak void *board_fdt_blob_setup(int *err)
{
void *fdt_blob = NULL;
+
+ *err = 0;
#ifdef CONFIG_SPL_BUILD
/* FDT is at end of BSS unless it is in a different memory region */
if (IS_ENABLED(CONFIG_SPL_SEPARATE_BSS))
/* FDT is at end of image */
fdt_blob = (ulong *)&_end;
#endif
+
return fdt_blob;
}
#endif
# endif
# elif defined(CONFIG_OF_BOARD) || defined(CONFIG_OF_SEPARATE)
/* Allow the board to override the fdt address. */
- gd->fdt_blob = board_fdt_blob_setup();
-# elif defined(CONFIG_OF_HOSTFILE)
- if (sandbox_read_fdt_from_file()) {
- puts("Failed to read control FDT\n");
- return -1;
- }
+ gd->fdt_blob = board_fdt_blob_setup(&ret);
+ if (ret)
+ return ret;
# endif
# ifndef CONFIG_SPL_BUILD
/* Allow the early environment to override the fdt address */
config RSA
bool "Use RSA Library"
- select RSA_FREESCALE_EXP if FSL_CAAM && !ARCH_MX7 && !ARCH_MX6 && !ARCH_MX5
+ select RSA_FREESCALE_EXP if FSL_CAAM && !ARCH_MX7 && !ARCH_MX7ULP && !ARCH_MX6 && !ARCH_MX5
select RSA_SOFTWARE_EXP if !RSA_FREESCALE_EXP
help
RSA support. This enables the RSA algorithm used for FIT image
config RSA_FREESCALE_EXP
bool "Enable RSA Modular Exponentiation with FSL crypto accelerator"
- depends on DM && FSL_CAAM && !ARCH_MX7 && !ARCH_MX6 && !ARCH_MX5
+ depends on DM && FSL_CAAM && !ARCH_MX7 && !ARCH_MX7ULP && !ARCH_MX6 && !ARCH_MX5
help
Enables driver for RSA modular exponentiation using Freescale cryptographic
accelerator - CAAM.
struct padding_algo *padding = info->padding;
int hash_len;
- if (!prop || !sig || !hash || !checksum)
+ if (!prop || !sig || !hash || !checksum || !padding)
return -EIO;
if (sig_len != (prop->num_bits / 8)) {
return entry;
}
-static const struct smbios_header *next_header(const struct smbios_header *curr)
+static u8 *find_next_header(u8 *pos)
{
- u8 *pos = ((u8 *)curr) + curr->length;
-
/* search for _double_ NULL bytes */
while (!((*pos == 0) && (*(pos + 1) == 0)))
pos++;
/* step behind the double NULL bytes */
pos += 2;
- return (struct smbios_header *)pos;
+ return pos;
+}
+
+static struct smbios_header *get_next_header(struct smbios_header *curr)
+{
+ u8 *pos = ((u8 *)curr) + curr->length;
+
+ return (struct smbios_header *)find_next_header(pos);
+}
+
+static const struct smbios_header *next_header(const struct smbios_header *curr)
+{
+ u8 *pos = ((u8 *)curr) + curr->length;
+
+ return (struct smbios_header *)find_next_header(pos);
}
const struct smbios_header *smbios_header(const struct smbios_entry *entry, int type)
{
const unsigned int num_header = entry->struct_count;
- const struct smbios_header *header = (struct smbios_header *)entry->struct_table_address;
+ const struct smbios_header *header = (struct smbios_header *)((uintptr_t)entry->struct_table_address);
for (unsigned int i = 0; i < num_header; i++) {
if (header->type == type)
return NULL;
}
-static const char *string_from_smbios_table(const struct smbios_header *header,
- int idx)
+static char *string_from_smbios_table(const struct smbios_header *header,
+ int idx)
{
unsigned int i = 1;
u8 *pos;
pos++;
}
- return (const char *)pos;
+ return (char *)pos;
}
-const char *smbios_string(const struct smbios_header *header, int index)
+char *smbios_string(const struct smbios_header *header, int index)
{
if (!header)
return NULL;
if (!hdr)
return log_msg_ret("tab", -ENOENT);
bios = (struct smbios_type0 *)hdr;
- ptr = (char *)smbios_string(hdr, bios->bios_ver);
+ ptr = smbios_string(hdr, bios->bios_ver);
if (!ptr)
return log_msg_ret("str", -ENOMEDIUM);
return 0;
}
+
+struct smbios_filter_param {
+ u32 offset;
+ u32 size;
+ bool is_string;
+};
+
+struct smbios_filter_table {
+ int type;
+ struct smbios_filter_param *params;
+ u32 count;
+};
+
+struct smbios_filter_param smbios_type1_filter_params[] = {
+ {offsetof(struct smbios_type1, serial_number),
+ FIELD_SIZEOF(struct smbios_type1, serial_number), true},
+ {offsetof(struct smbios_type1, uuid),
+ FIELD_SIZEOF(struct smbios_type1, uuid), false},
+ {offsetof(struct smbios_type1, wakeup_type),
+ FIELD_SIZEOF(struct smbios_type1, wakeup_type), false},
+};
+
+struct smbios_filter_param smbios_type2_filter_params[] = {
+ {offsetof(struct smbios_type2, serial_number),
+ FIELD_SIZEOF(struct smbios_type2, serial_number), true},
+ {offsetof(struct smbios_type2, chassis_location),
+ FIELD_SIZEOF(struct smbios_type2, chassis_location), false},
+};
+
+struct smbios_filter_param smbios_type3_filter_params[] = {
+ {offsetof(struct smbios_type3, serial_number),
+ FIELD_SIZEOF(struct smbios_type3, serial_number), true},
+ {offsetof(struct smbios_type3, asset_tag_number),
+ FIELD_SIZEOF(struct smbios_type3, asset_tag_number), true},
+};
+
+struct smbios_filter_param smbios_type4_filter_params[] = {
+ {offsetof(struct smbios_type4, serial_number),
+ FIELD_SIZEOF(struct smbios_type4, serial_number), true},
+ {offsetof(struct smbios_type4, asset_tag),
+ FIELD_SIZEOF(struct smbios_type4, asset_tag), true},
+ {offsetof(struct smbios_type4, part_number),
+ FIELD_SIZEOF(struct smbios_type4, part_number), true},
+ {offsetof(struct smbios_type4, core_count),
+ FIELD_SIZEOF(struct smbios_type4, core_count), false},
+ {offsetof(struct smbios_type4, core_enabled),
+ FIELD_SIZEOF(struct smbios_type4, core_enabled), false},
+ {offsetof(struct smbios_type4, thread_count),
+ FIELD_SIZEOF(struct smbios_type4, thread_count), false},
+ {offsetof(struct smbios_type4, core_count2),
+ FIELD_SIZEOF(struct smbios_type4, core_count2), false},
+ {offsetof(struct smbios_type4, core_enabled2),
+ FIELD_SIZEOF(struct smbios_type4, core_enabled2), false},
+ {offsetof(struct smbios_type4, thread_count2),
+ FIELD_SIZEOF(struct smbios_type4, thread_count2), false},
+ {offsetof(struct smbios_type4, voltage),
+ FIELD_SIZEOF(struct smbios_type4, voltage), false},
+};
+
+struct smbios_filter_table smbios_filter_tables[] = {
+ {SMBIOS_SYSTEM_INFORMATION, smbios_type1_filter_params,
+ ARRAY_SIZE(smbios_type1_filter_params)},
+ {SMBIOS_BOARD_INFORMATION, smbios_type2_filter_params,
+ ARRAY_SIZE(smbios_type2_filter_params)},
+ {SMBIOS_SYSTEM_ENCLOSURE, smbios_type3_filter_params,
+ ARRAY_SIZE(smbios_type3_filter_params)},
+ {SMBIOS_PROCESSOR_INFORMATION, smbios_type4_filter_params,
+ ARRAY_SIZE(smbios_type4_filter_params)},
+};
+
+static void clear_smbios_table(struct smbios_header *header,
+ struct smbios_filter_param *filter,
+ u32 count)
+{
+ u32 i;
+ char *str;
+ u8 string_id;
+
+ for (i = 0; i < count; i++) {
+ if (filter[i].is_string) {
+ string_id = *((u8 *)header + filter[i].offset);
+ if (string_id == 0) /* string is empty */
+ continue;
+
+ str = smbios_string(header, string_id);
+ if (!str)
+ continue;
+
+ /* string is cleared to space, keep '\0' terminator */
+ memset(str, ' ', strlen(str));
+
+ } else {
+ memset((void *)((u8 *)header + filter[i].offset),
+ 0, filter[i].size);
+ }
+ }
+}
+
+void smbios_prepare_measurement(const struct smbios_entry *entry,
+ struct smbios_header *smbios_copy)
+{
+ u32 i, j;
+ struct smbios_header *header;
+
+ for (i = 0; i < ARRAY_SIZE(smbios_filter_tables); i++) {
+ header = smbios_copy;
+ for (j = 0; j < entry->struct_count; j++) {
+ if (header->type == smbios_filter_tables[i].type)
+ break;
+
+ header = get_next_header(header);
+ }
+ if (j >= entry->struct_count)
+ continue;
+
+ clear_smbios_table(header,
+ smbios_filter_tables[i].params,
+ smbios_filter_tables[i].count);
+ }
+}
return 0;
}
+
+u32 tpm2_submit_command(struct udevice *dev, const u8 *sendbuf,
+ u8 *recvbuf, size_t *recv_size)
+{
+ return tpm_sendrecv_command(dev, sendbuf, recvbuf, recv_size);
+}
if (IS_ENABLED(CONFIG_DM_RNG)) {
ret = uclass_get_device(UCLASS_RNG, 0, &devp);
- if (ret) {
+ if (!ret) {
ret = dm_rng_read(devp, &randv, sizeof(randv));
if (ret < 0)
randv = 0;
}
#endif
+static char local_toa[22];
+
char *simple_itoa(ulong i)
{
/* 21 digits plus null terminator, good for 64-bit or smaller ints */
- static char local[22];
- char *p = &local[21];
+ char *p = &local_toa[21];
*p-- = '\0';
do {
return p + 1;
}
+char *simple_xtoa(ulong num)
+{
+ /* 16 digits plus nul terminator, good for 64-bit or smaller ints */
+ char *p = &local_toa[17];
+
+ *--p = '\0';
+ do {
+ p -= 2;
+ hex_byte_pack(p, num & 0xff);
+ num >>= 8;
+ } while (num > 0);
+
+ return p;
+}
+
/* We don't seem to have %'d in U-Boot */
void print_grouped_ull(unsigned long long int_val, int digits)
{
quiet_cmd_efi_ld = LD $@
cmd_efi_ld = $(LD) -nostdlib -znocombreloc -T $(EFI_LDS_PATH) -shared \
- -Bsymbolic -s $^ -o $@
+ -Bsymbolic -znorelro -s $^ -o $@
EFI_LDS_PATH = $(srctree)/arch/$(ARCH)/lib/$(EFI_LDS)
# Special handling for a few options which support SPL/TPL
ifeq ($(CONFIG_TPL_BUILD),y)
-libs-$(CONFIG_TPL_LIBCOMMON_SUPPORT) += common/ cmd/ env/
+libs-$(CONFIG_TPL_LIBCOMMON_SUPPORT) += boot/ common/ cmd/ env/
libs-$(CONFIG_TPL_LIBGENERIC_SUPPORT) += lib/
else
-libs-$(CONFIG_SPL_LIBCOMMON_SUPPORT) += common/ cmd/ env/
+libs-$(CONFIG_SPL_LIBCOMMON_SUPPORT) += boot/ common/ cmd/ env/
libs-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/
ifdef CONFIG_SPL_FRAMEWORK
libs-$(CONFIG_PARTITIONS) += disk/
# - we have either OF_SEPARATE or OF_HOSTFILE
build_dtb :=
ifneq ($(CONFIG_$(SPL_TPL_)OF_REAL),)
-ifeq ($(CONFIG_OF_SEPARATE)$(CONFIG_OF_HOSTFILE),y)
+ifeq ($(CONFIG_OF_SEPARATE)$(CONFIG_SANDBOX),y)
build_dtb := y
endif
endif
--- /dev/null
+#!/bin/bash
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Script to build an EFI thing suitable for booting with QEMU, possibly running
+# it also.
+
+# This just an example. It assumes that
+
+# - you build U-Boot in ${ubdir}/<name> where <name> is the U-Boot board config
+# - /mnt/x is a directory used for mounting
+# - you have access to the 'pure UEFI' builds for QEMU
+#
+# UEFI binaries for QEMU used for testing this script:
+#
+# OVMF-pure-efi.i386.fd at
+# https://drive.google.com/file/d/1jWzOAZfQqMmS2_dAK2G518GhIgj9r2RY/view?usp=sharing
+
+# OVMF-pure-efi.x64.fd at
+# https://drive.google.com/file/d/1c39YI9QtpByGQ4V0UNNQtGqttEzS-eFV/view?usp=sharing
+
+set -e
+
+usage() {
+ echo "Usage: $0 [-a | -p] [other opts]" 1>&2
+ echo 1>&2
+ echo " -a - Package up the app" 1>&2
+ echo " -o - Use old EFI app build (before 32/64 split)" 1>&2
+ echo " -p - Package up the payload" 1>&2
+ echo " -P - Create a partition table" 1>&2
+ echo " -r - Run QEMU with the image" 1>&2
+ echo " -s - Run QEMU with serial only (no display)" 1>&2
+ echo " -w - Use word version (32-bit)" 1>&2
+ exit 1
+}
+
+# 32- or 64-bit EFI
+bitness=64
+
+# app or payload ?
+type=app
+
+# create a partition table and put the filesystem in that (otherwise put the
+# filesystem in the raw device)
+part=
+
+# run the image with QEMU
+run=
+
+# run QEMU without a display (U-Boot must be set to stdout=serial)
+serial=
+
+# before the 32/64 split of the app
+old=
+
+# Set ubdir to the build directory where you build U-Boot out-of-tree
+# We avoid in-tree build because it gets confusing trying different builds
+ubdir=/tmp/b/
+
+while getopts "aopPrsw" opt; do
+ case "${opt}" in
+ a)
+ type=app
+ ;;
+ p)
+ type=payload
+ ;;
+ r)
+ run=1
+ ;;
+ s)
+ serial=1
+ ;;
+ w)
+ bitness=32
+ ;;
+ o)
+ old=1
+ ;;
+ P)
+ part=1
+ ;;
+ *)
+ usage
+ ;;
+ esac
+done
+
+run_qemu() {
+ extra=
+ if [[ "${bitness}" = "64" ]]; then
+ qemu=qemu-system-x86_64
+ bios=OVMF-pure-efi.x64.fd
+ else
+ qemu=qemu-system-i386
+ bios=OVMF-pure-efi.i386.fd
+ fi
+ if [[ -n "${serial}" ]]; then
+ extra="-display none -serial mon:stdio"
+ fi
+ echo "Running ${qemu}"
+ # Use 512MB since U-Boot EFI likes to have 256MB to play with
+ "${qemu}" -bios "${bios}" \
+ -m 512 \
+ -drive id=disk,file="${IMG}",if=none,format=raw \
+ -nic none -device ahci,id=ahci \
+ -device ide-hd,drive=disk,bus=ahci.0 ${extra}
+}
+
+setup_files() {
+ echo "Packaging ${BUILD}"
+ mkdir -p $TMP
+ cat >$TMP/startup.nsh <<EOF
+fs0:u-boot-${type}.efi
+EOF
+ sudo cp ${ubdir}/${BUILD}/u-boot-${type}.efi $TMP
+
+ # Can copy in other files here:
+ #sudo cp ${ubdir}/$BUILD/image.bin $TMP/chromeos.rom
+ #sudo cp /boot/vmlinuz-5.4.0-77-generic $TMP/vmlinuz
+}
+
+# Copy files into the filesystem
+copy_files() {
+ sudo cp $TMP/* $MNT
+}
+
+# Create a filesystem on a raw device and copy in the files
+setup_raw() {
+ mkfs.vfat "${IMG}" >/dev/null
+ sudo mount -o loop "${IMG}" $MNT
+ copy_files
+ sudo umount $MNT
+}
+
+# Create a partition table and put the filesystem in the first partition
+# then copy in the files
+setup_part() {
+ # Create a gpt partition table with one partition
+ parted "${IMG}" mklabel gpt 2>/dev/null
+
+ # This doesn't work correctly. It creates:
+ # Number Start End Size File system Name Flags
+ # 1 1049kB 24.1MB 23.1MB boot msftdata
+ # Odd if the same is entered interactively it does set the FS type
+ parted -s -a optimal -- "${IMG}" mkpart boot fat32 1MiB 23MiB
+
+ # Map this partition to a loop device
+ kp="$(sudo kpartx -av ${IMG})"
+ read boot_dev<<<$(grep -o 'loop.*p.' <<< "${kp}")
+ test "${boot_dev}"
+ dev="/dev/mapper/${boot_dev}"
+
+ mkfs.vfat "${dev}" >/dev/null
+
+ sudo mount -o loop "${dev}" $MNT
+
+ copy_files
+
+ # Sync here since this makes kpartx more likely to work the first time
+ sync
+ sudo umount $MNT
+
+ # For some reason this needs a sleep or it sometimes fails, if it was
+ # run recently (in the last few seconds)
+ if ! sudo kpartx -d "${IMG}" > /dev/null; then
+ sleep .5
+ sudo kpartx -d "${IMG}" > /dev/null || \
+ echo "Failed to remove ${boot_dev}, use: sudo kpartx -d ${IMG}"
+ fi
+}
+
+TMP="/tmp/efi${bitness}${type}"
+MNT=/mnt/x
+BUILD="efi-x86_${type}${bitness}"
+IMG=try.img
+
+if [[ -n "${old}" && "${bitness}" = "32" ]]; then
+ BUILD="efi-x86_${type}"
+fi
+
+setup_files
+
+qemu-img create "${IMG}" 24M >/dev/null
+
+if [[ -n "${part}" ]]; then
+ setup_part
+else
+ setup_raw
+fi
+
+if [[ -n "${run}" ]]; then
+ run_qemu
+fi
CONFIG_ARCH_ADPAG101P
CONFIG_ARCH_HAS_ILOG2_U32
CONFIG_ARCH_HAS_ILOG2_U64
-CONFIG_ARCH_MAP_SYSMEM
CONFIG_ARCH_OMAP4
CONFIG_ARCH_RMOBILE_EXTRAM_BOOT
CONFIG_ARCH_USE_BUILTIN_BSWAP
CONFIG_EXYNOS5250
CONFIG_EXYNOS5420
CONFIG_EXYNOS5_DT
-CONFIG_EXYNOS7420
CONFIG_EXYNOS_ACE_SHA
CONFIG_EXYNOS_DP
CONFIG_EXYNOS_FB
CONFIG_I2C_GSC
CONFIG_I2C_MBB_TIMEOUT
CONFIG_I2C_MULTI_BUS
-CONFIG_I2C_MV
CONFIG_I2C_MVTWSI
CONFIG_I2C_MVTWSI_BASE
CONFIG_I2C_MVTWSI_BASE0
CONFIG_LS102XA_STREAM_ID
CONFIG_LSCHLV2
CONFIG_LSXHL
-CONFIG_LYNXKDI
CONFIG_M41T94_SPI_CS
CONFIG_M520x
CONFIG_M5301x
CONFIG_SERIAL_BOOT
CONFIG_SERIAL_FLASH
CONFIG_SERIAL_HW_FLOW_CONTROL
-CONFIG_SERIAL_MULTI
CONFIG_SERIAL_SOFTWARE_FIFO
CONFIG_SERIRQ_CONTINUOUS_MODE
CONFIG_SERVERIP
CONFIG_SYS_FM2_DTSEC4_PHY_ADDR
CONFIG_SYS_FM2_DTSEC_MDIO_ADDR
CONFIG_SYS_FM2_TGEC_MDIO_ADDR
-CONFIG_SYS_FMAN_FW_ADDR
CONFIG_SYS_FMAN_V3
CONFIG_SYS_FM_MURAM_SIZE
CONFIG_SYS_FORM_3U_CPCI
CONFIG_SYS_PTDPAR
CONFIG_SYS_PTV
CONFIG_SYS_PUAPAR
-CONFIG_SYS_QE_FMAN_FW_LENGTH
-CONFIG_SYS_QE_FW_ADDR
CONFIG_SYS_QMAN_CENA_BASE
CONFIG_SYS_QMAN_CENA_SIZE
CONFIG_SYS_QMAN_CINH_BASE
CONFIG_XGI_XG22_BASE
CONFIG_XSENGINE
CONFIG_XTFPGA
-CONFIG_YAFFSFS_PROVIDE_VALUES
CONFIG_YAFFS_AUTO_UNICODE
CONFIG_YAFFS_CASE_INSENSITIVE
CONFIG_YAFFS_DEFINES_TYPES
-CONFIG_YAFFS_DIRECT
-CONFIG_YAFFS_PROVIDE_DEFS
CONFIG_YAFFS_UNICODE
CONFIG_YAFFS_UTIL
CONFIG_YAFFS_WINCE
obj-$(CONFIG_SOUND) += i2s.o
obj-y += irq.o
obj-$(CONFIG_CLK_K210_SET_RATE) += k210_pll.o
+obj-$(CONFIG_IOMMU) += iommu.o
obj-$(CONFIG_LED) += led.o
obj-$(CONFIG_DM_MAILBOX) += mailbox.o
obj-$(CONFIG_DM_MDIO) += mdio.o
obj-$(CONFIG_DM_USB) += usb.o
obj-$(CONFIG_DM_VIDEO) += video.o
obj-$(CONFIG_VIRTIO_SANDBOX) += virtio.o
-obj-$(CONFIG_WDT) += wdt.o
+ifeq ($(CONFIG_WDT_GPIO)$(CONFIG_WDT_SANDBOX),yy)
+obj-y += wdt.o
+endif
endif
endif # !SPL
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 Mark Kettenis <kettenis@openbsd.org>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/test.h>
+#include <dm/uclass-internal.h>
+#include <iommu.h>
+#include <test/test.h>
+#include <test/ut.h>
+
+static int dm_test_iommu(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+
+ ut_assertok(uclass_find_device(UCLASS_IOMMU, 0, &dev));
+ ut_assert(!(dev_get_flags(dev) & DM_FLAG_ACTIVATED));
+
+ /* Probing USB probes the IOMMU through the "iommus" property */
+ ut_assertok(uclass_probe_all(UCLASS_USB));
+ ut_assert(dev_get_flags(dev) & DM_FLAG_ACTIVATED);
+
+ return 0;
+}
+
+DM_TEST(dm_test_iommu, UT_TESTF_SCAN_FDT);
return 0;
}
DM_TEST(dm_test_ofnode_conf, 0);
+
+static int dm_test_ofnode_for_each_compatible_node(struct unit_test_state *uts)
+{
+ const char compatible[] = "denx,u-boot-fdt-test";
+ bool found = false;
+ ofnode node;
+
+ ofnode_for_each_compatible_node(node, compatible) {
+ ut_assert(ofnode_device_is_compatible(node, compatible));
+ found = true;
+ }
+
+ /* There should be at least one matching node */
+ ut_assert(found);
+
+ return 0;
+}
+DM_TEST(dm_test_ofnode_for_each_compatible_node, UT_TESTF_SCAN_FDT);
#include <log.h>
#include <mapmem.h>
#include <version_string.h>
+#include <vsprintf.h>
#include <test/suites.h>
#include <test/test.h>
#include <test/ut.h>
}
PRINT_TEST(print_do_hex_dump, UT_TESTF_CONSOLE_REC);
+static int print_itoa(struct unit_test_state *uts)
+{
+ ut_asserteq_str("123", simple_itoa(123));
+ ut_asserteq_str("0", simple_itoa(0));
+ ut_asserteq_str("2147483647", simple_itoa(0x7fffffff));
+ ut_asserteq_str("4294967295", simple_itoa(0xffffffff));
+
+ /* Use #ifdef here to avoid a compiler warning on 32-bit machines */
+#ifdef CONFIG_PHYS_64BIT
+ if (sizeof(ulong) == 8) {
+ ut_asserteq_str("9223372036854775807",
+ simple_itoa((1UL << 63) - 1));
+ ut_asserteq_str("18446744073709551615", simple_itoa(-1));
+ }
+#endif /* CONFIG_PHYS_64BIT */
+
+ return 0;
+}
+PRINT_TEST(print_itoa, 0);
+
+static int print_xtoa(struct unit_test_state *uts)
+{
+ ut_asserteq_str("7f", simple_xtoa(127));
+ ut_asserteq_str("00", simple_xtoa(0));
+ ut_asserteq_str("7fffffff", simple_xtoa(0x7fffffff));
+ ut_asserteq_str("ffffffff", simple_xtoa(0xffffffff));
+
+ /* Use #ifdef here to avoid a compiler warning on 32-bit machines */
+#ifdef CONFIG_PHYS_64BIT
+ if (sizeof(ulong) == 8) {
+ ut_asserteq_str("7fffffffffffffff",
+ simple_xtoa((1UL << 63) - 1));
+ ut_asserteq_str("ffffffffffffffff", simple_xtoa(-1));
+ }
+#endif /* CONFIG_PHYS_64BIT */
+
+ return 0;
+}
+PRINT_TEST(print_xtoa, 0);
+
int do_ut_print(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
struct unit_test *tests = UNIT_TEST_SUITE_START(print_test);
hostprogs-$(CONFIG_CMD_BOOTEFI_SELFTEST) += file2include
-FIT_OBJS-y := fit_common.o fit_image.o image-host.o common/image-fit.o
-FIT_SIG_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := image-sig-host.o common/image-fit-sig.o
-FIT_CIPHER_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := common/image-cipher.o
+FIT_OBJS-y := fit_common.o fit_image.o image-host.o boot/image-fit.o
+FIT_SIG_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := image-sig-host.o boot/image-fit-sig.o
+FIT_CIPHER_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := boot/image-cipher.o
# The following files are synced with upstream DTC.
# Use synced versions from scripts/dtc/libfdt/.
$(FIT_OBJS-y) \
$(FIT_SIG_OBJS-y) \
$(FIT_CIPHER_OBJS-y) \
- common/fdt_region.o \
- common/bootm.o \
+ boot/fdt_region.o \
+ boot/bootm.o \
lib/crc32.o \
default_image.o \
lib/fdtdec_common.o \
lib/fdtdec.o \
- common/image.o \
- common/image-host.o \
+ boot/image.o \
+ boot/image-host.o \
imagetool.o \
imximage.o \
imx8image.o \
update_octeon_header-objs := update_octeon_header.o lib/crc32.o
hostprogs-y += fdtgrep
-fdtgrep-objs += $(LIBFDT_OBJS) common/fdt_region.o fdtgrep.o
+fdtgrep-objs += $(LIBFDT_OBJS) boot/fdt_region.o fdtgrep.o
ifneq ($(TOOLS_ONLY),y)
hostprogs-y += spl_size_limit
quiet_cmd_wrap = WRAP $@
cmd_wrap = echo "\#include <../$(patsubst $(obj)/%,%,$@)>" >$@
-$(obj)/lib/%.c $(obj)/common/%.c $(obj)/env/%.c:
+$(obj)/boot/%.c $(obj)/common/%.c $(obj)/env/%.c $(obj)/lib/%.c:
$(call cmd,wrap)
clean-dirs := lib common
# u_boot_dtsi_options_debug = $(u_boot_dtsi_options_raw)
+Updating an ELF file
+====================
+
+For the EFI app, where U-Boot is loaded from UEFI and runs as an app, there is
+no way to update the devicetree after U-Boot is built. Normally this works by
+creating a new u-boot.dtb.out with he updated devicetree, which is automatically
+built into the output image. With ELF this is not possible since the ELF is
+not part of an image, just a stand-along file. We must create an updated ELF
+file with the new devicetree.
+
+This is handled by the --update-fdt-in-elf option. It takes four arguments,
+separated by comma:
+
+ infile - filename of input ELF file, e.g. 'u-boot's
+ outfile - filename of output ELF file, e.g. 'u-boot.out'
+ begin_sym - symbol at the start of the embedded devicetree, e.g.
+ '__dtb_dt_begin'
+ end_sym - symbol at the start of the embedded devicetree, e.g.
+ '__dtb_dt_end'
+
+When this flag is used, U-Boot does all the normal packaging, but as an
+additional step, it creates a new ELF file with the new devicetree embedded in
+it.
+
+If logging is enabled you will see a message like this::
+
+ Updating file 'u-boot' with data length 0x400a (16394) between symbols
+ '__dtb_dt_begin' and '__dtb_dt_end'
+
+There must be enough space for the updated devicetree. If not, an error like
+the following is produced::
+
+ ValueError: Not enough space in 'u-boot' for data length 0x400a (16394);
+ size is 0x1744 (5956)
+
+
Entry Documentation
===================
'given')
build_parser.add_argument('-u', '--update-fdt', action='store_true',
default=False, help='Update the binman node with offset/size info')
+ build_parser.add_argument('--update-fdt-in-elf', type=str,
+ help='Update an ELF file with the output dtb: infile,outfile,begin_sym,end_sym')
entry_parser = subparsers.add_parser('entry-docs',
help='Write out entry documentation (see entries.rst)')
replace_parser.add_argument('-C', '--compressed', action='store_true',
help='Input data is already compressed if needed for the entry')
replace_parser.add_argument('-i', '--image', type=str, required=True,
- help='Image filename to extract')
+ help='Image filename to update')
replace_parser.add_argument('-f', '--filename', type=str,
help='Input filename to read from')
replace_parser.add_argument('-F', '--fix-size', action='store_true',
replace_parser.add_argument('-m', '--map', action='store_true',
default=False, help='Output a map file for the updated image')
replace_parser.add_argument('paths', type=str, nargs='*',
- help='Paths within file to extract (wildcard)')
+ help='Paths within file to replace (wildcard)')
test_parser = subparsers.add_parser('test', help='Run tests')
test_parser.add_argument('-P', '--processes', type=int,
Args:
image_fname: Image filename to process
- input_fname: Single input ilename to use if replacing one file, None
+ input_fname: Single input filename to use if replacing one file, None
otherwise
indir: Input directory to use (for any number of files), else None
- entry_paths: List of entry paths to extract
+ entry_paths: List of entry paths to replace
do_compress: True if the input data is uncompressed and may need to be
compressed if the entry requires it, False if the data is already
compressed.
tools.FinaliseOutputDir()
return 0
+ elf_params = None
+ if args.update_fdt_in_elf:
+ elf_params = args.update_fdt_in_elf.split(',')
+ if len(elf_params) != 4:
+ raise ValueError('Invalid args %s to --update-fdt-in-elf: expected infile,outfile,begin_sym,end_sym' %
+ elf_params)
+
# Try to figure out which device tree contains our image description
if args.dt:
dtb_fname = args.dt
for dtb_item in state.GetAllFdts():
tools.WriteFile(dtb_item._fname, dtb_item.GetContents())
+ if elf_params:
+ data = state.GetFdtForEtype('u-boot-dtb').GetContents()
+ elf.UpdateFile(*elf_params, data)
+
if missing:
tout.Warning("\nSome images are invalid")
except: # pragma: no cover
ELF_TOOLS = False
-Symbol = namedtuple('Symbol', ['section', 'address', 'size', 'weak'])
+# Information about an EFL symbol:
+# section (str): Name of the section containing this symbol
+# address (int): Address of the symbol (its value)
+# size (int): Size of the symbol in bytes
+# weak (bool): True if the symbol is weak
+# offset (int or None): Offset of the symbol's data in the ELF file, or None if
+# not known
+Symbol = namedtuple('Symbol', ['section', 'address', 'size', 'weak', 'offset'])
# Information about an ELF file:
# data: Extracted program contents of ELF file (this would be loaded by an
section, size = parts[:2]
if len(parts) > 2:
name = parts[2] if parts[2] != '.hidden' else parts[3]
- syms[name] = Symbol(section, int(value, 16), int(size,16),
- flags[1] == 'w')
+ syms[name] = Symbol(section, int(value, 16), int(size, 16),
+ flags[1] == 'w', None)
+
+ # Sort dict by address
+ return OrderedDict(sorted(syms.items(), key=lambda x: x[1].address))
+
+def GetSymbolFileOffset(fname, patterns):
+ """Get the symbols from an ELF file
+
+ Args:
+ fname: Filename of the ELF file to read
+ patterns: List of regex patterns to search for, each a string
+
+ Returns:
+ None, if the file does not exist, or Dict:
+ key: Name of symbol
+ value: Hex value of symbol
+ """
+ def _GetFileOffset(elf, addr):
+ for seg in elf.iter_segments():
+ seg_end = seg['p_vaddr'] + seg['p_filesz']
+ if seg.header['p_type'] == 'PT_LOAD':
+ if addr >= seg['p_vaddr'] and addr < seg_end:
+ return addr - seg['p_vaddr'] + seg['p_offset']
+
+ if not ELF_TOOLS:
+ raise ValueError('Python elftools package is not available')
+
+ syms = {}
+ with open(fname, 'rb') as fd:
+ elf = ELFFile(fd)
+
+ re_syms = re.compile('|'.join(patterns))
+ for section in elf.iter_sections():
+ if isinstance(section, SymbolTableSection):
+ for symbol in section.iter_symbols():
+ if not re_syms or re_syms.search(symbol.name):
+ addr = symbol.entry['st_value']
+ syms[symbol.name] = Symbol(
+ section.name, addr, symbol.entry['st_size'],
+ symbol.entry['st_info']['bind'] == 'STB_WEAK',
+ _GetFileOffset(elf, addr))
# Sort dict by address
return OrderedDict(sorted(syms.items(), key=lambda x: x[1].address))
segment.data()[offset:])
return ElfInfo(output, data_start, elf.header['e_entry'] + virt_to_phys,
mem_end - data_start)
+
+def UpdateFile(infile, outfile, start_sym, end_sym, insert):
+ tout.Notice("Creating file '%s' with data length %#x (%d) between symbols '%s' and '%s'" %
+ (outfile, len(insert), len(insert), start_sym, end_sym))
+ syms = GetSymbolFileOffset(infile, [start_sym, end_sym])
+ if len(syms) != 2:
+ raise ValueError("Expected two symbols '%s' and '%s': got %d: %s" %
+ (start_sym, end_sym, len(syms),
+ ','.join(syms.keys())))
+
+ size = syms[end_sym].offset - syms[start_sym].offset
+ if len(insert) > size:
+ raise ValueError("Not enough space in '%s' for data length %#x (%d); size is %#x (%d)" %
+ (infile, len(insert), len(insert), size, size))
+
+ data = tools.ReadFile(infile)
+ newdata = data[:syms[start_sym].offset]
+ newdata += insert + tools.GetBytes(0, size - len(insert))
+ newdata += data[syms[end_sym].offset:]
+ tools.WriteFile(outfile, newdata)
+ tout.Info('Written to offset %#x' % syms[start_sym].offset)
import os
import shutil
+import struct
import sys
import tempfile
import unittest
# correctly. So drop any make flags here.
if 'MAKEFLAGS' in os.environ:
del os.environ['MAKEFLAGS']
- tools.Run('make', '-C', target_dir, '-f',
- os.path.join(testdir, 'Makefile'), 'SRC=%s/' % testdir)
+ try:
+ tools.Run('make', '-C', target_dir, '-f',
+ os.path.join(testdir, 'Makefile'), 'SRC=%s/' % testdir)
+ except ValueError as e:
+ # The test system seems to suppress this in a strange way
+ print(e)
class TestElf(unittest.TestCase):
elf.DecodeElf(data, load + 2))
shutil.rmtree(outdir)
+ def testEmbedData(self):
+ """Test for the GetSymbolFileOffset() function"""
+ if not elf.ELF_TOOLS:
+ self.skipTest('Python elftools not available')
+
+ fname = self.ElfTestFile('embed_data')
+ offset = elf.GetSymbolFileOffset(fname, ['embed_start', 'embed_end'])
+ start = offset['embed_start'].offset
+ end = offset['embed_end'].offset
+ data = tools.ReadFile(fname)
+ embed_data = data[start:end]
+ expect = struct.pack('<III', 0x1234, 0x5678, 0)
+ self.assertEqual(expect, embed_data)
+
+ def testEmbedFail(self):
+ """Test calling GetSymbolFileOffset() without elftools"""
+ try:
+ old_val = elf.ELF_TOOLS
+ elf.ELF_TOOLS = False
+ fname = self.ElfTestFile('embed_data')
+ with self.assertRaises(ValueError) as e:
+ elf.GetSymbolFileOffset(fname, ['embed_start', 'embed_end'])
+ self.assertIn('Python elftools package is not available',
+ str(e.exception))
+ finally:
+ elf.ELF_TOOLS = old_val
+
+ def testEmbedDataNoSym(self):
+ """Test for GetSymbolFileOffset() getting no symbols"""
+ if not elf.ELF_TOOLS:
+ self.skipTest('Python elftools not available')
+
+ fname = self.ElfTestFile('embed_data')
+ offset = elf.GetSymbolFileOffset(fname, ['missing_sym'])
+ self.assertEqual({}, offset)
+
if __name__ == '__main__':
unittest.main()
entry_args=None, images=None, use_real_dtb=False,
use_expanded=False, verbosity=None, allow_missing=False,
extra_indirs=None, threads=None,
- test_section_timeout=False):
+ test_section_timeout=False, update_fdt_in_elf=None):
"""Run binman with a given test file
Args:
extra_indirs: Extra input directories to add using -I
threads: Number of threads to use (None for default, 0 for
single-threaded)
+ test_section_timeout: True to force the first time to timeout, as
+ used in testThreadTimeout()
+ update_fdt_in_elf: Value to pass with --update-fdt-in-elf=xxx
+
+ Returns:
+ int return code, 0 on success
"""
args = []
if debug:
args.append('-a%s=%s' % (arg, value))
if allow_missing:
args.append('-M')
+ if update_fdt_in_elf:
+ args += ['--update-fdt-in-elf', update_fdt_in_elf]
if images:
for image in images:
args += ['-i', image]
with self.assertRaises(ValueError) as e:
self._DoTestFile('202_section_timeout.dts',
test_section_timeout=True)
- self.assertIn("Node '/binman/section@0': Timed out obtaining contents",
- str(e.exception))
+ self.assertIn("Timed out obtaining contents", str(e.exception))
def testTiming(self):
"""Test output of timing information"""
self.assertIn('read:', stdout.getvalue())
self.assertIn('compress:', stdout.getvalue())
+ def testUpdateFdtInElf(self):
+ """Test that we can update the devicetree in an ELF file"""
+ infile = elf_fname = self.ElfTestFile('u_boot_binman_embed')
+ outfile = os.path.join(self._indir, 'u-boot.out')
+ begin_sym = 'dtb_embed_begin'
+ end_sym = 'dtb_embed_end'
+ retcode = self._DoTestFile(
+ '060_fdt_update.dts', update_dtb=True,
+ update_fdt_in_elf=','.join([infile,outfile,begin_sym,end_sym]))
+ self.assertEqual(0, retcode)
+
+ # Check that the output file does in fact contact a dtb with the binman
+ # definition in the correct place
+ syms = elf.GetSymbolFileOffset(infile,
+ ['dtb_embed_begin', 'dtb_embed_end'])
+ data = tools.ReadFile(outfile)
+ dtb_data = data[syms['dtb_embed_begin'].offset:
+ syms['dtb_embed_end'].offset]
+
+ dtb = fdt.Fdt.FromData(dtb_data)
+ dtb.Scan()
+ props = self._GetPropTree(dtb, BASE_DTB_PROPS + REPACK_DTB_PROPS)
+ self.assertEqual({
+ 'image-pos': 0,
+ 'offset': 0,
+ '_testing:offset': 32,
+ '_testing:size': 2,
+ '_testing:image-pos': 32,
+ 'section@0/u-boot:offset': 0,
+ 'section@0/u-boot:size': len(U_BOOT_DATA),
+ 'section@0/u-boot:image-pos': 0,
+ 'section@0:offset': 0,
+ 'section@0:size': 16,
+ 'section@0:image-pos': 0,
+
+ 'section@1/u-boot:offset': 0,
+ 'section@1/u-boot:size': len(U_BOOT_DATA),
+ 'section@1/u-boot:image-pos': 16,
+ 'section@1:offset': 16,
+ 'section@1:size': 16,
+ 'section@1:image-pos': 16,
+ 'size': 40
+ }, props)
+
+ def testUpdateFdtInElfInvalid(self):
+ """Test that invalid args are detected with --update-fdt-in-elf"""
+ with self.assertRaises(ValueError) as e:
+ self._DoTestFile('060_fdt_update.dts', update_fdt_in_elf='fred')
+ self.assertIn("Invalid args ['fred'] to --update-fdt-in-elf",
+ str(e.exception))
+
+ def testUpdateFdtInElfNoSyms(self):
+ """Test that missing symbols are detected with --update-fdt-in-elf"""
+ infile = elf_fname = self.ElfTestFile('u_boot_binman_embed')
+ outfile = ''
+ begin_sym = 'wrong_begin'
+ end_sym = 'wrong_end'
+ with self.assertRaises(ValueError) as e:
+ self._DoTestFile(
+ '060_fdt_update.dts',
+ update_fdt_in_elf=','.join([infile,outfile,begin_sym,end_sym]))
+ self.assertIn("Expected two symbols 'wrong_begin' and 'wrong_end': got 0:",
+ str(e.exception))
+
+ def testUpdateFdtInElfTooSmall(self):
+ """Test that an over-large dtb is detected with --update-fdt-in-elf"""
+ infile = elf_fname = self.ElfTestFile('u_boot_binman_embed_sm')
+ outfile = os.path.join(self._indir, 'u-boot.out')
+ begin_sym = 'dtb_embed_begin'
+ end_sym = 'dtb_embed_end'
+ with self.assertRaises(ValueError) as e:
+ self._DoTestFile(
+ '060_fdt_update.dts', update_dtb=True,
+ update_fdt_in_elf=','.join([infile,outfile,begin_sym,end_sym]))
+ self.assertRegex(
+ str(e.exception),
+ "Not enough space in '.*u_boot_binman_embed_sm' for data length.*")
+
if __name__ == "__main__":
unittest.main()
LDS_BINMAN := -T $(SRC)u_boot_binman_syms.lds
LDS_BINMAN_BAD := -T $(SRC)u_boot_binman_syms_bad.lds
LDS_BINMAN_X86 := -T $(SRC)u_boot_binman_syms_x86.lds
+LDS_BINMAN_EMBED := -T $(SRC)u_boot_binman_embed.lds
TARGETS = u_boot_ucode_ptr u_boot_no_ucode_ptr bss_data \
u_boot_binman_syms u_boot_binman_syms.bin u_boot_binman_syms_bad \
- u_boot_binman_syms_size u_boot_binman_syms_x86
+ u_boot_binman_syms_size u_boot_binman_syms_x86 embed_data \
+ u_boot_binman_embed u_boot_binman_embed_sm
all: $(TARGETS)
bss_data: CFLAGS += $(SRC)bss_data.lds
bss_data: bss_data.c
+embed_data: CFLAGS += $(SRC)embed_data.lds
+embed_data: embed_data.c
+
u_boot_binman_syms.bin: u_boot_binman_syms
$(OBJCOPY) -O binary $< -R .note.gnu.build-id $@
u_boot_binman_syms_size: CFLAGS += $(LDS_BINMAN)
u_boot_binman_syms_size: u_boot_binman_syms_size.c
+u_boot_binman_embed: CFLAGS += $(LDS_BINMAN_EMBED)
+u_boot_binman_embed: u_boot_binman_embed.c
+
+u_boot_binman_embed_sm: CFLAGS += $(LDS_BINMAN_EMBED)
+u_boot_binman_embed_sm: u_boot_binman_embed_sm.c
+
clean:
rm -f $(TARGETS)
/*
* Copyright (c) 2016 Google, Inc
*
- * Simple program to create a _dt_ucode_base_size symbol which can be read
+ * Simple program to create a bss_data region so the symbol can be read
* by binutils. This is used by binman tests.
*/
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Google LLC
+ *
+ * Simple program including some embedded data that can be accessed by binman.
+ * This is used by binman tests.
+ */
+
+int first[10] = {1};
+int embed[3] __attribute__((section(".embed"))) = {0x1234, 0x5678};
+int second[10] = {1};
+
+int main(void)
+{
+ return 0;
+}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 Google LLC
+ */
+
+OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
+OUTPUT_ARCH(i386)
+ENTRY(_start)
+
+SECTIONS
+{
+ _start = .;
+ __data_start = .;
+ .data :
+ {
+ . = ALIGN(32);
+ embed_start = .;
+ *(.embed*)
+ embed_end = .;
+ . = ALIGN(32);
+ *(.data*)
+ }
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Google LLC
+ *
+ * Simple program to embed a devicetree. This is used by binman tests.
+ */
+
+int __attribute__((section(".mydtb"))) dtb_data[4096];
+
+int main(void)
+{
+ return 0;
+}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2016 Google, Inc
+ */
+
+OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
+OUTPUT_ARCH(i386)
+ENTRY(_start)
+
+SECTIONS
+{
+ . = 0x00000000;
+ _start = .;
+
+ . = ALIGN(4);
+ .text :
+ {
+ *(.text*)
+ }
+
+ . = ALIGN(4);
+ .data : {
+ dtb_embed_begin = .;
+ KEEP(*(.mydtb));
+ dtb_embed_end = .;
+ }
+ .interp : { *(.interp*) }
+
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Google LLC
+ *
+ * Simple program to embed a devicetree. This is used by binman tests.
+ */
+
+int __attribute__((section(".mydtb"))) dtb_data[16];
+
+int main(void)
+{
+ return 0;
+}
from patman import terminal
from patman.terminal import Print
+# This indicates an new int or hex Kconfig property with no default
+# It hangs the build since the 'conf' tool cannot proceed without valid input.
+#
+# We get a repeat sequence of something like this:
+# >>
+# Break things (BREAK_ME) [] (NEW)
+# Error in reading or end of file.
+# <<
+# which indicates that BREAK_ME has an empty default
+RE_NO_DEFAULT = re.compile(b'\((\w+)\) \[] \(NEW\)')
+
"""
Theory of Operation
_working_dir: Base working directory containing all threads
_single_builder: BuilderThread object for the singer builder, if
threading is not being used
+ _terminated: Thread was terminated due to an error
+ _restarting_config: True if 'Restart config' is detected in output
"""
class Outcome:
"""Records a build outcome for a single make invocation
self.work_in_output = work_in_output
if not self.squash_config_y:
self.config_filenames += EXTRA_CONFIG_FILENAMES
+ self._terminated = False
+ self._restarting_config = False
self.warnings_as_errors = warnings_as_errors
self.col = terminal.Color()
args: Arguments to pass to make
kwargs: Arguments to pass to command.RunPipe()
"""
+
+ def check_output(stream, data):
+ if b'Restart config' in data:
+ self._restarting_config = True
+
+ # If we see 'Restart config' following by multiple errors
+ if self._restarting_config:
+ m = RE_NO_DEFAULT.findall(data)
+
+ # Number of occurences of each Kconfig item
+ multiple = [m.count(val) for val in set(m)]
+
+ # If any of them occur more than once, we have a loop
+ if [val for val in multiple if val > 1]:
+ self._terminated = True
+ return True
+ return False
+
+ self._restarting_config = False
+ self._terminated = False
cmd = [self.gnu_make] + list(args)
result = command.RunPipe([cmd], capture=True, capture_stderr=True,
- cwd=cwd, raise_on_error=False, infile='/dev/null', **kwargs)
+ cwd=cwd, raise_on_error=False, infile='/dev/null',
+ output_func=check_output, **kwargs)
+
+ if self._terminated:
+ # Try to be helpful
+ result.stderr += '(** did you define an int/hex Kconfig with no default? **)'
+
if self.verbose_build:
result.stdout = '%s\n' % (' '.join(cmd)) + result.stdout
result.combined = '%s\n' % (' '.join(cmd)) + result.combined
work_in_output: Use the output directory as the work directory and
don't write to a separate output directory.
"""
- # Fatal error
- if result.return_code < 0:
- return
-
# If we think this might have been aborted with Ctrl-C, record the
# failure but not that we are 'done' with this board. A retry may fix
# it.
- maybe_aborted = result.stderr and 'No child processes' in result.stderr
+ maybe_aborted = result.stderr and 'No child processes' in result.stderr
- if result.already_done:
+ if result.return_code >= 0 and result.already_done:
return
# Write the output and stderr
elif os.path.exists(errfile):
os.remove(errfile)
+ # Fatal error
+ if result.return_code < 0:
+ return
+
if result.toolchain:
# Write the build result and toolchain information.
done_file = self.builder.GetDoneFile(result.commit_upto,
if arch == 'aarch64':
arch = 'arm64'
base = 'https://www.kernel.org/pub/tools/crosstool/files/bin'
- versions = ['9.2.0', '7.3.0', '6.4.0', '4.9.4']
+ versions = ['11.1.0', '9.2.0', '7.3.0', '6.4.0', '4.9.4']
links = []
for version in versions:
url = '%s/%s/%s/' % (base, arch, version)
# This Dockerfile is used to build an image containing basic stuff to be used
# to build U-Boot and run our test suites.
-FROM ubuntu:focal-20210921
+FROM ubuntu:focal-20211006
MAINTAINER Tom Rini <trini@konsulko.com>
LABEL Description=" This image is for building U-Boot inside a container"
dosfstools \
e2fsprogs \
efitools \
+ expect \
fakeroot \
flex \
+ gawk \
gdisk \
git \
gnu-efi \
+ gnutls-dev \
graphviz \
grub-efi-amd64-bin \
grub-efi-ia32-bin \
iputils-ping \
libconfuse-dev \
libgit2-dev \
+ libjson-glib-dev \
libguestfs-tools \
liblz4-tool \
libpixman-1-dev \
libpython3-dev \
libsdl1.2-dev \
libsdl2-dev \
+ libseccomp-dev \
libssl-dev \
+ libtool \
libudev-dev \
libusb-1.0-0-dev \
linux-image-kvm \
mount \
mtd-utils \
mtools \
+ net-tools \
ninja-build \
openssl \
picocom \
rpm2cpio \
sbsigntool \
sloccount \
+ socat \
+ softhsm2 \
sparse \
srecord \
sudo \
make install && \
rm -rf /tmp/genimage-14
+# Build libtpms
+RUN git clone https://github.com/stefanberger/libtpms /tmp/libtpms && \
+ cd /tmp/libtpms && \
+ ./autogen.sh && \
+ ./configure && \
+ make -j$(nproc) && \
+ make install && \
+ ldconfig && \
+ rm -rf /tmp/libtpms
+
+# Build swtpm
+RUN git clone https://github.com/stefanberger/swtpm /tmp/swtpm && \
+ cd /tmp/swtpm && \
+ ./autogen.sh && \
+ ./configure && \
+ make -j$(nproc) && \
+ make install && \
+ rm -rf /tmp/swtpm
+
# Create our user/group
RUN echo uboot ALL=NOPASSWD: ALL > /etc/sudoers.d/uboot
RUN useradd -m -U uboot
cat spl/u-boot-spl-pad.bin ddr4_1d_fw.bin ddr4_2d_fw.bin > spl/u-boot-spl-ddr.bin
rm -f ddr4_1d_fw.bin ddr4_2d_fw.bin ddr4_imem_1d_pad.bin ddr4_dmem_1d_pad.bin ddr4_imem_2d_pad.bin spl/u-boot-spl-pad.bin
fi
+ if [ -f ddr3_imem_1d.bin ]; then
+ objcopy -I binary -O binary --pad-to 0x8000 --gap-fill=0x0 ddr3_imem_1d.bin ddr3_imem_1d_pad.bin
+ cat ddr3_imem_1d_pad.bin ddr3_dmem_1d.bin > ddr3_1d_fw.bin
+ dd if=spl/u-boot-spl.bin of=spl/u-boot-spl-pad.bin bs=4 conv=sync
+ cat spl/u-boot-spl-pad.bin ddr3_1d_fw.bin > spl/u-boot-spl-ddr.bin
+ rm -f ddr3_1d_fw.bin ddr3_imem_1d_pad.bin spl/u-boot-spl-pad.bin
+ fi
fi
exit 0
if (ptr == MAP_FAILED) {
fprintf(stderr, "Can't read %s: %s\n",
datafile, strerror(errno));
- exit(EXIT_FAILURE);
+ goto err_mmap;
}
size = sbuf.st_size - datafile_offset;
}
munmap((void *)ptr, sbuf.st_size);
+err_mmap:
close(dfd);
}
IMAGE_CFG_DATA,
IMAGE_CFG_DATA_DELAY,
IMAGE_CFG_BAUDRATE,
+ IMAGE_CFG_UART_PORT,
+ IMAGE_CFG_UART_MPP,
IMAGE_CFG_DEBUG,
IMAGE_CFG_KAK,
IMAGE_CFG_CSK,
[IMAGE_CFG_DATA] = "DATA",
[IMAGE_CFG_DATA_DELAY] = "DATA_DELAY",
[IMAGE_CFG_BAUDRATE] = "BAUDRATE",
+ [IMAGE_CFG_UART_PORT] = "UART_PORT",
+ [IMAGE_CFG_UART_MPP] = "UART_MPP",
[IMAGE_CFG_DEBUG] = "DEBUG",
[IMAGE_CFG_KAK] = "KAK",
[IMAGE_CFG_CSK] = "CSK",
struct ext_hdr_v0_reg regdata;
unsigned int regdata_delay;
unsigned int baudrate;
+ unsigned int uart_port;
+ unsigned int uart_mpp;
unsigned int debug;
const char *key_name;
int csk_idx;
return e->sec_specialized_img;
}
+static int image_get_bootfrom(void)
+{
+ struct image_cfg_element *e;
+
+ e = image_find_option(IMAGE_CFG_BOOT_FROM);
+ if (!e)
+ /* fallback to SPI if no BOOT_FROM is not provided */
+ return IBR_HDR_SPI_ID;
+
+ return e->bootfrom;
+}
+
/*
* Compute a 8-bit checksum of a memory area. This algorithm follows
* the requirements of the Marvell SoC BootROM specifications.
return ret;
}
+static size_t image_headersz_align(size_t headersz, uint8_t blockid)
+{
+ /*
+ * Header needs to be 4-byte aligned, which is already ensured by code
+ * above. Moreover UART images must have header aligned to 128 bytes
+ * (xmodem block size), NAND images to 256 bytes (ECC calculation),
+ * and SATA and SDIO images to 512 bytes (storage block size).
+ * Note that SPI images do not have to have header size aligned
+ * to 256 bytes because it is possible to read from SPI storage from
+ * any offset (read offset does not have to be aligned to block size).
+ */
+ if (blockid == IBR_HDR_UART_ID)
+ return ALIGN(headersz, 128);
+ else if (blockid == IBR_HDR_NAND_ID)
+ return ALIGN(headersz, 256);
+ else if (blockid == IBR_HDR_SATA_ID || blockid == IBR_HDR_SDIO_ID)
+ return ALIGN(headersz, 512);
+ else
+ return headersz;
+}
+
+static size_t image_headersz_v0(int *hasext)
+{
+ size_t headersz;
+
+ headersz = sizeof(struct main_hdr_v0);
+ if (image_count_options(IMAGE_CFG_DATA) > 0) {
+ headersz += sizeof(struct ext_hdr_v0);
+ if (hasext)
+ *hasext = 1;
+ }
+
+ return image_headersz_align(headersz, image_get_bootfrom());
+}
+
static void *image_create_v0(size_t *imagesz, struct image_tool_params *params,
int payloadsz)
{
* Calculate the size of the header and the size of the
* payload
*/
- headersz = sizeof(struct main_hdr_v0);
-
- if (image_count_options(IMAGE_CFG_DATA) > 0) {
- has_ext = 1;
- headersz += sizeof(struct ext_hdr_v0);
- }
+ headersz = image_headersz_v0(&has_ext);
image = malloc(headersz);
if (!image) {
/* Fill in the main header */
main_hdr->blocksize =
- cpu_to_le32(payloadsz - headersz);
+ cpu_to_le32(payloadsz);
main_hdr->srcaddr = cpu_to_le32(headersz);
main_hdr->ext = has_ext;
+ main_hdr->version = 0;
main_hdr->destaddr = cpu_to_le32(params->addr);
main_hdr->execaddr = cpu_to_le32(params->ep);
+ main_hdr->blockid = image_get_bootfrom();
- e = image_find_option(IMAGE_CFG_BOOT_FROM);
- if (e)
- main_hdr->blockid = e->bootfrom;
e = image_find_option(IMAGE_CFG_NAND_ECC_MODE);
if (e)
main_hdr->nandeccmode = e->nandeccmode;
main_hdr->checksum = image_checksum8(image,
sizeof(struct main_hdr_v0));
+ /*
+ * For SATA srcaddr is specified in number of sectors starting from
+ * sector 0. The main header is stored at sector number 1.
+ * This expects the sector size to be 512 bytes.
+ * Header size is already aligned.
+ */
+ if (main_hdr->blockid == IBR_HDR_SATA_ID)
+ main_hdr->srcaddr = cpu_to_le32(headersz / 512 + 1);
+
+ /*
+ * For SDIO srcaddr is specified in number of sectors starting from
+ * sector 0. The main header is stored at sector number 0.
+ * This expects sector size to be 512 bytes.
+ * Header size is already aligned.
+ */
+ if (main_hdr->blockid == IBR_HDR_SDIO_ID)
+ main_hdr->srcaddr = cpu_to_le32(headersz / 512);
+
+ /* For PCIe srcaddr is not used and must be set to 0xFFFFFFFF. */
+ if (main_hdr->blockid == IBR_HDR_PEX_ID)
+ main_hdr->srcaddr = cpu_to_le32(0xFFFFFFFF);
+
/* Generate the ext header */
if (has_ext) {
struct ext_hdr_v0 *ext_hdr;
*/
headersz = sizeof(struct main_hdr_v1);
+ if (image_get_csk_index() >= 0) {
+ headersz += sizeof(struct secure_hdr_v1);
+ if (hasext)
+ *hasext = 1;
+ }
+
count = image_count_options(IMAGE_CFG_DATA);
if (count > 0)
headersz += sizeof(struct register_set_hdr_v1) + 8 * count + 4;
return 0;
}
- headersz += sizeof(struct opt_hdr_v1) +
- ALIGN(s.st_size, 4) +
- (binarye->binary.nargs + 2) * sizeof(uint32_t);
- if (hasext)
- *hasext = 1;
- }
-
- if (image_get_csk_index() >= 0) {
- headersz += sizeof(struct secure_hdr_v1);
+ headersz += sizeof(struct opt_hdr_v1) + sizeof(uint32_t) +
+ (binarye->binary.nargs) * sizeof(uint32_t);
+ headersz = ALIGN(headersz, 16);
+ headersz += ALIGN(s.st_size, 4) + sizeof(uint32_t);
if (hasext)
*hasext = 1;
}
- /*
- * The payload should be aligned on some reasonable
- * boundary
- */
- return ALIGN(headersz, 4096);
+ return image_headersz_align(headersz, image_get_bootfrom());
}
int add_binary_header_v1(uint8_t **cur, uint8_t **next_ext,
- struct image_cfg_element *binarye)
+ struct image_cfg_element *binarye,
+ struct main_hdr_v1 *main_hdr)
{
struct opt_hdr_v1 *hdr = (struct opt_hdr_v1 *)*cur;
+ uint32_t add_args;
+ uint32_t offset;
uint32_t *args;
size_t binhdrsz;
struct stat s;
goto err_close;
}
- binhdrsz = sizeof(struct opt_hdr_v1) +
- (binarye->binary.nargs + 2) * sizeof(uint32_t) +
- ALIGN(s.st_size, 4);
- hdr->headersz_lsb = cpu_to_le16(binhdrsz & 0xFFFF);
- hdr->headersz_msb = (binhdrsz & 0xFFFF0000) >> 16;
-
*cur += sizeof(struct opt_hdr_v1);
args = (uint32_t *)*cur;
*cur += (binarye->binary.nargs + 1) * sizeof(uint32_t);
+ /*
+ * ARM executable code inside the BIN header on some mvebu platforms
+ * (e.g. A370, AXP) must always be aligned with the 128-bit boundary.
+ * This requirement can be met by inserting dummy arguments into
+ * BIN header, if needed.
+ */
+ offset = *cur - (uint8_t *)main_hdr;
+ add_args = ((16 - offset % 16) % 16) / sizeof(uint32_t);
+ if (add_args) {
+ *(args - 1) = cpu_to_le32(binarye->binary.nargs + add_args);
+ *cur += add_args * sizeof(uint32_t);
+ }
+
ret = fread(*cur, s.st_size, 1, bin);
if (ret != 1) {
fprintf(stderr,
*cur += sizeof(uint32_t);
+ binhdrsz = sizeof(struct opt_hdr_v1) +
+ (binarye->binary.nargs + add_args + 2) * sizeof(uint32_t) +
+ ALIGN(s.st_size, 4);
+ hdr->headersz_lsb = cpu_to_le16(binhdrsz & 0xFFFF);
+ hdr->headersz_msb = (binhdrsz & 0xFFFF0000) >> 16;
+
return 0;
err_close:
{
struct image_cfg_element *e;
struct main_hdr_v1 *main_hdr;
+ struct opt_hdr_v1 *ohdr;
struct register_set_hdr_v1 *register_set_hdr;
struct secure_hdr_v1 *secure_hdr = NULL;
size_t headersz;
/* Fill the main header */
main_hdr->blocksize =
- cpu_to_le32(payloadsz - headersz);
+ cpu_to_le32(payloadsz);
main_hdr->headersz_lsb = cpu_to_le16(headersz & 0xFFFF);
main_hdr->headersz_msb = (headersz & 0xFFFF0000) >> 16;
main_hdr->destaddr = cpu_to_le32(params->addr);
main_hdr->srcaddr = cpu_to_le32(headersz);
main_hdr->ext = hasext;
main_hdr->version = 1;
- e = image_find_option(IMAGE_CFG_BOOT_FROM);
- if (e)
- main_hdr->blockid = e->bootfrom;
+ main_hdr->blockid = image_get_bootfrom();
+
e = image_find_option(IMAGE_CFG_NAND_BLKSZ);
if (e)
main_hdr->nandblocksize = e->nandblksz / (64 * 1024);
+ e = image_find_option(IMAGE_CFG_NAND_PAGESZ);
+ if (e)
+ main_hdr->nandpagesize = cpu_to_le16(e->nandpagesz);
e = image_find_option(IMAGE_CFG_NAND_BADBLK_LOCATION);
if (e)
main_hdr->nandbadblklocation = e->nandbadblklocation;
e = image_find_option(IMAGE_CFG_BAUDRATE);
if (e)
- main_hdr->options = baudrate_to_option(e->baudrate);
+ main_hdr->options |= baudrate_to_option(e->baudrate);
+ e = image_find_option(IMAGE_CFG_UART_PORT);
+ if (e)
+ main_hdr->options |= (e->uart_port & 3) << 3;
+ e = image_find_option(IMAGE_CFG_UART_MPP);
+ if (e)
+ main_hdr->options |= (e->uart_mpp & 7) << 5;
e = image_find_option(IMAGE_CFG_DEBUG);
if (e)
main_hdr->flags = e->debug ? 0x1 : 0;
if (e->type != IMAGE_CFG_BINARY)
continue;
- if (add_binary_header_v1(&cur, &next_ext, e))
+ if (add_binary_header_v1(&cur, &next_ext, e, main_hdr))
return NULL;
}
- if (secure_hdr && add_secure_header_v1(params, ptr, payloadsz,
+ if (secure_hdr && add_secure_header_v1(params, ptr, payloadsz + headersz,
headersz, image, secure_hdr))
return NULL;
main_hdr->checksum = image_checksum8(main_hdr, headersz);
*imagesz = headersz;
+
+ /* Fill the real header size without padding into the main header */
+ headersz = sizeof(*main_hdr);
+ for_each_opt_hdr_v1 (ohdr, main_hdr)
+ headersz += opt_hdr_v1_size(ohdr);
+ main_hdr->headersz_lsb = cpu_to_le16(headersz & 0xFFFF);
+ main_hdr->headersz_msb = (headersz & 0xFFFF0000) >> 16;
+
return image;
}
case IMAGE_CFG_BAUDRATE:
el->baudrate = strtoul(value1, NULL, 10);
break;
+ case IMAGE_CFG_UART_PORT:
+ el->uart_port = strtoul(value1, NULL, 16);
+ break;
+ case IMAGE_CFG_UART_MPP:
+ el->uart_mpp = strtoul(value1, NULL, 16);
+ break;
case IMAGE_CFG_DEBUG:
el->debug = strtoul(value1, NULL, 10);
break;
return e->version;
}
-static int image_get_bootfrom(void)
-{
- struct image_cfg_element *e;
-
- e = image_find_option(IMAGE_CFG_BOOT_FROM);
- if (!e)
- return -1;
-
- return e->bootfrom;
-}
-
static void kwbimage_set_header(void *ptr, struct stat *sbuf, int ifd,
struct image_tool_params *params)
{
void *image = NULL;
int version;
size_t headersz = 0;
+ size_t datasz;
uint32_t checksum;
+ struct stat s;
int ret;
+ /*
+ * Do not use sbuf->st_size as it contains size with padding.
+ * We need original image data size, so stat original file.
+ */
+ if (stat(params->datafile, &s)) {
+ fprintf(stderr, "Could not stat data file %s: %s\n",
+ params->datafile, strerror(errno));
+ exit(EXIT_FAILURE);
+ }
+ datasz = ALIGN(s.st_size, 4);
+
fcfg = fopen(params->imagename, "r");
if (!fcfg) {
fprintf(stderr, "Could not open input file %s\n",
*/
case -1:
case 0:
- image = image_create_v0(&headersz, params, sbuf->st_size);
+ image = image_create_v0(&headersz, params, datasz + 4);
break;
case 1:
- image = image_create_v1(&headersz, params, ptr, sbuf->st_size);
+ image = image_create_v1(&headersz, params, ptr, datasz + 4);
break;
default:
free(image_cfg);
- /* Build and add image checksum header */
+ /* Build and add image data checksum */
checksum = cpu_to_le32(image_checksum32((uint8_t *)ptr + headersz,
- sbuf->st_size - headersz - sizeof(uint32_t)));
- memcpy((uint8_t *)ptr + sbuf->st_size - sizeof(uint32_t), &checksum,
- sizeof(uint32_t));
+ datasz));
+ memcpy((uint8_t *)ptr + headersz + datasz, &checksum, sizeof(uint32_t));
/* Finally copy the header into the image area */
memcpy(ptr, image, headersz);
struct image_tool_params *params)
{
size_t header_size = kwbheader_size(ptr);
+ uint8_t blockid;
+ uint32_t offset;
+ uint32_t size;
uint8_t csum;
if (header_size > image_size)
if (csum != ext_hdr->checksum)
return -FDT_ERR_BADSTRUCTURE;
}
+
+ blockid = mhdr->blockid;
+ offset = le32_to_cpu(mhdr->srcaddr);
+ size = le32_to_cpu(mhdr->blocksize);
} else if (kwbimage_version(ptr) == 1) {
struct main_hdr_v1 *mhdr = (struct main_hdr_v1 *)ptr;
const uint8_t *mhdr_end;
struct opt_hdr_v1 *ohdr;
- uint32_t offset;
- uint32_t size;
mhdr_end = (uint8_t *)mhdr + header_size;
for_each_opt_hdr_v1 (ohdr, ptr)
if (!opt_hdr_v1_valid_size(ohdr, mhdr_end))
return -FDT_ERR_BADSTRUCTURE;
+ blockid = mhdr->blockid;
offset = le32_to_cpu(mhdr->srcaddr);
+ size = le32_to_cpu(mhdr->blocksize);
+ } else {
+ return -FDT_ERR_BADSTRUCTURE;
+ }
- /*
- * For SATA srcaddr is specified in number of sectors.
- * The main header is must be stored at sector number 1.
- * This expects that sector size is 512 bytes and recalculates
- * data offset to bytes relative to the main header.
- */
- if (mhdr->blockid == IBR_HDR_SATA_ID) {
- if (offset < 1)
- return -FDT_ERR_BADSTRUCTURE;
- offset -= 1;
- offset *= 512;
- }
+ /*
+ * For SATA srcaddr is specified in number of sectors.
+ * The main header is must be stored at sector number 1.
+ * This expects that sector size is 512 bytes and recalculates
+ * data offset to bytes relative to the main header.
+ */
+ if (blockid == IBR_HDR_SATA_ID) {
+ if (offset < 1)
+ return -FDT_ERR_BADSTRUCTURE;
+ offset -= 1;
+ offset *= 512;
+ }
- /*
- * For SDIO srcaddr is specified in number of sectors.
- * This expects that sector size is 512 bytes and recalculates
- * data offset to bytes.
- */
- if (mhdr->blockid == IBR_HDR_SDIO_ID)
- offset *= 512;
+ /*
+ * For SDIO srcaddr is specified in number of sectors.
+ * This expects that sector size is 512 bytes and recalculates
+ * data offset to bytes.
+ */
+ if (blockid == IBR_HDR_SDIO_ID)
+ offset *= 512;
- /*
- * For PCIe srcaddr is always set to 0xFFFFFFFF.
- * This expects that data starts after all headers.
- */
- if (mhdr->blockid == IBR_HDR_PEX_ID && offset == 0xFFFFFFFF)
- offset = header_size;
+ /*
+ * For PCIe srcaddr is always set to 0xFFFFFFFF.
+ * This expects that data starts after all headers.
+ */
+ if (blockid == IBR_HDR_PEX_ID && offset == 0xFFFFFFFF)
+ offset = header_size;
- if (offset > image_size || offset % 4 != 0)
- return -FDT_ERR_BADSTRUCTURE;
+ if (offset > image_size || offset % 4 != 0)
+ return -FDT_ERR_BADSTRUCTURE;
- size = le32_to_cpu(mhdr->blocksize);
- if (size < 4 || offset + size > image_size || size % 4 != 0)
- return -FDT_ERR_BADSTRUCTURE;
+ if (size < 4 || offset + size > image_size || size % 4 != 0)
+ return -FDT_ERR_BADSTRUCTURE;
- if (image_checksum32(ptr + offset, size - 4) !=
- *(uint32_t *)(ptr + offset + size - 4))
- return -FDT_ERR_BADSTRUCTURE;
- } else {
+ if (image_checksum32(ptr + offset, size - 4) !=
+ *(uint32_t *)(ptr + offset + size - 4))
return -FDT_ERR_BADSTRUCTURE;
- }
return 0;
}
*/
case -1:
case 0:
- alloc_len = sizeof(struct main_hdr_v0) +
- sizeof(struct ext_hdr_v0);
+ alloc_len = image_headersz_v0(NULL);
break;
case 1:
* The resulting image needs to be 4-byte aligned. At least
* the Marvell hdrparser tool complains if its unaligned.
* After the image data is stored 4-byte checksum.
+ * Final UART image must be aligned to 128 bytes.
* Final SPI and NAND images must be aligned to 256 bytes.
* Final SATA and SDIO images must be aligned to 512 bytes.
*/
return 4 + (256 - (alloc_len + s.st_size + 4) % 256) % 256;
else if (bootfrom == IBR_HDR_SATA_ID || bootfrom == IBR_HDR_SDIO_ID)
return 4 + (512 - (alloc_len + s.st_size + 4) % 512) % 512;
+ else if (bootfrom == IBR_HDR_UART_ID)
+ return 4 + (128 - (alloc_len + s.st_size + 4) % 128) % 128;
else
return 4 + (4 - s.st_size % 4) % 4;
}
char *msg = "Configuration file for kwbimage creation omitted";
fprintf(stderr, "Error:%s - %s\n", params->cmdname, msg);
- return CFG_INVALID;
+ return 1;
}
return (params->dflag && (params->fflag || params->lflag)) ||
uint8_t nandeccmode; /* 0x1 */
uint16_t nandpagesize; /* 0x2-0x3 */
uint32_t blocksize; /* 0x4-0x7 */
- uint32_t rsvd1; /* 0x8-0xB */
+ uint8_t version; /* 0x8 */
+ uint8_t rsvd1[3]; /* 0x9-0xB */
uint32_t srcaddr; /* 0xC-0xF */
uint32_t destaddr; /* 0x10-0x13 */
uint32_t execaddr; /* 0x14-0x17 */
struct main_hdr_v1 {
uint8_t blockid; /* 0x0 */
uint8_t flags; /* 0x1 */
- uint16_t reserved2; /* 0x2-0x3 */
+ uint16_t nandpagesize; /* 0x2-0x3 */
uint32_t blocksize; /* 0x4-0x7 */
uint8_t version; /* 0x8 */
uint8_t headersz_msb; /* 0x9 */
#define OPT_HDR_V1_BINARY_TYPE 0x2
#define OPT_HDR_V1_REGISTER_TYPE 0x3
-enum kwbimage_cmd {
- CMD_INVALID,
- CMD_BOOT_FROM,
- CMD_NAND_ECC_MODE,
- CMD_NAND_PAGE_SIZE,
- CMD_SATA_PIO_MODE,
- CMD_DDR_INIT_DELAY,
- CMD_DATA
-};
-
-enum kwbimage_cmd_types {
- CFG_INVALID = -1,
- CFG_COMMAND,
- CFG_DATA0,
- CFG_DATA1
-};
-
-/*
- * functions
- */
-void init_kwb_image_type (void);
-
/*
* Byte 8 of the image header contains the version number. In the v0
* header, byte 8 was reserved, and always set to 0. In the v1 header,
#define KWBOOT_BLK_RSP_TIMEO 1000 /* ms */
#define KWBOOT_HDR_RSP_TIMEO 10000 /* ms */
-/* ARM code making baudrate changing function return to original exec address */
-static unsigned char kwboot_pre_baud_code[] = {
- /* exec_addr: */
- 0x00, 0x00, 0x00, 0x00, /* .word 0 */
- 0x0c, 0xe0, 0x1f, 0xe5, /* ldr lr, exec_addr */
-};
-
-/* ARM code for binary header injection to change baudrate */
+/* ARM code to change baudrate */
static unsigned char kwboot_baud_code[] = {
/* ; #define UART_BASE 0xd0012000 */
- /* ; #define THR 0x00 */
/* ; #define DLL 0x00 */
/* ; #define DLH 0x04 */
/* ; #define LCR 0x0c */
/* ; #define DLAB 0x80 */
/* ; #define LSR 0x14 */
- /* ; #define THRE 0x20 */
/* ; #define TEMT 0x40 */
/* ; #define DIV_ROUND(a, b) ((a + b/2) / b) */
/* ; */
/* ; u32 set_baudrate(u32 old_b, u32 new_b) { */
- /* ; const u8 *str = "$baudratechange"; */
- /* ; u8 c; */
- /* ; do { */
- /* ; c = *str++; */
- /* ; writel(UART_BASE + THR, c); */
- /* ; } while (c); */
/* ; while */
/* ; (!(readl(UART_BASE + LSR) & TEMT)); */
/* ; u32 lcr = readl(UART_BASE + LCR); */
/* ; writel(UART_BASE + DLL, new_dll); */
/* ; writel(UART_BASE + DLH, new_dlh); */
/* ; writel(UART_BASE + LCR, lcr & ~DLAB); */
- /* ; msleep(1); */
+ /* ; msleep(5); */
/* ; return 0; */
/* ; } */
- 0xfe, 0x5f, 0x2d, 0xe9, /* push { r1 - r12, lr } */
-
/* ; r0 = UART_BASE */
- 0x02, 0x0a, 0xa0, 0xe3, /* mov r0, #0x2000 */
- 0x01, 0x00, 0x4d, 0xe3, /* movt r0, #0xd001 */
-
- /* ; r2 = address of preamble string */
- 0xd0, 0x20, 0x8f, 0xe2, /* adr r2, preamble */
-
- /* ; Send preamble string over UART */
- /* .Lloop_preamble: */
- /* */
- /* ; Wait until Transmitter Holding is Empty */
- /* .Lloop_thre: */
- /* ; r1 = UART_BASE[LSR] & THRE */
- 0x14, 0x10, 0x90, 0xe5, /* ldr r1, [r0, #0x14] */
- 0x20, 0x00, 0x11, 0xe3, /* tst r1, #0x20 */
- 0xfc, 0xff, 0xff, 0x0a, /* beq .Lloop_thre */
-
- /* ; Put character into Transmitter FIFO */
- /* ; r1 = *r2++ */
- 0x01, 0x10, 0xd2, 0xe4, /* ldrb r1, [r2], #1 */
- /* ; UART_BASE[THR] = r1 */
- 0x00, 0x10, 0x80, 0xe5, /* str r1, [r0, #0x0] */
-
- /* ; Loop until end of preamble string */
- 0x00, 0x00, 0x51, 0xe3, /* cmp r1, #0 */
- 0xf8, 0xff, 0xff, 0x1a, /* bne .Lloop_preamble */
+ 0x0d, 0x02, 0xa0, 0xe3, /* mov r0, #0xd0000000 */
+ 0x12, 0x0a, 0x80, 0xe3, /* orr r0, r0, #0x12000 */
/* ; Wait until Transmitter FIFO is Empty */
/* .Lloop_txempty: */
/* ; Read old baudrate value */
/* ; r2 = old_baudrate */
- 0x8c, 0x20, 0x9f, 0xe5, /* ldr r2, old_baudrate */
+ 0x74, 0x20, 0x9f, 0xe5, /* ldr r2, old_baudrate */
/* ; Calculate base clock */
/* ; r1 = r2 * r1 */
0x92, 0x01, 0x01, 0xe0, /* mul r1, r2, r1 */
/* ; Read new baudrate value */
- /* ; r2 = baudrate */
- 0x88, 0x20, 0x9f, 0xe5, /* ldr r2, baudrate */
+ /* ; r2 = new_baudrate */
+ 0x70, 0x20, 0x9f, 0xe5, /* ldr r2, new_baudrate */
/* ; Calculate new Divisor Latch */
/* ; r1 = DIV_ROUND(r1, r2) = */
0x80, 0x10, 0xc1, 0xe3, /* bic r1, r1, #0x80 */
0x0c, 0x10, 0x80, 0xe5, /* str r1, [r0, #0x0c] */
- /* ; Sleep 1ms ~~ 600000 cycles at 1200 MHz */
- /* ; r1 = 600000 */
- 0x9f, 0x1d, 0xa0, 0xe3, /* mov r1, #0x27c0 */
- 0x09, 0x10, 0x40, 0xe3, /* movt r1, #0x0009 */
+ /* ; Loop 0x2dc000 (2998272) cycles */
+ /* ; which is about 5ms on 1200 MHz CPU */
+ /* ; r1 = 0x2dc000 */
+ 0xb7, 0x19, 0xa0, 0xe3, /* mov r1, #0x2dc000 */
/* .Lloop_sleep: */
0x01, 0x10, 0x41, 0xe2, /* sub r1, r1, #1 */
0x00, 0x00, 0x51, 0xe3, /* cmp r1, #0 */
0xfc, 0xff, 0xff, 0x1a, /* bne .Lloop_sleep */
- /* ; Return 0 - no error */
- 0x00, 0x00, 0xa0, 0xe3, /* mov r0, #0 */
- 0xfe, 0x9f, 0xbd, 0xe8, /* pop { r1 - r12, pc } */
-
- /* ; Preamble string */
- /* preamble: */
- 0x24, 0x62, 0x61, 0x75, /* .asciz "$baudratechange" */
- 0x64, 0x72, 0x61, 0x74,
- 0x65, 0x63, 0x68, 0x61,
- 0x6e, 0x67, 0x65, 0x00,
+ /* ; Jump to the end of execution */
+ 0x01, 0x00, 0x00, 0xea, /* b end */
/* ; Placeholder for old baudrate value */
/* old_baudrate: */
/* ; Placeholder for new baudrate value */
/* new_baudrate: */
0x00, 0x00, 0x00, 0x00, /* .word 0 */
+
+ /* end: */
};
-#define KWBOOT_BAUDRATE_BIN_HEADER_SZ (sizeof(kwboot_baud_code) + \
- sizeof(struct opt_hdr_v1) + 8)
+/* ARM code from binary header executed by BootROM before changing baudrate */
+static unsigned char kwboot_baud_code_binhdr_pre[] = {
+ /* ; #define UART_BASE 0xd0012000 */
+ /* ; #define THR 0x00 */
+ /* ; #define LSR 0x14 */
+ /* ; #define THRE 0x20 */
+ /* ; */
+ /* ; void send_preamble(void) { */
+ /* ; const u8 *str = "$baudratechange"; */
+ /* ; u8 c; */
+ /* ; do { */
+ /* ; while */
+ /* ; ((readl(UART_BASE + LSR) & THRE)); */
+ /* ; c = *str++; */
+ /* ; writel(UART_BASE + THR, c); */
+ /* ; } while (c); */
+ /* ; } */
+
+ /* ; Preserve registers for BootROM */
+ 0xfe, 0x5f, 0x2d, 0xe9, /* push { r1 - r12, lr } */
+
+ /* ; r0 = UART_BASE */
+ 0x0d, 0x02, 0xa0, 0xe3, /* mov r0, #0xd0000000 */
+ 0x12, 0x0a, 0x80, 0xe3, /* orr r0, r0, #0x12000 */
+
+ /* ; r2 = address of preamble string */
+ 0x00, 0x20, 0x8f, 0xe2, /* adr r2, .Lstr_preamble */
+
+ /* ; Skip preamble data section */
+ 0x03, 0x00, 0x00, 0xea, /* b .Lloop_preamble */
+
+ /* ; Preamble string */
+ /* .Lstr_preamble: */
+ 0x24, 0x62, 0x61, 0x75, /* .asciz "$baudratechange" */
+ 0x64, 0x72, 0x61, 0x74,
+ 0x65, 0x63, 0x68, 0x61,
+ 0x6e, 0x67, 0x65, 0x00,
+
+ /* ; Send preamble string over UART */
+ /* .Lloop_preamble: */
+ /* */
+ /* ; Wait until Transmitter Holding is Empty */
+ /* .Lloop_thre: */
+ /* ; r1 = UART_BASE[LSR] & THRE */
+ 0x14, 0x10, 0x90, 0xe5, /* ldr r1, [r0, #0x14] */
+ 0x20, 0x00, 0x11, 0xe3, /* tst r1, #0x20 */
+ 0xfc, 0xff, 0xff, 0x0a, /* beq .Lloop_thre */
+
+ /* ; Put character into Transmitter FIFO */
+ /* ; r1 = *r2++ */
+ 0x01, 0x10, 0xd2, 0xe4, /* ldrb r1, [r2], #1 */
+ /* ; UART_BASE[THR] = r1 */
+ 0x00, 0x10, 0x80, 0xe5, /* str r1, [r0, #0x0] */
+
+ /* ; Loop until end of preamble string */
+ 0x00, 0x00, 0x51, 0xe3, /* cmp r1, #0 */
+ 0xf8, 0xff, 0xff, 0x1a, /* bne .Lloop_preamble */
+};
+
+/* ARM code for returning from binary header back to BootROM */
+static unsigned char kwboot_baud_code_binhdr_post[] = {
+ /* ; Return 0 - no error */
+ 0x00, 0x00, 0xa0, 0xe3, /* mov r0, #0 */
+ 0xfe, 0x9f, 0xbd, 0xe8, /* pop { r1 - r12, pc } */
+};
+
+/* ARM code for jumping to the original image exec_addr */
+static unsigned char kwboot_baud_code_data_jump[] = {
+ 0x04, 0xf0, 0x1f, 0xe5, /* ldr pc, exec_addr */
+ /* ; Placeholder for exec_addr */
+ /* exec_addr: */
+ 0x00, 0x00, 0x00, 0x00, /* .word 0 */
+};
static const char kwb_baud_magic[16] = "$baudratechange";
}
static int
-kwboot_tty_send(int fd, const void *buf, size_t len)
+kwboot_tty_send(int fd, const void *buf, size_t len, int nodrain)
{
if (!buf)
return 0;
if (kwboot_write(fd, buf, len) < 0)
return -1;
+ if (nodrain)
+ return 0;
+
return tcdrain(fd);
}
static int
kwboot_tty_send_char(int fd, unsigned char c)
{
- return kwboot_tty_send(fd, &c, 1);
+ return kwboot_tty_send(fd, &c, 1, 0);
}
static speed_t
cfmakeraw(&tio);
tio.c_cflag |= CREAD | CLOCAL;
+ tio.c_cflag &= ~(CSTOPB | HUPCL | CRTSCTS);
tio.c_cc[VMIN] = 1;
tio.c_cc[VTIME] = 0;
break;
for (count = 0; count < 128; count++) {
- rc = kwboot_tty_send(tty, msg, 8);
+ rc = kwboot_tty_send(tty, msg, 8, 0);
if (rc) {
usleep(msg_req_delay * 1000);
continue;
if (rc)
break;
- rc = kwboot_tty_send(tty, msg, 8);
+ rc = kwboot_tty_send(tty, msg, 8, 0);
if (rc) {
usleep(msg_req_delay * 1000);
continue;
}
static int
-kwboot_xm_recv_reply(int fd, char *c, int allow_non_xm, int *non_xm_print,
+kwboot_xm_recv_reply(int fd, char *c, int nak_on_non_xm,
+ int allow_non_xm, int *non_xm_print,
int baudrate, int *baud_changed)
{
int timeout = allow_non_xm ? KWBOOT_HDR_RSP_TIMEO : blk_rsp_timeo;
uint64_t recv_until = _now() + timeout;
int rc;
- if (non_xm_print)
- *non_xm_print = 0;
- if (baud_changed)
- *baud_changed = 0;
-
while (1) {
rc = kwboot_tty_recv(fd, c, 1, timeout);
if (rc) {
*non_xm_print = 1;
}
} else {
+ if (nak_on_non_xm) {
+ *c = NAK;
+ break;
+ }
timeout = recv_until - _now();
if (timeout < 0) {
errno = ETIMEDOUT;
char c;
*done_print = 0;
+ non_xm_print = 0;
+ baud_changed = 0;
- retries = 16;
+ retries = 0;
do {
- rc = kwboot_tty_send(fd, block, sizeof(*block));
+ rc = kwboot_tty_send(fd, block, sizeof(*block), 1);
if (rc)
return rc;
*done_print = 1;
}
- rc = kwboot_xm_recv_reply(fd, &c, allow_non_xm, &non_xm_print,
+ rc = kwboot_xm_recv_reply(fd, &c, retries < 3,
+ allow_non_xm, &non_xm_print,
baudrate, &baud_changed);
if (rc)
goto can;
if (!allow_non_xm && c != ACK)
kwboot_progress(-1, '+');
- } while (c == NAK && retries-- > 0);
+ } while (c == NAK && retries++ < 16);
if (non_xm_print)
kwboot_printv("\n");
kwboot_printv("Finishing transfer\n");
- retries = 16;
+ retries = 0;
do {
rc = kwboot_tty_send_char(fd, EOT);
if (rc)
return rc;
- rc = kwboot_xm_recv_reply(fd, &c, 0, NULL, 0, NULL);
+ rc = kwboot_xm_recv_reply(fd, &c, retries < 3,
+ 0, NULL, 0, NULL);
if (rc)
return rc;
- } while (c == NAK && retries-- > 0);
+ } while (c == NAK && retries++ < 16);
return _xm_reply_to_error(c);
}
hdrsz = kwbheader_size(img);
+ /*
+ * If header size is not aligned to xmodem block size (which applies
+ * for all images in kwbimage v0 format) then we have to ensure that
+ * the last xmodem block of header contains beginning of the data
+ * followed by the header. So align header size to xmodem block size.
+ */
+ hdrsz += (KWBOOT_XM_BLKSZ - hdrsz % KWBOOT_XM_BLKSZ) % KWBOOT_XM_BLKSZ;
+
kwboot_printv("Waiting 2s and flushing tty\n");
sleep(2); /* flush isn't effective without it */
tcflush(tty, TCIOFLUSH);
if (rc)
return rc;
- img += hdrsz;
- size -= hdrsz;
-
- rc = kwboot_xmodem_one(tty, &pnum, 0, img, size, 0);
- if (rc)
- return rc;
+ /*
+ * If we have already sent image data as a part of the last
+ * xmodem header block then we have nothing more to send.
+ */
+ if (hdrsz < size) {
+ img += hdrsz;
+ size -= hdrsz;
+ rc = kwboot_xmodem_one(tty, &pnum, 0, img, size, 0);
+ if (rc)
+ return rc;
+ }
rc = kwboot_xm_finish(tty);
if (rc)
return rc;
if (baudrate) {
- char buf[sizeof(kwb_baud_magic)];
-
- /* Wait 1s for baudrate change magic */
- rc = kwboot_tty_recv(tty, buf, sizeof(buf), 1000);
- if (rc)
- return rc;
-
- if (memcmp(buf, kwb_baud_magic, sizeof(buf))) {
- errno = EPROTO;
- return -1;
- }
-
kwboot_printv("\nChanging baudrate back to 115200 Bd\n\n");
rc = kwboot_tty_change_baudrate(tty, 115200);
if (rc)
fd_set rfds;
int nfds = 0;
+ FD_ZERO(&rfds);
FD_SET(tty, &rfds);
nfds = nfds < tty ? tty : nfds;
return csum;
}
+static uint32_t *
+kwboot_img_csum32_ptr(void *img)
+{
+ struct main_hdr_v1 *hdr = img;
+ uint32_t datasz;
+
+ datasz = le32_to_cpu(hdr->blocksize) - sizeof(uint32_t);
+
+ return img + le32_to_cpu(hdr->srcaddr) + datasz;
+}
+
+static uint32_t
+kwboot_img_csum32(const void *img)
+{
+ const struct main_hdr_v1 *hdr = img;
+ uint32_t datasz, csum = 0;
+ const uint32_t *data;
+
+ datasz = le32_to_cpu(hdr->blocksize) - sizeof(csum);
+ if (datasz % sizeof(uint32_t))
+ return 0;
+
+ data = img + le32_to_cpu(hdr->srcaddr);
+ while (datasz > 0) {
+ csum += le32_to_cpu(*data++);
+ datasz -= 4;
+ }
+
+ return cpu_to_le32(csum);
+}
+
static int
kwboot_img_is_secure(void *img)
{
}
static void *
-kwboot_img_grow_data_left(void *img, size_t *size, size_t grow)
+kwboot_img_grow_data_right(void *img, size_t *size, size_t grow)
{
- uint32_t hdrsz, datasz, srcaddr;
struct main_hdr_v1 *hdr = img;
- uint8_t *data;
-
- srcaddr = le32_to_cpu(hdr->srcaddr);
-
- hdrsz = kwbheader_size(hdr);
- data = (uint8_t *)img + srcaddr;
- datasz = *size - srcaddr;
-
- /* only move data if there is not enough space */
- if (hdrsz + grow > srcaddr) {
- size_t need = hdrsz + grow - srcaddr;
-
- /* move data by enough bytes */
- memmove(data + need, data, datasz);
- *size += need;
- srcaddr += need;
- }
+ void *result;
- srcaddr -= grow;
- hdr->srcaddr = cpu_to_le32(srcaddr);
- hdr->destaddr = cpu_to_le32(le32_to_cpu(hdr->destaddr) - grow);
+ /*
+ * 32-bit checksum comes after end of image code, so we will be putting
+ * new code there. So we get this pointer and then increase data size
+ * (since increasing data size changes kwboot_img_csum32_ptr() return
+ * value).
+ */
+ result = kwboot_img_csum32_ptr(img);
hdr->blocksize = cpu_to_le32(le32_to_cpu(hdr->blocksize) + grow);
+ *size += grow;
- return (uint8_t *)img + srcaddr;
+ return result;
}
static void
{
uint32_t hdrsz, datasz, srcaddr;
struct main_hdr_v1 *hdr = img;
+ struct opt_hdr_v1 *ohdr;
uint8_t *data;
srcaddr = le32_to_cpu(hdr->srcaddr);
- hdrsz = kwbheader_size(img);
+ /* calculate real used space in kwbimage header */
+ if (kwbimage_version(img) == 0) {
+ hdrsz = kwbheader_size(img);
+ } else {
+ hdrsz = sizeof(*hdr);
+ for_each_opt_hdr_v1 (ohdr, hdr)
+ hdrsz += opt_hdr_v1_size(ohdr);
+ }
+
data = (uint8_t *)img + srcaddr;
datasz = *size - srcaddr;
if (kwbimage_version(img) == 1) {
hdrsz += grow;
- hdr->headersz_msb = hdrsz >> 16;
- hdr->headersz_lsb = cpu_to_le16(hdrsz & 0xffff);
+ if (hdrsz > kwbheader_size(img)) {
+ hdr->headersz_msb = hdrsz >> 16;
+ hdr->headersz_lsb = cpu_to_le16(hdrsz & 0xffff);
+ }
}
}
{
struct main_hdr_v1 *hdr = img;
struct opt_hdr_v1 *ohdr;
+ uint32_t num_args;
+ uint32_t offset;
uint32_t ohdrsz;
-
- ohdrsz = binsz + 8 + sizeof(*ohdr);
- kwboot_img_grow_hdr(img, size, ohdrsz);
+ uint8_t *prev_ext;
if (hdr->ext & 0x1) {
for_each_opt_hdr_v1 (ohdr, img)
if (opt_hdr_v1_next(ohdr) == NULL)
break;
- *opt_hdr_v1_ext(ohdr) |= 1;
- ohdr = opt_hdr_v1_next(ohdr);
+ prev_ext = opt_hdr_v1_ext(ohdr);
+ ohdr = _opt_hdr_v1_next(ohdr);
} else {
- hdr->ext |= 1;
ohdr = (void *)(hdr + 1);
+ prev_ext = &hdr->ext;
}
+ /*
+ * ARM executable code inside the BIN header on some mvebu platforms
+ * (e.g. A370, AXP) must always be aligned with the 128-bit boundary.
+ * This requirement can be met by inserting dummy arguments into
+ * BIN header, if needed.
+ */
+ offset = &ohdr->data[4] - (char *)img;
+ num_args = ((16 - offset % 16) % 16) / sizeof(uint32_t);
+
+ ohdrsz = sizeof(*ohdr) + 4 + 4 * num_args + binsz + 4;
+ kwboot_img_grow_hdr(hdr, size, ohdrsz);
+
+ *prev_ext |= 1;
+
ohdr->headertype = OPT_HDR_V1_BINARY_TYPE;
ohdr->headersz_msb = ohdrsz >> 16;
ohdr->headersz_lsb = cpu_to_le16(ohdrsz & 0xffff);
memset(&ohdr->data[0], 0, ohdrsz - sizeof(*ohdr));
+ *(uint32_t *)&ohdr->data[0] = cpu_to_le32(num_args);
- return &ohdr->data[4];
+ return &ohdr->data[4 + 4 * num_args];
}
static void
-_copy_baudrate_change_code(struct main_hdr_v1 *hdr, void *dst, int pre,
- int old_baud, int new_baud)
+_inject_baudrate_change_code(void *img, size_t *size, int for_data,
+ int old_baud, int new_baud)
{
- size_t codesz = sizeof(kwboot_baud_code);
- uint8_t *code = dst;
-
- if (pre) {
- size_t presz = sizeof(kwboot_pre_baud_code);
+ struct main_hdr_v1 *hdr = img;
+ uint32_t orig_datasz;
+ uint32_t codesz;
+ uint8_t *code;
- /*
- * We need to prepend code that loads lr register with original
- * value of hdr->execaddr. We do this by putting the original
- * exec address before the code that loads it relatively from
- * it's beginning.
- * Afterwards we change the exec address to this code (which is
- * at offset 4, because the first 4 bytes contain the original
- * exec address).
- */
- memcpy(code, kwboot_pre_baud_code, presz);
- *(uint32_t *)code = hdr->execaddr;
+ if (for_data) {
+ orig_datasz = le32_to_cpu(hdr->blocksize) - sizeof(uint32_t);
- hdr->execaddr = cpu_to_le32(le32_to_cpu(hdr->destaddr) + 4);
+ codesz = sizeof(kwboot_baud_code) +
+ sizeof(kwboot_baud_code_data_jump);
+ code = kwboot_img_grow_data_right(img, size, codesz);
+ } else {
+ codesz = sizeof(kwboot_baud_code_binhdr_pre) +
+ sizeof(kwboot_baud_code) +
+ sizeof(kwboot_baud_code_binhdr_post);
+ code = kwboot_add_bin_ohdr_v1(img, size, codesz);
- code += presz;
+ codesz = sizeof(kwboot_baud_code_binhdr_pre);
+ memcpy(code, kwboot_baud_code_binhdr_pre, codesz);
+ code += codesz;
}
- memcpy(code, kwboot_baud_code, codesz - 8);
- *(uint32_t *)(code + codesz - 8) = cpu_to_le32(old_baud);
- *(uint32_t *)(code + codesz - 4) = cpu_to_le32(new_baud);
+ codesz = sizeof(kwboot_baud_code) - 2 * sizeof(uint32_t);
+ memcpy(code, kwboot_baud_code, codesz);
+ code += codesz;
+ *(uint32_t *)code = cpu_to_le32(old_baud);
+ code += sizeof(uint32_t);
+ *(uint32_t *)code = cpu_to_le32(new_baud);
+ code += sizeof(uint32_t);
+
+ if (for_data) {
+ codesz = sizeof(kwboot_baud_code_data_jump) - sizeof(uint32_t);
+ memcpy(code, kwboot_baud_code_data_jump, codesz);
+ code += codesz;
+ *(uint32_t *)code = hdr->execaddr;
+ code += sizeof(uint32_t);
+ hdr->execaddr = cpu_to_le32(le32_to_cpu(hdr->destaddr) + orig_datasz);
+ } else {
+ codesz = sizeof(kwboot_baud_code_binhdr_post);
+ memcpy(code, kwboot_baud_code_binhdr_post, codesz);
+ code += codesz;
+ }
}
static int
if (csum != hdr->checksum)
goto err;
- if (image_ver == 0) {
- struct main_hdr_v0 *hdr_v0 = img;
-
- hdr_v0->nandeccmode = IBR_HDR_ECC_DISABLED;
- hdr_v0->nandpagesize = 0;
- }
-
srcaddr = le32_to_cpu(hdr->srcaddr);
switch (hdr->blockid) {
*size < le32_to_cpu(hdr->srcaddr) + le32_to_cpu(hdr->blocksize))
goto err;
+ if (kwboot_img_csum32(img) != *kwboot_img_csum32_ptr(img))
+ goto err;
+
is_secure = kwboot_img_is_secure(img);
if (hdr->blockid != IBR_HDR_UART_ID) {
hdr->blockid = IBR_HDR_UART_ID;
}
- if (baudrate) {
- uint32_t codesz = sizeof(kwboot_baud_code);
- void *code;
+ if (!is_secure) {
+ if (image_ver == 1) {
+ /*
+ * Tell BootROM to send BootROM messages to UART port
+ * number 0 (used also for UART booting) with default
+ * baudrate (which should be 115200) and do not touch
+ * UART MPP configuration.
+ */
+ hdr->options &= ~0x1F;
+ hdr->options |= MAIN_HDR_V1_OPT_BAUD_DEFAULT;
+ hdr->options |= 0 << 3;
+ }
+ if (image_ver == 0)
+ ((struct main_hdr_v0 *)img)->nandeccmode = IBR_HDR_ECC_DISABLED;
+ hdr->nandpagesize = 0;
+ }
+ if (baudrate) {
if (image_ver == 0) {
fprintf(stderr,
"Cannot inject code for changing baudrate into v0 image header\n");
*/
kwboot_printv("Injecting binary header code for changing baudrate to %d Bd\n",
baudrate);
-
- code = kwboot_add_bin_ohdr_v1(img, size, codesz);
- _copy_baudrate_change_code(hdr, code, 0, 115200, baudrate);
+ _inject_baudrate_change_code(img, size, 0, 115200, baudrate);
/*
* Now inject code that changes the baudrate back to 115200 Bd.
- * This code is prepended to the data part of the image, so it
- * is executed before U-Boot proper.
+ * This code is appended after the data part of the image, and
+ * execaddr is changed so that it is executed before U-Boot
+ * proper.
*/
kwboot_printv("Injecting code for changing baudrate back\n");
+ _inject_baudrate_change_code(img, size, 1, baudrate, 115200);
- codesz += sizeof(kwboot_pre_baud_code);
- code = kwboot_img_grow_data_left(img, size, codesz);
- _copy_baudrate_change_code(hdr, code, 1, baudrate, 115200);
+ /* Update the 32-bit data checksum */
+ *kwboot_img_csum32_ptr(img) = kwboot_img_csum32(img);
/* recompute header size */
hdrsz = kwbheader_size(hdr);
}
if (hdrsz % KWBOOT_XM_BLKSZ) {
- size_t offset = (KWBOOT_XM_BLKSZ - hdrsz % KWBOOT_XM_BLKSZ) %
- KWBOOT_XM_BLKSZ;
+ size_t grow = KWBOOT_XM_BLKSZ - hdrsz % KWBOOT_XM_BLKSZ;
if (is_secure) {
fprintf(stderr, "Cannot align image with secure header\n");
}
kwboot_printv("Aligning image header to Xmodem block size\n");
- kwboot_img_grow_hdr(img, size, offset);
+ kwboot_img_grow_hdr(img, size, grow);
}
hdr->checksum = kwboot_hdr_csum8(hdr) - csum;
static void
kwboot_usage(FILE *stream, char *progname)
{
- fprintf(stream, "kwboot version %s\n", PLAIN_VERSION);
fprintf(stream,
"Usage: %s [OPTIONS] [-b <image> | -D <image> ] [-B <baud> ] <TTY>\n",
progname);
after_img_rsv = KWBOOT_XM_BLKSZ;
baudrate = 115200;
+ printf("kwboot version %s\n", PLAIN_VERSION);
+
kwboot_verbose = isatty(STDOUT_FILENO);
do {
baudrate = 0;
else
/* ensure we have enough space for baudrate change code */
- after_img_rsv += KWBOOT_BAUDRATE_BIN_HEADER_SZ +
- sizeof(kwboot_pre_baud_code) +
- sizeof(kwboot_baud_code);
+ after_img_rsv += sizeof(struct opt_hdr_v1) + 8 + 16 +
+ sizeof(kwboot_baud_code_binhdr_pre) +
+ sizeof(kwboot_baud_code) +
+ sizeof(kwboot_baud_code_binhdr_post) +
+ KWBOOT_XM_BLKSZ +
+ sizeof(kwboot_baud_code) +
+ sizeof(kwboot_baud_code_data_jump) +
+ KWBOOT_XM_BLKSZ;
if (imgpath) {
img = kwboot_read_image(imgpath, &size, after_img_rsv);
* Author: AKASHI Takahiro
*/
-#include <errno.h>
#include <getopt.h>
#include <malloc.h>
#include <stdbool.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
-#include <unistd.h>
#include <linux/types.h>
-#include <sys/mman.h>
#include <sys/stat.h>
#include <sys/types.h>
-#include "fdt_host.h"
-
typedef __u8 u8;
typedef __u16 u16;
typedef __u32 u32;
#define aligned_u64 __aligned_u64
-#define SIGNATURE_NODENAME "signature"
-#define OVERLAY_NODENAME "__overlay__"
-
#ifndef __packed
#define __packed __attribute__((packed))
#endif
{"raw", required_argument, NULL, 'r'},
{"index", required_argument, NULL, 'i'},
{"instance", required_argument, NULL, 'I'},
- {"dtb", required_argument, NULL, 'D'},
- {"public key", required_argument, NULL, 'K'},
- {"overlay", no_argument, NULL, 'O'},
{"help", no_argument, NULL, 'h'},
{NULL, 0, NULL, 0},
};
"\t-r, --raw <raw image> new raw image file\n"
"\t-i, --index <index> update image index\n"
"\t-I, --instance <instance> update hardware instance\n"
- "\t-K, --public-key <key file> public key esl file\n"
- "\t-D, --dtb <dtb file> dtb file\n"
- "\t-O, --overlay the dtb file is an overlay\n"
"\t-h, --help print a help message\n",
tool_name);
}
-static int fdt_add_pub_key_data(void *sptr, void *dptr, size_t key_size,
- bool overlay)
-{
- int parent;
- int ov_node;
- int frag_node;
- int ret = 0;
-
- if (overlay) {
- /*
- * The signature would be stored in the
- * first fragment node of the overlay
- */
- frag_node = fdt_first_subnode(dptr, 0);
- if (frag_node == -FDT_ERR_NOTFOUND) {
- fprintf(stderr,
- "Couldn't find the fragment node: %s\n",
- fdt_strerror(frag_node));
- goto done;
- }
-
- ov_node = fdt_subnode_offset(dptr, frag_node, OVERLAY_NODENAME);
- if (ov_node == -FDT_ERR_NOTFOUND) {
- fprintf(stderr,
- "Couldn't find the __overlay__ node: %s\n",
- fdt_strerror(ov_node));
- goto done;
- }
- } else {
- ov_node = 0;
- }
-
- parent = fdt_subnode_offset(dptr, ov_node, SIGNATURE_NODENAME);
- if (parent == -FDT_ERR_NOTFOUND) {
- parent = fdt_add_subnode(dptr, ov_node, SIGNATURE_NODENAME);
- if (parent < 0) {
- ret = parent;
- if (ret != -FDT_ERR_NOSPACE) {
- fprintf(stderr,
- "Couldn't create signature node: %s\n",
- fdt_strerror(parent));
- }
- }
- }
- if (ret)
- goto done;
-
- /* Write the key to the FDT node */
- ret = fdt_setprop(dptr, parent, "capsule-key",
- sptr, key_size);
-
-done:
- if (ret)
- ret = ret == -FDT_ERR_NOSPACE ? -ENOSPC : -EIO;
-
- return ret;
-}
-
-static int add_public_key(const char *pkey_file, const char *dtb_file,
- bool overlay)
-{
- int ret;
- int srcfd = -1;
- int destfd = -1;
- void *sptr = NULL;
- void *dptr = NULL;
- off_t src_size;
- struct stat pub_key;
- struct stat dtb;
-
- /* Find out the size of the public key */
- srcfd = open(pkey_file, O_RDONLY);
- if (srcfd == -1) {
- fprintf(stderr, "%s: Can't open %s: %s\n",
- __func__, pkey_file, strerror(errno));
- ret = -1;
- goto err;
- }
-
- ret = fstat(srcfd, &pub_key);
- if (ret == -1) {
- fprintf(stderr, "%s: Can't stat %s: %s\n",
- __func__, pkey_file, strerror(errno));
- ret = -1;
- goto err;
- }
-
- src_size = pub_key.st_size;
-
- /* mmap the public key esl file */
- sptr = mmap(0, src_size, PROT_READ, MAP_SHARED, srcfd, 0);
- if (sptr == MAP_FAILED) {
- fprintf(stderr, "%s: Failed to mmap %s:%s\n",
- __func__, pkey_file, strerror(errno));
- ret = -1;
- goto err;
- }
-
- /* Open the dest FDT */
- destfd = open(dtb_file, O_RDWR);
- if (destfd == -1) {
- fprintf(stderr, "%s: Can't open %s: %s\n",
- __func__, dtb_file, strerror(errno));
- ret = -1;
- goto err;
- }
-
- ret = fstat(destfd, &dtb);
- if (ret == -1) {
- fprintf(stderr, "%s: Can't stat %s: %s\n",
- __func__, dtb_file, strerror(errno));
- goto err;
- }
-
- dtb.st_size += src_size + 0x30;
- if (ftruncate(destfd, dtb.st_size)) {
- fprintf(stderr, "%s: Can't expand %s: %s\n",
- __func__, dtb_file, strerror(errno));
- ret = -1;
- goto err;
- }
-
- errno = 0;
- /* mmap the dtb file */
- dptr = mmap(0, dtb.st_size, PROT_READ | PROT_WRITE, MAP_SHARED,
- destfd, 0);
- if (dptr == MAP_FAILED) {
- fprintf(stderr, "%s: Failed to mmap %s:%s\n",
- __func__, dtb_file, strerror(errno));
- ret = -1;
- goto err;
- }
-
- if (fdt_check_header(dptr)) {
- fprintf(stderr, "%s: Invalid FDT header\n", __func__);
- ret = -1;
- goto err;
- }
-
- ret = fdt_open_into(dptr, dptr, dtb.st_size);
- if (ret) {
- fprintf(stderr, "%s: Cannot expand FDT: %s\n",
- __func__, fdt_strerror(ret));
- ret = -1;
- goto err;
- }
-
- /* Copy the esl file to the expanded FDT */
- ret = fdt_add_pub_key_data(sptr, dptr, src_size, overlay);
- if (ret < 0) {
- fprintf(stderr, "%s: Unable to add public key to the FDT\n",
- __func__);
- ret = -1;
- goto err;
- }
-
- ret = 0;
-
-err:
- if (sptr)
- munmap(sptr, src_size);
-
- if (dptr)
- munmap(dptr, dtb.st_size);
-
- if (srcfd != -1)
- close(srcfd);
-
- if (destfd != -1)
- close(destfd);
-
- return ret;
-}
-
static int create_fwbin(char *path, char *bin, efi_guid_t *guid,
unsigned long index, unsigned long instance)
{
int main(int argc, char **argv)
{
char *file;
- char *pkey_file;
- char *dtb_file;
efi_guid_t *guid;
unsigned long index, instance;
int c, idx;
- int ret;
- bool overlay = false;
file = NULL;
- pkey_file = NULL;
- dtb_file = NULL;
guid = NULL;
index = 0;
instance = 0;
for (;;) {
- c = getopt_long(argc, argv, "f:r:i:I:v:D:K:Oh", options, &idx);
+ c = getopt_long(argc, argv, "f:r:i:I:v:h", options, &idx);
if (c == -1)
break;
case 'I':
instance = strtoul(optarg, NULL, 0);
break;
- case 'K':
- if (pkey_file) {
- printf("Public Key already specified\n");
- return -1;
- }
- pkey_file = optarg;
- break;
- case 'D':
- if (dtb_file) {
- printf("DTB file already specified\n");
- return -1;
- }
- dtb_file = optarg;
- break;
- case 'O':
- overlay = true;
- break;
case 'h':
print_usage();
return 0;
}
}
- /* need a fit image file or raw image file */
- if (!file && !pkey_file && !dtb_file) {
+ /* need an output file */
+ if (argc != optind + 1) {
print_usage();
exit(EXIT_FAILURE);
}
- if (pkey_file && dtb_file) {
- ret = add_public_key(pkey_file, dtb_file, overlay);
- if (ret == -1) {
- printf("Adding public key to the dtb failed\n");
- exit(EXIT_FAILURE);
- } else {
- exit(EXIT_SUCCESS);
- }
+ /* need a fit image file or raw image file */
+ if (!file) {
+ print_usage();
+ exit(EXIT_SUCCESS);
}
if (create_fwbin(argv[optind], file, guid, index, instance)
#include <stdlib.h>
#include <string.h>
#include <errno.h>
+#include <sunxi_image.h>
#include <sys/types.h>
#include <sys/stat.h>
#include "imagetool.h"
-#include "../arch/arm/include/asm/arch-sunxi/spl.h"
#define STAMP_VALUE 0x5F0A6C39
well. If your format.subjectprefix is set to InternalProject, then
the patch shows like: [InternalProject][RFC/RESEND PATCH]
+Series-postfix: postfix
+ Sets the subject "postfix". Normally empty, but can be the name of a
+ tree such as net or net-next if that needs to be specified. The patch
+ subject is like [PATCH net] or [PATCH net-next].
+
Series-name: name
Sets the name of the series. You don't need to have a name, and
patman does not yet use it, but it is convenient to put the branch
def RunPipe(pipe_list, infile=None, outfile=None,
capture=False, capture_stderr=False, oneline=False,
- raise_on_error=True, cwd=None, binary=False, **kwargs):
+ raise_on_error=True, cwd=None, binary=False,
+ output_func=None, **kwargs):
"""
Perform a command pipeline, with optional input/output filenames.
capture: True to capture output
capture_stderr: True to capture stderr
oneline: True to strip newline chars from output
+ output_func: Output function to call with each output fragment
+ (if it returns True the function terminates)
kwargs: Additional keyword arguments to cros_subprocess.Popen()
Returns:
CommandResult object
if capture:
result.stdout, result.stderr, result.combined = (
- last_pipe.CommunicateFilter(None))
+ last_pipe.CommunicateFilter(output_func))
if result.stdout and oneline:
result.output = result.stdout.rstrip(b'\r\n')
result.return_code = last_pipe.wait()
sys.stdout or sys.stderr.
data: a string containing the data
+ Returns:
+ True to terminate the process
+
Note: The data read is buffered in memory, so do not use this
method if the data size is large or unlimited.
stderr = bytearray()
combined = bytearray()
+ stop_now = False
input_offset = 0
while read_set or write_set:
try:
stdout += data
combined += data
if output:
- output(sys.stdout, data)
+ stop_now = output(sys.stdout, data)
if self.stderr in rlist:
data = b''
# We will get an error on read if the pty is closed
stderr += data
combined += data
if output:
- output(sys.stderr, data)
+ stop_now = output(sys.stderr, data)
+ if stop_now:
+ self.terminate()
# All data exchanged. Translate lists into strings.
stdout = self.ConvertData(stdout)
Series-to: u-boot
Series-prefix: RFC
+ Series-postfix: some-branch
Series-cc: Stefan Brüns <stefan.bruens@rwth-aachen.de>
Cover-letter-cc: Lord Mëlchett <clergy@palace.gov>
Series-version: 3
- each patch has the correct subject
- dry-run information prints out correctly
- unicode is handled correctly
- - Series-to, Series-cc, Series-prefix, Cover-letter
+ - Series-to, Series-cc, Series-prefix, Series-postfix, Cover-letter
- Cover-letter-cc, Series-version, Series-changes, Series-notes
- Commit-notes
"""
self.assertEqual('Cc: %s' % stefan, next(lines))
self.assertEqual('Version: 3', next(lines))
self.assertEqual('Prefix:\t RFC', next(lines))
+ self.assertEqual('Postfix:\t some-branch', next(lines))
self.assertEqual('Cover: 4 lines', next(lines))
self.assertEqual(' Cc: %s' % self.fred, next(lines))
self.assertEqual(' Cc: %s' % self.leb,
'''
lines = open(cover_fname, encoding='utf-8').read().splitlines()
self.assertEqual(
- 'Subject: [RFC PATCH v3 0/2] test: A test patch series',
+ 'Subject: [RFC PATCH some-branch v3 0/2] test: A test patch series',
lines[3])
self.assertEqual(expected.splitlines(), lines[7:])
# These seem like they would be nice to include.
if 'prefix' in self.series:
parts.append(self.series['prefix'])
+ if 'postfix' in self.series:
+ parts.append(self.serties['postfix'])
if 'version' in self.series:
parts.append("v%s" % self.series['version'])
# Series-xxx tags that we understand
valid_series = ['to', 'cc', 'version', 'changes', 'prefix', 'notes', 'name',
- 'cover_cc', 'process_log', 'links', 'patchwork_url']
+ 'cover_cc', 'process_log', 'links', 'patchwork_url', 'postfix']
class Series(dict):
"""Holds information about a patch series, including all tags.
print('Cc:\t ', item)
print('Version: ', self.get('version'))
print('Prefix:\t ', self.get('prefix'))
+ print('Postfix:\t ', self.get('postfix'))
if self.cover:
print('Cover: %d lines' % len(self.cover))
cover_cc = gitutil.BuildEmailList(self.get('cover_cc', ''))
prefix = ''
if self.get('prefix'):
prefix = '%s ' % self['prefix']
- return '%s%sPATCH%s' % (git_prefix, prefix, version)
+
+ postfix = ''
+ if self.get('postfix'):
+ postfix = ' %s' % self['postfix']
+ return '%s%sPATCH%s%s' % (git_prefix, prefix, postfix, version)
Signed-off-by: Simon Glass <sjg@chromium.org>
Series-to: u-boot
Series-prefix: RFC
+ Series-postfix: some-branch
Series-cc: Stefan Brüns <stefan.bruens@rwth-aachen.de>
Cover-letter-cc: Lord Mëlchett <clergy@palace.gov>
Series-version: 3
result = command.RunPipe([all_args], capture=True, capture_stderr=True,
env=env, raise_on_error=False, binary=binary)
if result.return_code:
- raise Exception("Error %d running '%s': %s" %
+ raise ValueError("Error %d running '%s': %s" %
(result.return_code,' '.join(all_args),
result.stderr))
return result.stdout
static inline int tcsendbreak(int fd, int d)
{
- return ioctl(fd, TCSBRK, d);
+#ifdef TCSBRKP
+ return ioctl(fd, TCSBRKP, d);
+#else
+ return ioctl(fd, TCSBRK, 0);
+#endif
}
static inline int tcflow(int fd, int a)
projects / platform / kernel / u-boot.git / commitdiff