drm/amd/display: Fix hangs with psr enabled on dcn3.xx

[Why]
SKIP_CRTC_DISABLE bit should be applicable to all dcn asics
not only Raven.

[How]
Replace check for Raven only with check for all DCNs.

Signed-off-by: Roman Li <Roman.Li@amd.com>
Acked-by: Bindu Ramamurthy <bindur12@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index ac7a2b7..9507b08 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2813,12 +2813,9 @@ bool dc_link_setup_psr(struct dc_link *link,
 
        psr_context->psr_level.u32all = 0;
 
-#if defined(CONFIG_DRM_AMD_DC_DCN)
        /*skip power down the single pipe since it blocks the cstate*/
-       if ((link->ctx->asic_id.chip_family == FAMILY_RV) &&
-            ASICREV_IS_RAVEN(link->ctx->asic_id.hw_internal_rev))
+       if (link->ctx->asic_id.chip_family >= FAMILY_RV)
                psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
-#endif
 
        /* SMU will perform additional powerdown sequence.
         * For unsupported ASICs, set psr_level flag to skip PSR