case TargetOpcode::G_AND:
return AArch64::ANDXrr;
case TargetOpcode::G_ADD:
+ case TargetOpcode::G_GEP:
return AArch64::ADDXrr;
case TargetOpcode::G_SUB:
return AArch64::SUBXrr;
case TargetOpcode::G_SDIV:
case TargetOpcode::G_UDIV:
case TargetOpcode::G_ADD:
- case TargetOpcode::G_SUB: {
+ case TargetOpcode::G_SUB:
+ case TargetOpcode::G_GEP: {
// Reject the various things we don't support yet.
if (unsupportedBinOp(I, RBI, MRI, TRI))
return false;
define i32 @const_s32() { ret i32 42 }
define i64 @const_s64() { ret i64 1234567890123 }
+ define i8* @gep(i8* %in) { ret i8* undef }
...
---
bb.0:
%0(s64) = G_CONSTANT 1234567890123
...
+
+---
+# CHECK-LABEL: name: gep
+name: gep
+legalized: true
+regBankSelected: true
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+ - { id: 2, class: gpr }
+
+# CHECK: body:
+# CHECK: %1 = MOVi64imm 42
+# CHECK: %2 = ADDXrr %0, %1
+body: |
+ bb.0:
+ %0(p0) = COPY %x0
+ %1(s64) = G_CONSTANT 42
+ %2(p0) = G_GEP %0, %1(s64)
+...