remove FEATURE_AVX_SUPPORT flag

diff --git a/src/jit/CMakeLists.txt b/src/jit/CMakeLists.txt
index a6efcd8..bf5fdaa 100644 (file)
--- a/src/jit/CMakeLists.txt
+++ b/src/jit/CMakeLists.txt
@@ -6,7 +6,6 @@ include_directories("../inc")
 
 if (CLR_CMAKE_TARGET_ARCH_AMD64 OR (CLR_CMAKE_TARGET_ARCH_I386 AND NOT CLR_CMAKE_PLATFORM_UNIX))
   add_definitions(-DFEATURE_SIMD)
-  add_definitions(-DFEATURE_AVX_SUPPORT)
 endif ()
 
 # JIT_BUILD disables certain PAL_TRY debugging features

diff --git a/src/jit/codegencommon.cpp b/src/jit/codegencommon.cpp
index 07a5241..e195553 100644 (file)
--- a/src/jit/codegencommon.cpp
+++ b/src/jit/codegencommon.cpp
@@ -11154,7 +11154,6 @@ void CodeGen::genRestoreCalleeSavedFltRegs(unsigned lclFrameSize)
 //
 void CodeGen::genVzeroupperIfNeeded(bool check256bitOnly /* = true*/)
 {
-#ifdef FEATURE_AVX_SUPPORT
     bool emitVzeroUpper = false;
     if (check256bitOnly)
     {
@@ -11170,7 +11169,6 @@ void CodeGen::genVzeroupperIfNeeded(bool check256bitOnly /* = true*/)
         assert(compiler->getSIMDInstructionSet() == InstructionSet_AVX);
         instGen(INS_vzeroupper);
     }
-#endif
 }
 
 #endif // defined(_TARGET_XARCH_) && !FEATURE_STACK_FP_X87

diff --git a/src/jit/codegenxarch.cpp b/src/jit/codegenxarch.cpp
index a512436..adfb575 100644 (file)
--- a/src/jit/codegenxarch.cpp
+++ b/src/jit/codegenxarch.cpp
@@ -5370,7 +5370,6 @@ void CodeGen::genCallInstruction(GenTreeCall* call)
     }
 #endif // defined(_TARGET_X86_)
 
-#ifdef FEATURE_AVX_SUPPORT
     // When it's a PInvoke call and the call type is USER function, we issue VZEROUPPER here
     // if the function contains 256bit AVX instructions, this is to avoid AVX-256 to Legacy SSE
     // transition penalty, assuming the user function contains legacy SSE instruction.
@@ -5382,7 +5381,6 @@ void CodeGen::genCallInstruction(GenTreeCall* call)
         assert(compiler->getSIMDInstructionSet() == InstructionSet_AVX);
         instGen(INS_vzeroupper);
     }
-#endif
 
     if (target != nullptr)
     {
@@ -8732,7 +8730,6 @@ void CodeGen::genAmd64EmitterUnitTests()
     CLANG_FORMAT_COMMENT_ANCHOR;
 
 #ifdef ALL_XARCH_EMITTER_UNIT_TESTS
-#ifdef FEATURE_AVX_SUPPORT
     genDefineTempLabel(genCreateTempLabel());
 
     // vhaddpd     ymm0,ymm1,ymm2
@@ -8802,7 +8799,6 @@ void CodeGen::genAmd64EmitterUnitTests()
     getEmitter()->emitIns_R_R_R(INS_cvtss2sd, EA_4BYTE, REG_XMM0, REG_XMM1, REG_XMM2);
     // vdivsd      xmm0,xmm1,xmm2
     getEmitter()->emitIns_R_R_R(INS_cvtsd2ss, EA_8BYTE, REG_XMM0, REG_XMM1, REG_XMM2);
-#endif // FEATURE_AVX_SUPPORT
 #endif // ALL_XARCH_EMITTER_UNIT_TESTS
     printf("*************** End of genAmd64EmitterUnitTests()\n");
 }

diff --git a/src/jit/compiler.cpp b/src/jit/compiler.cpp
index 2421693..183e36a 100644 (file)
--- a/src/jit/compiler.cpp
+++ b/src/jit/compiler.cpp
@@ -2473,7 +2473,6 @@ void Compiler::compSetProcessor()
         }
     }
 
-#ifdef FEATURE_AVX_SUPPORT
     // COMPlus_EnableAVX can be used to disable using AVX if available on a target machine.
     opts.compCanUseAVX = false;
     if (!jitFlags.IsSet(JitFlags::JIT_FLAG_PREJIT) && jitFlags.IsSet(JitFlags::JIT_FLAG_USE_AVX2))
@@ -2483,11 +2482,9 @@ void Compiler::compSetProcessor()
             opts.compCanUseAVX = true;
         }
     }
-#endif // FEATURE_AVX_SUPPORT
 
     if (!compIsForInlining())
     {
-#ifdef FEATURE_AVX_SUPPORT
         if (opts.compCanUseAVX)
         {
             codeGen->getEmitter()->SetUseAVX(true);
@@ -2495,9 +2492,7 @@ void Compiler::compSetProcessor()
             codeGen->getEmitter()->SetContainsAVX(false);
             codeGen->getEmitter()->SetContains256bitAVX(false);
         }
-        else
-#endif // FEATURE_AVX_SUPPORT
-            if (opts.compCanUseSSE3_4)
+        else if (opts.compCanUseSSE3_4)
         {
             codeGen->getEmitter()->SetUseSSE3_4(true);
         }

diff --git a/src/jit/compiler.h b/src/jit/compiler.h
index 1cc6845..cd65c25 100644 (file)
--- a/src/jit/compiler.h
+++ b/src/jit/compiler.h
@@ -138,11 +138,7 @@ unsigned ReinterpretHexAsDecimal(unsigned);
 /*****************************************************************************/
 
 #ifdef FEATURE_SIMD
-#ifdef FEATURE_AVX_SUPPORT
 const unsigned TEMP_MAX_SIZE = YMM_REGSIZE_BYTES;
-#else  // !FEATURE_AVX_SUPPORT
-const unsigned TEMP_MAX_SIZE = XMM_REGSIZE_BYTES;
-#endif // !FEATURE_AVX_SUPPORT
 #else  // !FEATURE_SIMD
 const unsigned TEMP_MAX_SIZE = sizeof(double);
 #endif // !FEATURE_SIMD
@@ -7691,13 +7687,6 @@ private:
         return emitTypeSize(TYP_SIMD8);
     }
 
-#ifdef FEATURE_AVX_SUPPORT
-    // (maxPossibleSIMDStructBytes is for use in a context that requires a compile-time constant.)
-    static const unsigned maxPossibleSIMDStructBytes = 32;
-#else  // !FEATURE_AVX_SUPPORT
-    static const unsigned maxPossibleSIMDStructBytes = 16;
-#endif // !FEATURE_AVX_SUPPORT
-
     // Returns the codegen type for a given SIMD size.
     var_types getSIMDTypeForSize(unsigned size)
     {
@@ -7714,12 +7703,10 @@ private:
         {
             simdType = TYP_SIMD16;
         }
-#ifdef FEATURE_AVX_SUPPORT
         else if (size == 32)
         {
             simdType = TYP_SIMD32;
         }
-#endif // FEATURE_AVX_SUPPORT
         else
         {
             noway_assert(!"Unexpected size for SIMD type");
@@ -7830,7 +7817,7 @@ private:
 
     bool canUseAVX() const
     {
-#ifdef FEATURE_AVX_SUPPORT
+#ifdef _TARGET_XARCH_
         return opts.compCanUseAVX;
 #else
         return false;
@@ -7953,11 +7940,8 @@ public:
 #ifdef _TARGET_XARCH_
         bool compCanUseSSE2;   // Allow CodeGen to use "movq XMM" instructions
         bool compCanUseSSE3_4; // Allow CodeGen to use SSE3, SSSE3, SSE4.1 and SSE4.2 instructions
-
-#ifdef FEATURE_AVX_SUPPORT
-        bool compCanUseAVX; // Allow CodeGen to use AVX 256-bit vectors for SIMD operations
-#endif                      // FEATURE_AVX_SUPPORT
-#endif                      // _TARGET_XARCH_
+        bool compCanUseAVX;    // Allow CodeGen to use AVX 256-bit vectors for SIMD operations
+#endif                         // _TARGET_XARCH_
 
 #ifdef _TARGET_XARCH_
         uint64_t compSupportsISA;

diff --git a/src/jit/dll/jit.nativeproj b/src/jit/dll/jit.nativeproj
index 7505f5e..4d796f3 100644 (file)
--- a/src/jit/dll/jit.nativeproj
+++ b/src/jit/dll/jit.nativeproj
@@ -30,7 +30,7 @@
 
     <LinkModuleDefinitionFile>$(OutputName).def</LinkModuleDefinitionFile>
 
-    <ClDefines Condition="'$(BuildArchitecture)' == 'amd64'">$(ClDefines);FEATURE_SIMD;FEATURE_AVX_SUPPORT</ClDefines>
+    <ClDefines Condition="'$(BuildArchitecture)' == 'amd64'">$(ClDefines);FEATURE_SIMD</ClDefines>
 
     <Win32DllLibs>$(SdkLibPath)\kernel32.lib;$(SdkLibPath)\user32.lib;$(SdkLibPath)\advapi32.lib;$(SdkLibPath)\oleaut32.lib;$(SdkLibPath)\uuid.lib</Win32DllLibs>
     <Win32DllLibs>$(Win32DllLibs);$(ClrLibPath)\utilcode.lib</Win32DllLibs>

diff --git a/src/jit/ee_il_dll.cpp b/src/jit/ee_il_dll.cpp
index b32d59f..1f91ef6 100644 (file)
--- a/src/jit/ee_il_dll.cpp
+++ b/src/jit/ee_il_dll.cpp
@@ -397,7 +397,7 @@ unsigned CILJit::getMaxIntrinsicSIMDVectorLength(CORJIT_FLAGS cpuCompileFlags)
 
 #ifdef FEATURE_SIMD
 #ifdef _TARGET_XARCH_
-#ifdef FEATURE_AVX_SUPPORT
+#ifndef LEGACY_BACKEND
     if (!jitFlags.IsSet(JitFlags::JIT_FLAG_PREJIT) && jitFlags.IsSet(JitFlags::JIT_FLAG_FEATURE_SIMD) &&
         jitFlags.IsSet(JitFlags::JIT_FLAG_USE_AVX2))
     {
@@ -410,7 +410,7 @@ unsigned CILJit::getMaxIntrinsicSIMDVectorLength(CORJIT_FLAGS cpuCompileFlags)
             return 32;
         }
     }
-#endif // FEATURE_AVX_SUPPORT
+#endif // !LEGACY_BACKEND
     if (GetJitTls() != nullptr && JitTls::GetCompiler() != nullptr)
     {
         JITDUMP("getMaxIntrinsicSIMDVectorLength: returning 16\n");

diff --git a/src/jit/emit.h b/src/jit/emit.h
index 8c2b825..63243f4 100644 (file)
--- a/src/jit/emit.h
+++ b/src/jit/emit.h
@@ -428,11 +428,8 @@ public:
 
 #ifdef _TARGET_XARCH_
         SetUseSSE3_4(false);
-#endif // _TARGET_XARCH_
-
-#ifdef FEATURE_AVX_SUPPORT
         SetUseAVX(false);
-#endif // FEATURE_AVX_SUPPORT
+#endif // _TARGET_XARCH_
     }
 
 #include "emitpub.h"
@@ -938,12 +935,12 @@ protected:
                 regNumber _idReg3 : REGNUM_BITS;
                 regNumber _idReg4 : REGNUM_BITS;
             };
-#elif defined(_TARGET_XARCH_) && !defined(LEGACY_BACKEND)
+#elif defined(_TARGET_XARCH_)
             struct
             {
                 regNumber _idReg3 : REGNUM_BITS;
             };
-#endif // defined(_TARGET_XARCH_) && !defined(LEGACY_BACKEND)
+#endif // defined(_TARGET_XARCH_)
 
         } _idAddrUnion;
 
@@ -1109,7 +1106,7 @@ protected:
             assert(reg == _idReg2);
         }
 
-#if defined(_TARGET_XARCH_) && !defined(LEGACY_BACKEND)
+#if defined(_TARGET_XARCH_)
         regNumber idReg3() const
         {
             assert(!idIsTiny());
@@ -1123,7 +1120,7 @@ protected:
             idAddr()->_idReg3 = reg;
             assert(reg == idAddr()->_idReg3);
         }
-#endif // defined(_TARGET_XARCH_) && !defined(LEGACY_BACKEND)
+#endif // defined(_TARGET_XARCH_)
 #ifdef _TARGET_ARMARCH_
         insOpts idInsOpt() const
         {

diff --git a/src/jit/emitxarch.cpp b/src/jit/emitxarch.cpp
index d918cbd..09fdb1b 100644 (file)
--- a/src/jit/emitxarch.cpp
+++ b/src/jit/emitxarch.cpp
@@ -41,16 +41,16 @@ bool IsSSE4Instruction(instruction ins)
 
 bool IsSSEOrAVXInstruction(instruction ins)
 {
-#ifdef FEATURE_AVX_SUPPORT
+#ifndef LEGACY_BACKEND
     return (ins >= INS_FIRST_SSE2_INSTRUCTION && ins <= INS_LAST_AVX_INSTRUCTION);
-#else  // !FEATURE_AVX_SUPPORT
+#else  // !LEGACY_BACKEND
     return IsSSE2Instruction(ins);
-#endif // !FEATURE_AVX_SUPPORT
+#endif // LEGACY_BACKEND
 }
 
 bool IsAVXOnlyInstruction(instruction ins)
 {
-#ifdef FEATURE_AVX_SUPPORT
+#ifndef LEGACY_BACKEND
     return (ins >= INS_FIRST_AVX_INSTRUCTION && ins <= INS_LAST_AVX_INSTRUCTION);
 #else
     return false;
@@ -59,14 +59,14 @@ bool IsAVXOnlyInstruction(instruction ins)
 
 bool emitter::IsAVXInstruction(instruction ins)
 {
-#ifdef FEATURE_AVX_SUPPORT
+#ifndef LEGACY_BACKEND
     return (UseAVX() && IsSSEOrAVXInstruction(ins));
 #else
     return false;
 #endif
 }
 
-#ifdef FEATURE_AVX_SUPPORT
+#ifndef LEGACY_BACKEND
 // Returns true if the AVX instruction is a binary operator that requires 3 operands.
 // When we emit an instruction with only two operands, we will duplicate the destination
 // as a source.
@@ -122,7 +122,7 @@ bool emitter::Is4ByteAVXInstruction(instruction ins)
 {
     return UseAVX() && (IsSSE4Instruction(ins) || IsAVXOnlyInstruction(ins)) && EncodedBySSE38orSSE3A(ins);
 }
-#endif // FEATURE_AVX_SUPPORT
+#endif // !LEGACY_BACKEND
 
 // -------------------------------------------------------------------
 // Is4ByteSSE4Instruction: Returns true if the SSE4 instruction
@@ -143,7 +143,7 @@ bool emitter::Is4ByteSSE4Instruction(instruction ins)
 #endif
 }
 
-#ifdef FEATURE_AVX_SUPPORT
+#ifndef LEGACY_BACKEND
 // Returns true if this instruction requires a VEX prefix
 // All AVX instructions require a VEX prefix
 bool emitter::TakesVexPrefix(instruction ins)
@@ -202,7 +202,7 @@ emitter::code_t emitter::AddVexPrefix(instruction ins, code_t code, emitAttr att
 
     return code;
 }
-#endif // FEATURE_AVX_SUPPORT
+#endif // !LEGACY_BACKEND
 
 // Returns true if this instruction, for the given EA_SIZE(attr), will require a REX.W prefix
 bool TakesRexWPrefix(instruction ins, emitAttr attr)
@@ -442,7 +442,7 @@ bool isPrefix(BYTE b)
 // Outputs VEX prefix (in case of AVX instructions) and REX.R/X/W/B otherwise.
 unsigned emitter::emitOutputRexOrVexPrefixIfNeeded(instruction ins, BYTE* dst, code_t& code)
 {
-#ifdef FEATURE_AVX_SUPPORT
+#ifndef LEGACY_BACKEND
     if (hasVexPrefix(code))
     {
         // Only AVX instructions should have a VEX prefix
@@ -540,7 +540,7 @@ unsigned emitter::emitOutputRexOrVexPrefixIfNeeded(instruction ins, BYTE* dst, c
         emitOutputByte(dst + 2, vexPrefix & 0xFF);
         return 3;
     }
-#endif // FEATURE_AVX_SUPPORT
+#endif // !LEGACY_BACKEND
 
 #ifdef _TARGET_AMD64_
     if (code > 0x00FFFFFFFFLL)
@@ -670,7 +670,7 @@ unsigned emitter::emitGetVexPrefixSize(instruction ins, emitAttr attr)
 //=opcodeSize + vexPrefixAdjustedSize
 unsigned emitter::emitGetVexPrefixAdjustedSize(instruction ins, emitAttr attr, code_t code)
 {
-#ifdef FEATURE_AVX_SUPPORT
+#ifndef LEGACY_BACKEND
     if (IsAVXInstruction(ins))
     {
         unsigned vexPrefixAdjustedSize = emitGetVexPrefixSize(ins, attr);
@@ -706,8 +706,7 @@ unsigned emitter::emitGetVexPrefixAdjustedSize(instruction ins, emitAttr attr, c
 
         return vexPrefixAdjustedSize;
     }
-#endif // FEATURE_AVX_SUPPORT
-
+#endif // !LEGACY_BACKEND
     return 0;
 }
 
@@ -1246,7 +1245,7 @@ inline unsigned emitter::insEncodeReg345(instruction ins, regNumber reg, emitAtt
  */
 inline emitter::code_t emitter::insEncodeReg3456(instruction ins, regNumber reg, emitAttr size, code_t code)
 {
-#ifdef FEATURE_AVX_SUPPORT
+#ifndef LEGACY_BACKEND
     assert(reg < REG_STK);
     assert(IsAVXInstruction(ins));
     assert(hasVexPrefix(code));
@@ -3840,7 +3839,7 @@ void emitter::emitIns_R_R_I(instruction ins, emitAttr attr, regNumber reg1, regN
     dispIns(id);
     emitCurIGsize += sz;
 }
-#ifdef FEATURE_AVX_SUPPORT
+
 /*****************************************************************************
 *
 *  Add an instruction with three register operands.
@@ -3901,7 +3900,6 @@ void emitter::emitIns_R_R_R_I(
     emitCurIGsize += sz;
 }
 
-#endif
 /*****************************************************************************
  *
  *  Add an instruction with a register + static member operands.
@@ -6718,13 +6716,12 @@ void emitter::emitDispIns(
     /* Display the instruction name */
 
     sstr = codeGen->genInsName(ins);
-#ifdef FEATURE_AVX_SUPPORT
+
     if (IsAVXInstruction(ins))
     {
         printf(" v%-8s", sstr);
     }
     else
-#endif // FEATURE_AVX_SUPPORT
     {
         printf(" %-9s", sstr);
     }
@@ -7091,7 +7088,6 @@ void emitter::emitDispIns(
             printf(" %s", emitRegName(id->idReg2(), attr));
             break;
 
-#ifdef FEATURE_AVX_SUPPORT
         case IF_RWR_RRD_RRD:
             assert(IsAVXInstruction(ins));
             assert(IsThreeOperandAVXInstruction(ins));
@@ -7108,7 +7104,6 @@ void emitter::emitDispIns(
             val = emitGetInsSC(id);
             goto PRINT_CONSTANT;
             break;
-#endif
         case IF_RRW_RRW_CNS:
             printf("%s,", emitRegName(id->idReg1(), attr));
             printf(" %s", emitRegName(id->idReg2(), attr));
@@ -9487,7 +9482,6 @@ BYTE* emitter::emitOutputRR(BYTE* dst, instrDesc* id)
     return dst;
 }
 
-#ifdef FEATURE_AVX_SUPPORT
 BYTE* emitter::emitOutputRRR(BYTE* dst, instrDesc* id)
 {
     code_t code;
@@ -9563,7 +9557,6 @@ BYTE* emitter::emitOutputRRR(BYTE* dst, instrDesc* id)
 
     return dst;
 }
-#endif
 
 /*****************************************************************************
  *
@@ -10756,7 +10749,6 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp)
             sz  = emitSizeOfInsDsc(id);
             break;
 
-#ifdef FEATURE_AVX_SUPPORT
         case IF_RWR_RRD_RRD:
             dst = emitOutputRRR(dst, id);
             sz  = emitSizeOfInsDsc(id);
@@ -10766,7 +10758,6 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp)
             sz  = emitSizeOfInsDsc(id);
             dst += emitOutputByte(dst, emitGetInsSC(id));
             break;
-#endif
 
         case IF_RRW_RRW_CNS:
             assert(id->idGCref() == GCT_NONE);
@@ -10796,7 +10787,6 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp)
             }
             assert(code & 0x00FF0000);
 
-#ifdef FEATURE_AVX_SUPPORT
             if (TakesRexWPrefix(ins, size))
             {
                 code = AddRexWPrefix(ins, code);
@@ -10821,7 +10811,6 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp)
                     code = insEncodeReg3456(ins, id->idReg2(), size, code);
                 }
             }
-#endif // FEATURE_AVX_SUPPORT
 
             regcode = (insEncodeReg345(ins, rReg, size, &code) | insEncodeReg012(ins, mReg, size, &code)) << 8;
 
@@ -11174,7 +11163,6 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp)
         case IF_MWR_RRD:
         case IF_MRW_RRD:
             code = insCodeMR(ins);
-#ifdef FEATURE_AVX_SUPPORT
             code = AddVexPrefixIfNeeded(ins, code, size);
 
             // In case of AVX instructions that take 3 operands, encode reg1 as first source.
@@ -11188,7 +11176,6 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp)
                 // encode source operand reg in 'vvvv' bits in 1's compliement form
                 code = insEncodeReg3456(ins, id->idReg1(), size, code);
             }
-#endif // FEATURE_AVX_SUPPORT
 
             regcode = (insEncodeReg345(ins, id->idReg1(), size, &code) << 8);
             dst     = emitOutputCV(dst, id, code | regcode | 0x0500);

diff --git a/src/jit/emitxarch.h b/src/jit/emitxarch.h
index 2bafe85..de8e81f 100644 (file)
--- a/src/jit/emitxarch.h
+++ b/src/jit/emitxarch.h
@@ -62,9 +62,7 @@ BYTE* emitOutputRI(BYTE* dst, instrDesc* id);
 BYTE* emitOutputRR(BYTE* dst, instrDesc* id);
 BYTE* emitOutputIV(BYTE* dst, instrDesc* id);
 
-#ifdef FEATURE_AVX_SUPPORT
 BYTE* emitOutputRRR(BYTE* dst, instrDesc* id);
-#endif
 
 BYTE* emitOutputLJ(BYTE* dst, instrDesc* id);
 
@@ -118,7 +116,7 @@ bool hasRexPrefix(code_t code)
 #endif // !_TARGET_AMD64_
 }
 
-#ifdef FEATURE_AVX_SUPPORT
+#ifndef LEGACY_BACKEND
 
 // 3-byte VEX prefix starts with byte 0xC4
 #define VEX_PREFIX_MASK_3BYTE 0xFF000000000000ULL
@@ -186,19 +184,28 @@ bool IsThreeOperandAVXInstruction(instruction ins)
     return (IsDstDstSrcAVXInstruction(ins) || IsDstSrcSrcAVXInstruction(ins));
 }
 bool Is4ByteAVXInstruction(instruction ins);
-#else  // !FEATURE_AVX_SUPPORT
+#else  // LEGACY_BACKEND
 bool UseAVX()
 {
     return false;
 }
+void SetUseAVX(bool value)
+{
+}
 bool ContainsAVX()
 {
     return false;
 }
+void SetContainsAVX(bool value)
+{
+}
 bool Contains256bitAVX()
 {
     return false;
 }
+void SetContains256bitAVX(bool value)
+{
+}
 bool hasVexPrefix(code_t code)
 {
     return false;
@@ -231,7 +238,7 @@ code_t AddVexPrefixIfNeededAndNotPresent(instruction ins, code_t code, emitAttr
 {
     return code;
 }
-#endif // !FEATURE_AVX_SUPPORT
+#endif // LEGACY_BACKEND
 
 /************************************************************************/
 /*             Debug-only routines to display instructions              */
@@ -358,11 +365,9 @@ void emitIns_R_R(instruction ins, emitAttr attr, regNumber reg1, regNumber reg2)
 
 void emitIns_R_R_I(instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, int ival);
 
-#ifdef FEATURE_AVX_SUPPORT
 void emitIns_R_R_R(instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, regNumber reg3);
 
 void emitIns_R_R_R_I(instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, regNumber reg3, int ival);
-#endif
 
 void emitIns_S(instruction ins, emitAttr attr, int varx, int offs);
 

diff --git a/src/jit/instr.cpp b/src/jit/instr.cpp
index e9b001c..ccad416 100644 (file)
--- a/src/jit/instr.cpp
+++ b/src/jit/instr.cpp
@@ -440,7 +440,7 @@ void CodeGen::inst_RV_RV_RV(instruction ins,
 {
 #ifdef _TARGET_ARM_
     getEmitter()->emitIns_R_R_R(ins, size, reg1, reg2, reg3, flags);
-#elif defined(_TARGET_XARCH_) && defined(FEATURE_AVX_SUPPORT)
+#elif defined(_TARGET_XARCH_)
     getEmitter()->emitIns_R_R_R(ins, size, reg1, reg2, reg3);
 #else
     NYI("inst_RV_RV_RV");

diff --git a/src/jit/legacyjit/CMakeLists.txt b/src/jit/legacyjit/CMakeLists.txt
index 84fb42e..6aa95f4 100644 (file)
--- a/src/jit/legacyjit/CMakeLists.txt
+++ b/src/jit/legacyjit/CMakeLists.txt
@@ -9,7 +9,6 @@ remove_definitions(-DFEATURE_MERGE_JIT_AND_ENGINE)
 
 # No SIMD in legacy back-end.
 remove_definitions(-DFEATURE_SIMD)
-remove_definitions(-DFEATURE_AVX_SUPPORT)
 
 if(WIN32)
   add_definitions(-DFX_VER_INTERNALNAME_STR=legacyjit.dll)

diff --git a/src/jit/legacynonjit/CMakeLists.txt b/src/jit/legacynonjit/CMakeLists.txt
index 00fd9e5..4b7ef21 100644 (file)
--- a/src/jit/legacynonjit/CMakeLists.txt
+++ b/src/jit/legacynonjit/CMakeLists.txt
@@ -6,7 +6,6 @@ add_definitions(-DSELF_NO_HOST)
 remove_definitions(-DFEATURE_MERGE_JIT_AND_ENGINE)
 
 remove_definitions(-DFEATURE_SIMD)
-remove_definitions(-DFEATURE_AVX_SUPPORT)
 
 add_definitions(-DLEGACY_BACKEND)
 

diff --git a/src/jit/linuxnonjit/CMakeLists.txt b/src/jit/linuxnonjit/CMakeLists.txt
index 34899f2..23a66cb 100644 (file)
--- a/src/jit/linuxnonjit/CMakeLists.txt
+++ b/src/jit/linuxnonjit/CMakeLists.txt
@@ -11,7 +11,6 @@ endif(FEATURE_READYTORUN)
 
 if (CLR_CMAKE_PLATFORM_ARCH_I386)
     remove_definitions(-DFEATURE_SIMD)
-    remove_definitions(-DFEATURE_AVX_SUPPORT)
     add_definitions(-DUNIX_X86_ABI)
     set(JIT_ARCH_ALTJIT_SOURCES ${JIT_I386_SOURCES})
 elseif(CLR_CMAKE_PLATFORM_ARCH_AMD64)

diff --git a/src/jit/lsraxarch.cpp b/src/jit/lsraxarch.cpp
index 4fff111..24f7639 100644 (file)
--- a/src/jit/lsraxarch.cpp
+++ b/src/jit/lsraxarch.cpp
@@ -2735,7 +2735,6 @@ void LinearScan::TreeNodeInfoInitMul(GenTreePtr tree)
 //
 void LinearScan::SetContainsAVXFlags(bool isFloatingPointType /* = true */, unsigned sizeOfSIMDVector /* = 0*/)
 {
-#ifdef FEATURE_AVX_SUPPORT
     if (isFloatingPointType)
     {
         if (compiler->getFloatingPointInstructionSet() == InstructionSet_AVX)
@@ -2747,7 +2746,6 @@ void LinearScan::SetContainsAVXFlags(bool isFloatingPointType /* = true */, unsi
             compiler->getEmitter()->SetContains256bitAVX(true);
         }
     }
-#endif
 }
 
 #ifdef _TARGET_X86_

diff --git a/src/jit/protojit/protojit.nativeproj b/src/jit/protojit/protojit.nativeproj
index 3de0f0a..bea7344 100644 (file)
--- a/src/jit/protojit/protojit.nativeproj
+++ b/src/jit/protojit/protojit.nativeproj
@@ -39,7 +39,7 @@
     <LinkModuleDefinitionFile>$(OutputName).def</LinkModuleDefinitionFile>
 
     <ClDefines>$(ClDefines);ALT_JIT</ClDefines>
-    <ClDefines Condition="'$(BuildArchitecture)' == 'amd64'">$(ClDefines);FEATURE_SIMD;FEATURE_AVX_SUPPORT</ClDefines>
+    <ClDefines Condition="'$(BuildArchitecture)' == 'amd64'">$(ClDefines);FEATURE_SIMD</ClDefines>
 
     <Win32DllLibs>$(SdkLibPath)\kernel32.lib;$(SdkLibPath)\user32.lib;$(SdkLibPath)\advapi32.lib;$(SdkLibPath)\oleaut32.lib;$(SdkLibPath)\uuid.lib</Win32DllLibs>
     <Win32DllLibs>$(Win32DllLibs);$(ClrLibPath)\utilcode.lib</Win32DllLibs>

diff --git a/src/jit/protononjit/CMakeLists.txt b/src/jit/protononjit/CMakeLists.txt
index f8d9938..b8b1567 100644 (file)
--- a/src/jit/protononjit/CMakeLists.txt
+++ b/src/jit/protononjit/CMakeLists.txt
@@ -6,7 +6,6 @@ add_definitions(-DSELF_NO_HOST)
 remove_definitions(-DFEATURE_MERGE_JIT_AND_ENGINE)
 
 remove_definitions(-DFEATURE_SIMD)
-remove_definitions(-DFEATURE_AVX_SUPPORT)
 
 if(FEATURE_READYTORUN)
   add_definitions(-DFEATURE_READYTORUN_COMPILER)

diff --git a/src/jit/simdcodegenxarch.cpp b/src/jit/simdcodegenxarch.cpp
index 429cff0..d9ba775 100644 (file)
--- a/src/jit/simdcodegenxarch.cpp
+++ b/src/jit/simdcodegenxarch.cpp
@@ -671,7 +671,6 @@ void CodeGen::genSIMDScalarMove(
     var_types targetType, var_types baseType, regNumber targetReg, regNumber srcReg, SIMDScalarMoveType moveType)
 {
     assert(varTypeIsFloating(baseType));
-#ifdef FEATURE_AVX_SUPPORT
     if (compiler->getSIMDInstructionSet() == InstructionSet_AVX)
     {
         switch (moveType)
@@ -719,7 +718,6 @@ void CodeGen::genSIMDScalarMove(
         }
     }
     else
-#endif // FEATURE_AVX_SUPPORT
     {
         // SSE
 
@@ -843,13 +841,11 @@ void CodeGen::genSIMDIntrinsicInit(GenTreeSIMD* simdNode)
             ins = getOpForSIMDIntrinsic(SIMDIntrinsicBitwiseOr, baseType);
             inst_RV_RV(ins, targetReg, tmpReg, targetType, emitActualTypeSize(targetType));
 
-#ifdef FEATURE_AVX_SUPPORT
             if (compiler->canUseAVX())
             {
                 inst_RV_RV(INS_vpbroadcastq, targetReg, targetReg, TYP_SIMD32, emitTypeSize(TYP_SIMD32));
             }
             else
-#endif // FEATURE_AVX_SUPPORT
             {
                 ins = getOpForSIMDIntrinsic(SIMDIntrinsicShuffleSSE2, baseType);
                 getEmitter()->emitIns_R_R_I(ins, emitActualTypeSize(targetType), targetReg, targetReg, 0);
@@ -871,7 +867,6 @@ void CodeGen::genSIMDIntrinsicInit(GenTreeSIMD* simdNode)
             ins = getOpForSIMDIntrinsic(SIMDIntrinsicEqual, TYP_INT);
             inst_RV_RV(ins, targetReg, targetReg, targetType, emitActualTypeSize(targetType));
         }
-#ifdef FEATURE_AVX_SUPPORT
         else
         {
             assert(iset == InstructionSet_AVX);
@@ -891,7 +886,6 @@ void CodeGen::genSIMDIntrinsicInit(GenTreeSIMD* simdNode)
                 unreached();
             }
         }
-#endif // FEATURE_AVX_SUPPORT
     }
     else if (iset == InstructionSet_AVX && ((size == 32) || (size == 16)))
     {

diff --git a/src/jit/target.h b/src/jit/target.h
index fd28796..3cd5244 100644 (file)
--- a/src/jit/target.h
+++ b/src/jit/target.h
@@ -737,9 +737,9 @@ typedef unsigned short regPairNoSmall; // arm: need 12 bits
 
 #ifdef FEATURE_SIMD
   #define ALIGN_SIMD_TYPES         1       // whether SIMD type locals are to be aligned
-#if defined(UNIX_AMD64_ABI) || !defined(FEATURE_AVX_SUPPORT)
+#if defined(UNIX_AMD64_ABI)
   #define FEATURE_PARTIAL_SIMD_CALLEE_SAVE 0 // Whether SIMD registers are partially saved at calls
-#else // !UNIX_AMD64_ABI && !FEATURE_AVX_SUPPORT
+#else // !UNIX_AMD64_ABI
   #define FEATURE_PARTIAL_SIMD_CALLEE_SAVE 1 // Whether SIMD registers are partially saved at calls
 #endif // !UNIX_AMD64_ABI
 #endif

diff --git a/src/jit/utils.cpp b/src/jit/utils.cpp
index 85aec54..4e061fa 100644 (file)
--- a/src/jit/utils.cpp
+++ b/src/jit/utils.cpp
@@ -277,20 +277,20 @@ const char* getRegNameFloat(regNumber reg, var_types type)
 #define REGDEF(name, rnum, mask, sname) "x" sname,
 #include "register.h"
     };
-#ifdef FEATURE_AVX_SUPPORT
+#ifdef FEATURE_SIMD
     static const char* regNamesYMM[] = {
 #define REGDEF(name, rnum, mask, sname) "y" sname,
 #include "register.h"
     };
-#endif // FEATURE_AVX_SUPPORT
+#endif // FEATURE_SIMD
     assert((unsigned)reg < ArrLen(regNamesFloat));
 
-#ifdef FEATURE_AVX_SUPPORT
+#ifdef FEATURE_SIMD
     if (type == TYP_SIMD32)
     {
         return regNamesYMM[reg];
     }
-#endif // FEATURE_AVX_SUPPORT
+#endif // FEATURE_SIMD
 
     return regNamesFloat[reg];
 #endif

diff --git a/src/jit/vartype.h b/src/jit/vartype.h
index e75bc2a..7ec9d79 100644 (file)
--- a/src/jit/vartype.h
+++ b/src/jit/vartype.h
@@ -82,9 +82,7 @@ inline bool varTypeIsSIMD(T vt)
         case TYP_SIMD8:
         case TYP_SIMD12:
         case TYP_SIMD16:
-#ifdef FEATURE_AVX_SUPPORT
         case TYP_SIMD32:
-#endif // FEATURE_AVX_SUPPORT
             return true;
         default:
             return false;