2013-04-29 James Greenhalgh <james.greenhalgh@arm.com>
+ * config/aarch64/aarch64-builtins.c
+ (aarch64_builtin_vectorized_function): Use new names for
+ fcvt builtins.
+ * config/aarch64/aarch64-simd-builtins.def (fcvtzs): Split as...
+ (lbtruncv2sf, lbtruncv4sf, lbtruncv2df): ...This.
+ (fcvtzu): Split as...
+ (lbtruncuv2sf, lbtruncuv4sf, lbtruncuv2df): ...This.
+ (fcvtas): Split as...
+ (lroundv2sf, lroundv4sf, lroundv2df, lroundsf, lrounddf): ...This.
+ (fcvtau): Split as...
+ (lrounduv2sf, lrounduv4sf, lrounduv2df, lroundusf, lroundudf): ...This.
+ (fcvtps): Split as...
+ (lceilv2sf, lceilv4sf, lceilv2df): ...This.
+ (fcvtpu): Split as...
+ (lceiluv2sf, lceiluv4sf, lceiluv2df, lceilusf, lceiludf): ...This.
+ (fcvtms): Split as...
+ (lfloorv2sf, lfloorv4sf, lfloorv2df): ...This.
+ (fcvtmu): Split as...
+ (lflooruv2sf, lflooruv4sf, lflooruv2df, lfloorusf, lfloorudf): ...This.
+ (lfrintnv2sf, lfrintnv4sf, lfrintnv2df, lfrintnsf, lfrintndf): New.
+ (lfrintnuv2sf, lfrintnuv4sf, lfrintnuv2df): Likewise.
+ (lfrintnusf, lfrintnudf): Likewise.
+ * config/aarch64/aarch64-simd.md
+ (l<fcvt_pattern><su_optab><fcvt_target><VDQF:mode>2): Convert to
+ define_insn.
+ (aarch64_fcvt<frint_suffix><su><mode>): Remove.
+ * config/aarch64/iterators.md (FCVT): Include UNSPEC_FRINTN.
+ (fcvt_pattern): Likewise.
+
+2013-04-29 James Greenhalgh <james.greenhalgh@arm.com>
+
* config/aarch64/aarch64-simd.md
(l<fcvt_pattern><su_optab><fcvt_target><VDQF:mode>2): Rename to...
(l<fcvt_pattern><su_optab><VDQF:mode><fcvt_target>2): ... This.
BUILTIN_VDQF (UNOP, round, 2)
BUILTIN_VDQF (UNOP, frintn, 2)
- /* Implemented by aarch64_fcvt<frint_suffix><su><mode>. */
- BUILTIN_VDQF (UNOP, fcvtzs, 0)
- BUILTIN_VDQF (UNOP, fcvtzu, 0)
- BUILTIN_VDQF (UNOP, fcvtas, 0)
- BUILTIN_VDQF (UNOP, fcvtau, 0)
- BUILTIN_VDQF (UNOP, fcvtps, 0)
- BUILTIN_VDQF (UNOP, fcvtpu, 0)
- BUILTIN_VDQF (UNOP, fcvtms, 0)
- BUILTIN_VDQF (UNOP, fcvtmu, 0)
+ /* Implemented by l<fcvt_pattern><su_optab><VQDF:mode><vcvt_target>2. */
+ VAR1 (UNOP, lbtruncv2sf, 2, v2si)
+ VAR1 (UNOP, lbtruncv4sf, 2, v4si)
+ VAR1 (UNOP, lbtruncv2df, 2, v2di)
+
+ VAR1 (UNOP, lbtruncuv2sf, 2, v2si)
+ VAR1 (UNOP, lbtruncuv4sf, 2, v4si)
+ VAR1 (UNOP, lbtruncuv2df, 2, v2di)
+
+ VAR1 (UNOP, lroundv2sf, 2, v2si)
+ VAR1 (UNOP, lroundv4sf, 2, v4si)
+ VAR1 (UNOP, lroundv2df, 2, v2di)
+ /* Implemented by l<fcvt_pattern><su_optab><GPF:mode><GPI:mode>2. */
+ VAR1 (UNOP, lroundsf, 2, si)
+ VAR1 (UNOP, lrounddf, 2, di)
+
+ VAR1 (UNOP, lrounduv2sf, 2, v2si)
+ VAR1 (UNOP, lrounduv4sf, 2, v4si)
+ VAR1 (UNOP, lrounduv2df, 2, v2di)
+ VAR1 (UNOP, lroundusf, 2, si)
+ VAR1 (UNOP, lroundudf, 2, di)
+
+ VAR1 (UNOP, lceilv2sf, 2, v2si)
+ VAR1 (UNOP, lceilv4sf, 2, v4si)
+ VAR1 (UNOP, lceilv2df, 2, v2di)
+
+ VAR1 (UNOP, lceiluv2sf, 2, v2si)
+ VAR1 (UNOP, lceiluv4sf, 2, v4si)
+ VAR1 (UNOP, lceiluv2df, 2, v2di)
+ VAR1 (UNOP, lceilusf, 2, si)
+ VAR1 (UNOP, lceiludf, 2, di)
+
+ VAR1 (UNOP, lfloorv2sf, 2, v2si)
+ VAR1 (UNOP, lfloorv4sf, 2, v4si)
+ VAR1 (UNOP, lfloorv2df, 2, v2di)
+
+ VAR1 (UNOP, lflooruv2sf, 2, v2si)
+ VAR1 (UNOP, lflooruv4sf, 2, v4si)
+ VAR1 (UNOP, lflooruv2df, 2, v2di)
+ VAR1 (UNOP, lfloorusf, 2, si)
+ VAR1 (UNOP, lfloorudf, 2, di)
+
+ VAR1 (UNOP, lfrintnv2sf, 2, v2si)
+ VAR1 (UNOP, lfrintnv4sf, 2, v4si)
+ VAR1 (UNOP, lfrintnv2df, 2, v2di)
+ VAR1 (UNOP, lfrintnsf, 2, si)
+ VAR1 (UNOP, lfrintndf, 2, di)
+
+ VAR1 (UNOP, lfrintnuv2sf, 2, v2si)
+ VAR1 (UNOP, lfrintnuv4sf, 2, v4si)
+ VAR1 (UNOP, lfrintnuv2df, 2, v2di)
+ VAR1 (UNOP, lfrintnusf, 2, si)
+ VAR1 (UNOP, lfrintnudf, 2, di)
/* Implemented by
aarch64_<PERMUTE:perm_insn><PERMUTE:perm_hilo><mode>. */