drm/msm/a6xx: Fix perfcounter oob timeout

We were not programing the correct bit while clearing the perfcounter oob.
So, clear it correctly using the new 'clear' bit. This fixes the below
error:

[drm:a6xx_gmu_set_oob] *ERROR* Timeout waiting for GMU OOB set PERFCOUNTER: 0x80000000

Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org>
Link: https://lore.kernel.org/r/1617630433-36506-1-git-send-email-akhilpo@codeaurora.org
Signed-off-by: Rob Clark <robdclark@chromium.org>

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index 91cf46f..3d55e15 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -246,7 +246,7 @@ static int a6xx_gmu_hfi_start(struct a6xx_gmu *gmu)
 }
 
 struct a6xx_gmu_oob_bits {
-       int set, ack, set_new, ack_new;
+       int set, ack, set_new, ack_new, clear, clear_new;
        const char *name;
 };
 
@@ -260,6 +260,8 @@ static const struct a6xx_gmu_oob_bits a6xx_gmu_oob_bits[] = {
                .ack = 24,
                .set_new = 30,
                .ack_new = 31,
+               .clear = 24,
+               .clear_new = 31,
        },
 
        [GMU_OOB_PERFCOUNTER_SET] = {
@@ -268,18 +270,22 @@ static const struct a6xx_gmu_oob_bits a6xx_gmu_oob_bits[] = {
                .ack = 25,
                .set_new = 28,
                .ack_new = 30,
+               .clear = 25,
+               .clear_new = 29,
        },
 
        [GMU_OOB_BOOT_SLUMBER] = {
                .name = "BOOT_SLUMBER",
                .set = 22,
                .ack = 30,
+               .clear = 30,
        },
 
        [GMU_OOB_DCVS_SET] = {
                .name = "GPU_DCVS",
                .set = 23,
                .ack = 31,
+               .clear = 31,
        },
 };
 
@@ -335,9 +341,9 @@ void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state)
                return;
 
        if (gmu->legacy)
-               bit = a6xx_gmu_oob_bits[state].ack;
+               bit = a6xx_gmu_oob_bits[state].clear;
        else
-               bit = a6xx_gmu_oob_bits[state].ack_new;
+               bit = a6xx_gmu_oob_bits[state].clear_new;
 
        gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << bit);
 }