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clk: meson: axg: fix the od shift of the sys_pll
author
Yixun Lan
<yixun.lan@amlogic.com>
Fri, 19 Jan 2018 02:09:26 +0000
(10:09 +0800)
committer
Jerome Brunet
<jbrunet@baylibre.com>
Mon, 12 Feb 2018 08:49:23 +0000
(09:49 +0100)
According to the datasheet, the od shift of sys_pll is actually 16.
Fixes:
78b4af312f91
('clk: meson-axg: add clock controller drivers')
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
[fixed commit message]
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
drivers/clk/meson/axg.c
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diff --git
a/drivers/clk/meson/axg.c
b/drivers/clk/meson/axg.c
index
a1ac0ff
..
455d4d8
100644
(file)
--- a/
drivers/clk/meson/axg.c
+++ b/
drivers/clk/meson/axg.c
@@
-64,7
+64,7
@@
static struct meson_clk_pll axg_sys_pll = {
},
.od = {
.reg_off = HHI_SYS_PLL_CNTL,
- .shift = 1
0
,
+ .shift = 1
6
,
.width = 2,
},
.lock = &meson_clk_lock,