static ssize_t spramdump_show(struct device *_dev,
struct device_attribute *attr, char *buf)
{
+ /*
dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-
- //dwc_otg_dump_spram(otg_dev->core_if);
+ dwc_otg_dump_spram(otg_dev->core_if);
+ */
return sprintf(buf, "SPRAM Dump\n");
}
retval = -ENOMEM;
goto fail;
}
- dev_dbg(&_dev->dev, "base=0x%08x\n",
- (unsigned)dwc_otg_device->os_dep.base);
+ dev_dbg(&_dev->dev, "base=%p\n",
+ dwc_otg_device->os_dep.base);
#endif
/*
last = 1;
/* New DMA address - address of bounce buffer referred to in index */
- hcdma.d32 = (uint32_t) &blob->channel[n].index[i].buf[0];
+ hcdma.d32 = (uint32_t)(uintptr_t) &blob->channel[n].index[i].buf[0];
//hcdma.d32 = FIQ_READ(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n));
//hcdma.d32 += st->channel[n].dma_info.slot_len[i];
fiq_print(FIQDBG_INT, st, "LAST: %01d ", last);
/* We got an interrupt, didn't handle it. */
if (kick_irq) {
state->mphi_int_count++;
- FIQ_WRITE(state->mphi_regs.outdda, (int) state->dummy_send);
+ FIQ_WRITE(state->mphi_regs.outdda, (unsigned int)(uintptr_t) state->dummy_send);
FIQ_WRITE(state->mphi_regs.outddb, (1<<29));
}
FIQ_WRITE(state->dwc_regs_base + GINTMSK, gintmsk.d32);
/* Force a clear before another dummy send */
FIQ_WRITE(state->mphi_regs.intstat, (1<<29));
- FIQ_WRITE(state->mphi_regs.outdda, (int) state->dummy_send);
+ FIQ_WRITE(state->mphi_regs.outdda, (unsigned int)(uintptr_t) state->dummy_send);
FIQ_WRITE(state->mphi_regs.outddb, (1<<29));
}
* moderately readable array casts.
*/
hcd->fiq_dmab = DWC_DMA_ALLOC(dev, (sizeof(struct fiq_dma_channel) * num_channels), &hcd->fiq_state->dma_base);
- DWC_WARN("FIQ DMA bounce buffers: virt = 0x%08x dma = 0x%08x len=%d",
- (unsigned int)hcd->fiq_dmab, (unsigned int)hcd->fiq_state->dma_base,
- sizeof(struct fiq_dma_channel) * num_channels);
+ DWC_WARN("FIQ DMA bounce buffers: virt = %p dma = %pad len=%u",
+ hcd->fiq_dmab, &hcd->fiq_state->dma_base,
+ (uint32_t)sizeof(struct fiq_dma_channel) * num_channels);
DWC_MEMSET(hcd->fiq_dmab, 0x6b, 9024);
* state depending on transaction progress.
*/
blob = (struct fiq_dma_blob *) hcd->fiq_state->dma_base;
- st->hcdma_copy.d32 = (uint32_t) &blob->channel[hc->hc_num].index[0].buf[0];
+ st->hcdma_copy.d32 = (uint32_t)(uintptr_t) &blob->channel[hc->hc_num].index[0].buf[0];
/* Calculate the max number of CSPLITS such that the FIQ can time out
* a transaction if it fails.
*/
ptr = qtd->urb->buf + frame_desc->offset;
/* Point the HC at the DMA address of the bounce buffers */
blob = (struct fiq_dma_blob *) hcd->fiq_state->dma_base;
- st->hcdma_copy.d32 = (uint32_t) &blob->channel[hc->hc_num].index[0].buf[0];
+ st->hcdma_copy.d32 = (uint32_t)(uintptr_t) &blob->channel[hc->hc_num].index[0].buf[0];
/* fixup xfersize to the actual packet size */
st->hctsiz_copy.b.pid = 0;
dwc_list_link_t *qh_ptr;
dwc_otg_qh_t *qh;
int num_channels;
- dwc_irqflags_t flags;
dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE;
#ifdef DEBUG_HOST_CHANNELS
{
dwc_otg_transaction_type_e tr_type;
int free_qtd;
- dwc_irqflags_t flags;
-
int hog_port = 0;
DWC_DEBUGPL(DBG_HCDV, " %s: channel %d, halt_status %d, xfer_len %d\n",
dwc_otg_hcd->fiq_state->mphi_regs.outddb = otg_dev->os_dep.mphi_base + 0x2c;
dwc_otg_hcd->fiq_state->mphi_regs.intstat = otg_dev->os_dep.mphi_base + 0x50;
dwc_otg_hcd->fiq_state->dwc_regs_base = otg_dev->os_dep.base;
- DWC_WARN("MPHI regs_base at 0x%08x", (int)dwc_otg_hcd->fiq_state->mphi_regs.base);
+ DWC_WARN("MPHI regs_base at %p", dwc_otg_hcd->fiq_state->mphi_regs.base);
//Enable mphi peripheral
writel((1<<31),dwc_otg_hcd->fiq_state->mphi_regs.ctrl);
#ifdef DEBUG