LOCAL / usb: dwc_otg: remove build warnings 11/149911/2
authorSeung-Woo Kim <sw0312.kim@samsung.com>
Wed, 13 Sep 2017 12:29:31 +0000 (21:29 +0900)
committerSeung-Woo Kim <sw0312.kim@samsung.com>
Thu, 14 Sep 2017 03:48:26 +0000 (03:48 +0000)
There are build warnings for unused variable and casting from
pointer to integer of different size. Remove the build warnings.

NOTE: dwc_otg is not fully consider 64bit architecture and it
stores pointer into uint32_t variable already. This patch just
remove warnings for the converting.

Change-Id: I4182041881dbd3002f331a006e2b70a26e0b10c5
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
drivers/usb/host/dwc_otg/dwc_otg_attr.c
drivers/usb/host/dwc_otg/dwc_otg_driver.c
drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c
drivers/usb/host/dwc_otg/dwc_otg_hcd.c
drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c
drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c

index 9da0c92aaeca2fc393016442cc6578cb4a52c978..74f724582338b79cc9deb0cce6dd727735959db8 100644 (file)
@@ -918,9 +918,10 @@ DEVICE_ATTR(regdump, S_IRUGO, regdump_show, 0);
 static ssize_t spramdump_show(struct device *_dev,
                              struct device_attribute *attr, char *buf)
 {
+       /*
         dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-
-       //dwc_otg_dump_spram(otg_dev->core_if);
+       dwc_otg_dump_spram(otg_dev->core_if);
+       */
 
        return sprintf(buf, "SPRAM Dump\n");
 }
index 95943e07528276b26b51ea2d57a1f433f280aaef..63dea19e418d0c413fd93d5ba828fd56618f9508 100644 (file)
@@ -835,8 +835,8 @@ static int dwc_otg_driver_probe(
                retval = -ENOMEM;
                goto fail;
        }
-       dev_dbg(&_dev->dev, "base=0x%08x\n",
-                (unsigned)dwc_otg_device->os_dep.base);
+       dev_dbg(&_dev->dev, "base=%p\n",
+                dwc_otg_device->os_dep.base);
 #endif
 
        /*
index 0163e9cf620ba58df36a872b82cea92734baada6..9c902e8a7ae520fc89b2f354d78a642ae5e90bcc 100644 (file)
@@ -293,7 +293,7 @@ static int notrace fiq_iso_out_advance(struct fiq_state *st, int num_channels, i
                last = 1;
 
        /* New DMA address - address of bounce buffer referred to in index */
-       hcdma.d32 = (uint32_t) &blob->channel[n].index[i].buf[0];
+       hcdma.d32 = (uint32_t)(uintptr_t) &blob->channel[n].index[i].buf[0];
        //hcdma.d32 = FIQ_READ(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n));
        //hcdma.d32 += st->channel[n].dma_info.slot_len[i];
        fiq_print(FIQDBG_INT, st, "LAST: %01d ", last);
@@ -1336,7 +1336,7 @@ void notrace dwc_otg_fiq_fsm(struct fiq_state *state, int num_channels)
        /* We got an interrupt, didn't handle it. */
        if (kick_irq) {
                state->mphi_int_count++;
-               FIQ_WRITE(state->mphi_regs.outdda, (int) state->dummy_send);
+               FIQ_WRITE(state->mphi_regs.outdda, (unsigned int)(uintptr_t) state->dummy_send);
                FIQ_WRITE(state->mphi_regs.outddb, (1<<29));
 
        }
@@ -1397,7 +1397,7 @@ void notrace dwc_otg_fiq_nop(struct fiq_state *state)
                FIQ_WRITE(state->dwc_regs_base + GINTMSK, gintmsk.d32);
                /* Force a clear before another dummy send */
                FIQ_WRITE(state->mphi_regs.intstat, (1<<29));
-               FIQ_WRITE(state->mphi_regs.outdda, (int) state->dummy_send);
+               FIQ_WRITE(state->mphi_regs.outdda, (unsigned int)(uintptr_t) state->dummy_send);
                FIQ_WRITE(state->mphi_regs.outddb, (1<<29));
 
        }
index 7710370b30363e3170bf9bf522597c5f41dfb908..d237e2d817b043f5451a738d2521ff12d31037c6 100644 (file)
@@ -1027,9 +1027,9 @@ int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if)
                 * moderately readable array casts.
                 */
                hcd->fiq_dmab = DWC_DMA_ALLOC(dev, (sizeof(struct fiq_dma_channel) * num_channels), &hcd->fiq_state->dma_base);
-               DWC_WARN("FIQ DMA bounce buffers: virt = 0x%08x dma = 0x%08x len=%d",
-                               (unsigned int)hcd->fiq_dmab, (unsigned int)hcd->fiq_state->dma_base,
-                               sizeof(struct fiq_dma_channel) * num_channels);
+               DWC_WARN("FIQ DMA bounce buffers: virt = %p dma = %pad len=%u",
+                               hcd->fiq_dmab, &hcd->fiq_state->dma_base,
+                               (uint32_t)sizeof(struct fiq_dma_channel) * num_channels);
 
                DWC_MEMSET(hcd->fiq_dmab, 0x6b, 9024);
 
@@ -1510,7 +1510,7 @@ int fiq_fsm_setup_periodic_dma(dwc_otg_hcd_t *hcd, struct fiq_channel_state *st,
                 * state depending on transaction progress.
                 */
                blob = (struct fiq_dma_blob *) hcd->fiq_state->dma_base;
-               st->hcdma_copy.d32 = (uint32_t) &blob->channel[hc->hc_num].index[0].buf[0];
+               st->hcdma_copy.d32 = (uint32_t)(uintptr_t) &blob->channel[hc->hc_num].index[0].buf[0];
                /* Calculate the max number of CSPLITS such that the FIQ can time out
                 * a transaction if it fails.
                 */
@@ -1559,7 +1559,7 @@ int fiq_fsm_setup_periodic_dma(dwc_otg_hcd_t *hcd, struct fiq_channel_state *st,
                        ptr = qtd->urb->buf + frame_desc->offset;
                        /* Point the HC at the DMA address of the bounce buffers */
                        blob = (struct fiq_dma_blob *) hcd->fiq_state->dma_base;
-                       st->hcdma_copy.d32 = (uint32_t) &blob->channel[hc->hc_num].index[0].buf[0];
+                       st->hcdma_copy.d32 = (uint32_t)(uintptr_t) &blob->channel[hc->hc_num].index[0].buf[0];
 
                        /* fixup xfersize to the actual packet size */
                        st->hctsiz_copy.b.pid = 0;
@@ -2005,7 +2005,6 @@ dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd)
        dwc_list_link_t *qh_ptr;
        dwc_otg_qh_t *qh;
        int num_channels;
-       dwc_irqflags_t flags;
        dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE;
 
 #ifdef DEBUG_HOST_CHANNELS
index c8f52709a7d24974c0a38dcf1708f91073e96b0e..c7c1e5731f5ebd95f4f1a3c8181ca2def3cb98d2 100644 (file)
@@ -948,8 +948,6 @@ static void release_channel(dwc_otg_hcd_t * hcd,
 {
        dwc_otg_transaction_type_e tr_type;
        int free_qtd;
-       dwc_irqflags_t flags;
-
        int hog_port = 0;
 
        DWC_DEBUGPL(DBG_HCDV, "  %s: channel %d, halt_status %d, xfer_len %d\n",
index 992269d61ecf48126379a38e528f719009ee1d75..a46d575002d5775e9e2271d445de42c5e3b002c9 100644 (file)
@@ -483,7 +483,7 @@ static void hcd_init_fiq(void *cookie)
        dwc_otg_hcd->fiq_state->mphi_regs.outddb  = otg_dev->os_dep.mphi_base + 0x2c;
        dwc_otg_hcd->fiq_state->mphi_regs.intstat = otg_dev->os_dep.mphi_base + 0x50;
        dwc_otg_hcd->fiq_state->dwc_regs_base = otg_dev->os_dep.base;
-       DWC_WARN("MPHI regs_base at 0x%08x", (int)dwc_otg_hcd->fiq_state->mphi_regs.base);
+       DWC_WARN("MPHI regs_base at %p", dwc_otg_hcd->fiq_state->mphi_regs.base);
        //Enable mphi peripheral
        writel((1<<31),dwc_otg_hcd->fiq_state->mphi_regs.ctrl);
 #ifdef DEBUG