* lib/target-supports.exp

	(check_effective_target_arm_neon_ok_nocache): Add an option
	sequence that includes setting the ARM architecture to ARMv7-A.
	* gcc.target/arm/attr-neon.c: Use dg-add-options to add the
	command line options necessary to enable Neon support.
	* gcc.target/arm/neon-vlshr-imm-1.c: Likewise.
	* gcc.target/arm/neon-vshl-imm-1.c: Likewise.
	* gcc.target/arm/neon-vshr-imm-1.c: Likewise.
	* gcc.target/arm/pr69180.c: Likewise.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@232362 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 63976ea..ef76d22 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,15 @@
+2016-01-14  Nick Clifton  <nickc@redhat.com>
+
+       * lib/target-supports.exp
+       (check_effective_target_arm_neon_ok_nocache): Add an option
+       sequence that includes setting the ARM architecture to ARMv7-A.
+       * gcc.target/arm/attr-neon.c: Use dg-add-options to add the
+       command line options necessary to enable Neon support.
+       * gcc.target/arm/neon-vlshr-imm-1.c: Likewise.
+       * gcc.target/arm/neon-vshl-imm-1.c: Likewise.
+       * gcc.target/arm/neon-vshr-imm-1.c: Likewise.
+       * gcc.target/arm/pr69180.c: Likewise.
+
 2016-01-14  Jeff Law  <law@redhat.com>
 
        PR tree-optimization/69270

diff --git a/gcc/testsuite/gcc.target/arm/attr-neon.c b/gcc/testsuite/gcc.target/arm/attr-neon.c
index a29ea12..689e5e4 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/attr-neon.c
+++ b/gcc/testsuite/gcc.target/arm/attr-neon.c
@@ -1,6 +1,7 @@
 /* { dg-do compile } */
 /* { dg-require-effective-target arm_neon_ok } */
-/* { dg-options "-O2 -mfloat-abi=softfp -ftree-vectorize" } */
+/* { dg-options "-O2 -ftree-vectorize" } */
+/* { dg-add-options arm_neon } */
 
 /* Verify that neon instructions are emitted once.  */
 void __attribute__ ((target("fpu=neon")))

diff --git a/gcc/testsuite/gcc.target/arm/neon-vlshr-imm-1.c b/gcc/testsuite/gcc.target/arm/neon-vlshr-imm-1.c
index e666371..aaf1905 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/neon-vlshr-imm-1.c
+++ b/gcc/testsuite/gcc.target/arm/neon-vlshr-imm-1.c
@@ -1,6 +1,7 @@
 /* { dg-do compile } */
 /* { dg-require-effective-target arm_neon_ok } */
-/* { dg-options "-O2 -mfpu=neon -mfloat-abi=softfp -ftree-vectorize" } */
+/* { dg-options "-O2 -ftree-vectorize" } */
+/* { dg-add-options arm_neon } */
 /* { dg-final { scan-assembler "vshr\.u32.*#3" } } */
 
 /* Verify that VSHR immediate is used.  */

diff --git a/gcc/testsuite/gcc.target/arm/neon-vshl-imm-1.c b/gcc/testsuite/gcc.target/arm/neon-vshl-imm-1.c
index 913d595..2830c6d 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/neon-vshl-imm-1.c
+++ b/gcc/testsuite/gcc.target/arm/neon-vshl-imm-1.c
@@ -1,6 +1,7 @@
 /* { dg-do compile } */
 /* { dg-require-effective-target arm_neon_ok } */
-/* { dg-options "-O2 -mfpu=neon -mfloat-abi=softfp -ftree-vectorize" } */
+/* { dg-options "-O2 -ftree-vectorize" } */
+/* { dg-add-options arm_neon } */
 /* { dg-final { scan-assembler "vshl\.i32.*#3" } } */
 
 /* Verify that VSHR immediate is used.  */

diff --git a/gcc/testsuite/gcc.target/arm/neon-vshr-imm-1.c b/gcc/testsuite/gcc.target/arm/neon-vshr-imm-1.c
index 82a3c5c..d79e3ed 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/neon-vshr-imm-1.c
+++ b/gcc/testsuite/gcc.target/arm/neon-vshr-imm-1.c
@@ -1,6 +1,7 @@
 /* { dg-do compile } */
 /* { dg-require-effective-target arm_neon_ok } */
-/* { dg-options "-O2 -mfpu=neon -mfloat-abi=softfp -ftree-vectorize" } */
+/* { dg-options "-O2 -ftree-vectorize" } */
+/* { dg-add-options arm_neon } */
 /* { dg-final { scan-assembler "vshr\.s32.*#3" } } */
 
 /* Verify that VSHR immediate is used.  */

diff --git a/gcc/testsuite/gcc.target/arm/pr69180.c b/gcc/testsuite/gcc.target/arm/pr69180.c
index f434272..998c734 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/pr69180.c
+++ b/gcc/testsuite/gcc.target/arm/pr69180.c
@@ -3,8 +3,8 @@
    #pragma GCC target.  */
 /* { dg-do compile } */
 /* { dg-require-effective-target arm_neon_ok } */
-/* { dg-options "-mfloat-abi=softfp -mfpu=neon" } */
-
+/* { dg-options " " } */ /* Necessary to  prevent the harness from adding -ansi -pedantic-errors to the command line.  */
+/* { dg-add-options arm_neon } */
 #pragma GCC target ("fpu=neon-fp-armv8")
 
 #define __ARM_NEON_FP 0

diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 31a4f60..a930bd2 100644 (file)
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -2888,7 +2888,7 @@ proc check_effective_target_arm_neon_ok_nocache { } {
     global et_arm_neon_flags
     set et_arm_neon_flags ""
     if { [check_effective_target_arm32] } {
-       foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon" "-mfpu=neon -mfloat-abi=softfp"} {
+       foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon" "-mfpu=neon -mfloat-abi=softfp" "-mfpu=neon -mfloat-abi=softfp -march=armv7-a"} {
            if { [check_no_compiler_messages_nocache arm_neon_ok object {
                int dummy;
                #ifndef __ARM_NEON__